arch/arm/dts/mt7981.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7981-clk.h>
  10 #include <dt-bindings/reset/mt7629-reset.h>
  11 #include <dt-bindings/pinctrl/mt65xx.h>
  12
  13 / {
  14         compatible = "mediatek,mt7981";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a53";
  24                         reg = <0x0>;
  25                         mediatek,hwver = <&hwver>;
  26                 };
  27                 cpu1: cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a53";
  30                         reg = <0x1>;
  31                         mediatek,hwver = <&hwver>;
  32                 };
  33         };
  34
  35         gpt_clk: gpt_dummy20m {
  36                 compatible = "fixed-clock";
  37                 clock-frequency = <13000000>;
  38                 #clock-cells = <0>;
  39                 bootph-all;
  40         };
  41
  42         hwver: hwver {
  43                 compatible = "mediatek,hwver", "syscon";
  44                 reg = <0x8000000 0x1000>;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv8-timer";
  49                 interrupt-parent = <&gic>;
  50                 clock-frequency = <13000000>;
  51                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  52                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  53                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  54                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  55                 arm,cpu-registers-not-fw-configured;
  56         };
  57
  58         timer0: timer@10008000 {
  59                 compatible = "mediatek,mt7986-timer";
  60                 reg = <0x10008000 0x1000>;
  61                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  62                 clocks = <&gpt_clk>;
  63                 clock-names = "gpt-clk";
  64                 bootph-all;
  65         };
  66
  67         watchdog: watchdog@1001c000 {
  68                 compatible = "mediatek,mt7986-wdt";
  69                 reg = <0x1001c000 0x1000>;
  70                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  71                 #reset-cells = <1>;
  72                 status = "disabled";
  73         };
  74
  75         gic: interrupt-controller@c000000 {
  76                 compatible = "arm,gic-v3";
  77                 #interrupt-cells = <3>;
  78                 interrupt-parent = <&gic>;
  79                 interrupt-controller;
  80                 reg = <0x0c000000 0x40000>,  /* GICD */
  81                       <0x0c080000 0x200000>; /* GICR */
  82
  83                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  84         };
  85
  86         fixed_plls: apmixedsys@1001e000 {
  87                 compatible = "mediatek,mt7981-fixed-plls";
  88                 reg = <0x1001e000 0x1000>;
  89                 #clock-cells = <1>;
  90                 bootph-all;
  91         };
  92
  93         topckgen: topckgen@1001b000 {
  94                 compatible = "mediatek,mt7981-topckgen";
  95                 reg = <0x1001b000 0x1000>;
  96                 clock-parent = <&fixed_plls>;
  97                 #clock-cells = <1>;
  98                 bootph-all;
  99         };
 100
 101         infracfg_ao: infracfg_ao@10001000 {
 102                 compatible = "mediatek,mt7981-infracfg_ao";
 103                 reg = <0x10001000 0x80>;
 104                 clock-parent = <&infracfg>;
 105                 #clock-cells = <1>;
 106                 bootph-all;
 107         };
 108
 109         infracfg: infracfg@10001000 {
 110                 compatible = "mediatek,mt7981-infracfg";
 111                 reg = <0x10001000 0x30>;
 112                 clock-parent = <&topckgen>;
 113                 #clock-cells = <1>;
 114                 bootph-all;
 115         };
 116
 117         pinctrl: pinctrl@11d00000 {
 118                 compatible = "mediatek,mt7981-pinctrl";
 119                 reg = <0x11d00000 0x1000>,
 120                       <0x11c00000 0x1000>,
 121                       <0x11c10000 0x1000>,
 122                       <0x11d20000 0x1000>,
 123                       <0x11e00000 0x1000>,
 124                       <0x11e20000 0x1000>,
 125                       <0x11f00000 0x1000>,
 126                       <0x11f10000 0x1000>,
 127                       <0x1000b000 0x1000>;
 128                 reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
 129                             "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
 130                             "iocfg_tm_base", "iocfg_tl_base", "eint";
 131                 gpio: gpio-controller {
 132                         gpio-controller;
 133                         #gpio-cells = <2>;
 134                 };
 135         };
 136
 137         pwm: pwm@10048000 {
 138                 compatible = "mediatek,mt7981-pwm";
 139                 reg = <0x10048000 0x1000>;
 140                 #clock-cells = <1>;
 141                 #pwm-cells = <2>;
 142                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 143                 clocks = <&infracfg CK_INFRA_PWM>,
 144                          <&infracfg_ao CK_INFRA_PWM_BSEL>,
 145                          <&infracfg_ao CK_INFRA_PWM1_CK>,
 146                          <&infracfg_ao CK_INFRA_PWM2_CK>,
 147                          /* FIXME */
 148                          <&infracfg_ao CK_INFRA_PWM2_CK>;
 149                 assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
 150                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
 151                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
 152                 status = "disabled";
 153         };
 154
 155         uart0: serial@11002000 {
 156                 compatible = "mediatek,hsuart";
 157                 reg = <0x11002000 0x400>;
 158                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
 160                 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 161                                   <&infracfg_ao CK_INFRA_UART0_SEL>;
 162                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
 163                                          <&infracfg CK_INFRA_UART>;
 164                 mediatek,force-highspeed;
 165                 status = "disabled";
 166                 bootph-all;
 167         };
 168
 169         uart1: serial@11003000 {
 170                 compatible = "mediatek,hsuart";
 171                 reg = <0x11003000 0x400>;
 172                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
 174                 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 175                                   <&infracfg_ao CK_INFRA_UART1_SEL>;
 176                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
 177                                          <&infracfg CK_INFRA_UART>;
 178                 mediatek,force-highspeed;
 179                 status = "disabled";
 180         };
 181
 182         uart2: serial@11004000 {
 183                 compatible = "mediatek,hsuart";
 184                 reg = <0x11004000 0x400>;
 185                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
 187                 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
 188                                   <&infracfg_ao CK_INFRA_UART2_SEL>;
 189                 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
 190                                          <&infracfg CK_INFRA_UART>;
 191                 mediatek,force-highspeed;
 192                 status = "disabled";
 193         };
 194
 195         snand: snand@11005000 {
 196                 compatible = "mediatek,mt7986-snand";
 197                 reg = <0x11005000 0x1000>,
 198                       <0x11006000 0x1000>;
 199                 reg-names = "nfi", "ecc";
 200                 clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
 201                          <&infracfg_ao CK_INFRA_NFI1_CK>,
 202                          <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
 203                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 204                 assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
 205                                   <&topckgen CK_TOP_NFI1X_SEL>;
 206                 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
 207                                          <&topckgen CK_TOP_CB_M_D8>;
 208                 status = "disabled";
 209         };
 210
 211         ethsys: syscon@15000000 {
 212                 compatible = "mediatek,mt7981-ethsys", "syscon";
 213                 reg = <0x15000000 0x1000>;
 214                 clock-parent = <&topckgen>;
 215                 #clock-cells = <1>;
 216                 #reset-cells = <1>;
 217         };
 218
 219         eth: ethernet@15100000 {
 220                 compatible = "mediatek,mt7981-eth", "syscon";
 221                 reg = <0x15100000 0x20000>;
 222                 resets = <&ethsys ETHSYS_FE_RST>;
 223                 reset-names = "fe";
 224                 mediatek,ethsys = <&ethsys>;
 225                 mediatek,sgmiisys = <&sgmiisys0>;
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 status = "disabled";
 229         };
 230
 231         sgmiisys0: syscon@10060000 {
 232                 compatible = "mediatek,mt7986-sgmiisys", "syscon";
 233                 reg = <0x10060000 0x1000>;
 234                 pn_swap;
 235                 #clock-cells = <1>;
 236         };
 237
 238         sgmiisys1: syscon@10070000 {
 239                 compatible = "mediatek,mt7986-sgmiisys", "syscon";
 240                 reg = <0x10070000 0x1000>;
 241                 #clock-cells = <1>;
 242         };
 243
 244         spi0: spi@1100a000 {
 245                 compatible = "mediatek,ipm-spi";
 246                 reg = <0x1100a000 0x100>;
 247                 clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
 248                          <&topckgen CK_TOP_SPI_SEL>;
 249                 assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
 250                                   <&infracfg CK_INFRA_SPI0_SEL>;
 251                 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
 252                                          <&topckgen CK_INFRA_ISPI0>;
 253                 clock-names = "sel-clk", "spi-clk";
 254                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 255                 status = "disabled";
 256         };
 257
 258         spi1: spi@1100b000 {
 259                 compatible = "mediatek,ipm-spi";
 260                 reg = <0x1100b000 0x100>;
 261                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 262                 status = "disabled";
 263         };
 264
 265         spi2: spi@11009000 {
 266                 compatible = "mediatek,ipm-spi";
 267                 reg = <0x11009000 0x100>;
 268                 clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
 269                          <&topckgen CK_TOP_SPI_SEL>;
 270                 assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
 271                                   <&infracfg CK_INFRA_SPI0_SEL>;
 272                 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
 273                                          <&topckgen CK_INFRA_ISPI0>;
 274                 clock-names = "sel-clk", "spi-clk";
 275                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 276                 status = "disabled";
 277         };
 278
 279         mmc0: mmc@11230000 {
 280                 compatible = "mediatek,mt7981-mmc";
 281                 reg = <0x11230000 0x1000>,
 282                       <0x11C20000 0x1000>;
 283                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 284                 clocks = <&topckgen CK_TOP_EMMC_400M>,
 285                          <&topckgen CK_TOP_EMMC_208M>,
 286                          <&infracfg_ao CK_INFRA_MSDC_CK>;
 287                 assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
 288                                   <&topckgen CK_TOP_EMMC_208M_SEL>;
 289                 assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
 290                                          <&topckgen CK_TOP_CB_M_D2>;
 291                 clock-names = "source", "hclk", "source_cg";
 292                 status = "disabled";
 293         };
 294
 295 };