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Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians...
[thirdparty/u-boot.git] / arch / arm / dts / r8a7795.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car H3 (R8A77950) SoC
4 *
5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
11
12 #define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4
13
14 / {
15 compatible = "renesas,r8a7795";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 i2c5 = &i2c5;
26 i2c6 = &i2c6;
27 i2c7 = &i2c_dvfs;
28 };
29
30 /*
31 * The external audio clocks are configured as 0 Hz fixed frequency
32 * clocks by default.
33 * Boards that provide audio clocks should override them.
34 */
35 audio_clk_a: audio_clk_a {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
39 };
40
41 audio_clk_b: audio_clk_b {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 };
46
47 audio_clk_c: audio_clk_c {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <0>;
51 };
52
53 /* External CAN clock - to be overridden by boards that provide it */
54 can_clk: can {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 };
59
60 cluster0_opp: opp_table0 {
61 compatible = "operating-points-v2";
62 opp-shared;
63
64 opp-500000000 {
65 opp-hz = /bits/ 64 <500000000>;
66 opp-microvolt = <830000>;
67 clock-latency-ns = <300000>;
68 };
69 opp-1000000000 {
70 opp-hz = /bits/ 64 <1000000000>;
71 opp-microvolt = <830000>;
72 clock-latency-ns = <300000>;
73 };
74 opp-1500000000 {
75 opp-hz = /bits/ 64 <1500000000>;
76 opp-microvolt = <830000>;
77 clock-latency-ns = <300000>;
78 opp-suspend;
79 };
80 opp-1600000000 {
81 opp-hz = /bits/ 64 <1600000000>;
82 opp-microvolt = <900000>;
83 clock-latency-ns = <300000>;
84 turbo-mode;
85 };
86 opp-1700000000 {
87 opp-hz = /bits/ 64 <1700000000>;
88 opp-microvolt = <960000>;
89 clock-latency-ns = <300000>;
90 turbo-mode;
91 };
92 };
93
94 cluster1_opp: opp_table1 {
95 compatible = "operating-points-v2";
96 opp-shared;
97
98 opp-800000000 {
99 opp-hz = /bits/ 64 <800000000>;
100 opp-microvolt = <820000>;
101 clock-latency-ns = <300000>;
102 };
103 opp-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <820000>;
106 clock-latency-ns = <300000>;
107 };
108 opp-1200000000 {
109 opp-hz = /bits/ 64 <1200000000>;
110 opp-microvolt = <820000>;
111 clock-latency-ns = <300000>;
112 };
113 };
114
115 cpus {
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 cpu-map {
120 cluster0 {
121 core0 {
122 cpu = <&a57_0>;
123 };
124 core1 {
125 cpu = <&a57_1>;
126 };
127 core2 {
128 cpu = <&a57_2>;
129 };
130 core3 {
131 cpu = <&a57_3>;
132 };
133 };
134
135 cluster1 {
136 core0 {
137 cpu = <&a53_0>;
138 };
139 core1 {
140 cpu = <&a53_1>;
141 };
142 core2 {
143 cpu = <&a53_2>;
144 };
145 core3 {
146 cpu = <&a53_3>;
147 };
148 };
149 };
150
151 a57_0: cpu@0 {
152 compatible = "arm,cortex-a57";
153 reg = <0x0>;
154 device_type = "cpu";
155 power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
156 next-level-cache = <&L2_CA57>;
157 enable-method = "psci";
158 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
159 operating-points-v2 = <&cluster0_opp>;
160 capacity-dmips-mhz = <1024>;
161 #cooling-cells = <2>;
162 };
163
164 a57_1: cpu@1 {
165 compatible = "arm,cortex-a57";
166 reg = <0x1>;
167 device_type = "cpu";
168 power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
169 next-level-cache = <&L2_CA57>;
170 enable-method = "psci";
171 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
172 operating-points-v2 = <&cluster0_opp>;
173 capacity-dmips-mhz = <1024>;
174 #cooling-cells = <2>;
175 };
176
177 a57_2: cpu@2 {
178 compatible = "arm,cortex-a57";
179 reg = <0x2>;
180 device_type = "cpu";
181 power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
182 next-level-cache = <&L2_CA57>;
183 enable-method = "psci";
184 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
185 operating-points-v2 = <&cluster0_opp>;
186 capacity-dmips-mhz = <1024>;
187 #cooling-cells = <2>;
188 };
189
190 a57_3: cpu@3 {
191 compatible = "arm,cortex-a57";
192 reg = <0x3>;
193 device_type = "cpu";
194 power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
195 next-level-cache = <&L2_CA57>;
196 enable-method = "psci";
197 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
198 operating-points-v2 = <&cluster0_opp>;
199 capacity-dmips-mhz = <1024>;
200 #cooling-cells = <2>;
201 };
202
203 a53_0: cpu@100 {
204 compatible = "arm,cortex-a53";
205 reg = <0x100>;
206 device_type = "cpu";
207 power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
208 next-level-cache = <&L2_CA53>;
209 enable-method = "psci";
210 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
211 operating-points-v2 = <&cluster1_opp>;
212 capacity-dmips-mhz = <535>;
213 };
214
215 a53_1: cpu@101 {
216 compatible = "arm,cortex-a53";
217 reg = <0x101>;
218 device_type = "cpu";
219 power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
220 next-level-cache = <&L2_CA53>;
221 enable-method = "psci";
222 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
223 operating-points-v2 = <&cluster1_opp>;
224 capacity-dmips-mhz = <535>;
225 };
226
227 a53_2: cpu@102 {
228 compatible = "arm,cortex-a53";
229 reg = <0x102>;
230 device_type = "cpu";
231 power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
232 next-level-cache = <&L2_CA53>;
233 enable-method = "psci";
234 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
235 operating-points-v2 = <&cluster1_opp>;
236 capacity-dmips-mhz = <535>;
237 };
238
239 a53_3: cpu@103 {
240 compatible = "arm,cortex-a53";
241 reg = <0x103>;
242 device_type = "cpu";
243 power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
244 next-level-cache = <&L2_CA53>;
245 enable-method = "psci";
246 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
247 operating-points-v2 = <&cluster1_opp>;
248 capacity-dmips-mhz = <535>;
249 };
250
251 L2_CA57: cache-controller-0 {
252 compatible = "cache";
253 power-domains = <&sysc R8A7795_PD_CA57_SCU>;
254 cache-unified;
255 cache-level = <2>;
256 };
257
258 L2_CA53: cache-controller-1 {
259 compatible = "cache";
260 power-domains = <&sysc R8A7795_PD_CA53_SCU>;
261 cache-unified;
262 cache-level = <2>;
263 };
264 };
265
266 extal_clk: extal {
267 compatible = "fixed-clock";
268 #clock-cells = <0>;
269 /* This value must be overridden by the board */
270 clock-frequency = <0>;
271 };
272
273 extalr_clk: extalr {
274 compatible = "fixed-clock";
275 #clock-cells = <0>;
276 /* This value must be overridden by the board */
277 clock-frequency = <0>;
278 };
279
280 /* External PCIe clock - can be overridden by the board */
281 pcie_bus_clk: pcie_bus {
282 compatible = "fixed-clock";
283 #clock-cells = <0>;
284 clock-frequency = <0>;
285 };
286
287 pmu_a53 {
288 compatible = "arm,cortex-a53-pmu";
289 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
290 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
291 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
292 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-affinity = <&a53_0>,
294 <&a53_1>,
295 <&a53_2>,
296 <&a53_3>;
297 };
298
299 pmu_a57 {
300 compatible = "arm,cortex-a57-pmu";
301 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
302 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
303 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
304 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-affinity = <&a57_0>,
306 <&a57_1>,
307 <&a57_2>,
308 <&a57_3>;
309 };
310
311 psci {
312 compatible = "arm,psci-1.0", "arm,psci-0.2";
313 method = "smc";
314 };
315
316 /* External SCIF clock - to be overridden by boards that provide it */
317 scif_clk: scif {
318 compatible = "fixed-clock";
319 #clock-cells = <0>;
320 clock-frequency = <0>;
321 };
322
323 soc: soc {
324 compatible = "simple-bus";
325 interrupt-parent = <&gic>;
326
327 #address-cells = <2>;
328 #size-cells = <2>;
329 ranges;
330
331 rwdt: watchdog@e6020000 {
332 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
333 reg = <0 0xe6020000 0 0x0c>;
334 clocks = <&cpg CPG_MOD 402>;
335 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
336 resets = <&cpg 402>;
337 status = "disabled";
338 };
339
340 gpio0: gpio@e6050000 {
341 compatible = "renesas,gpio-r8a7795",
342 "renesas,rcar-gen3-gpio";
343 reg = <0 0xe6050000 0 0x50>;
344 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
345 #gpio-cells = <2>;
346 gpio-controller;
347 gpio-ranges = <&pfc 0 0 16>;
348 #interrupt-cells = <2>;
349 interrupt-controller;
350 clocks = <&cpg CPG_MOD 912>;
351 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
352 resets = <&cpg 912>;
353 };
354
355 gpio1: gpio@e6051000 {
356 compatible = "renesas,gpio-r8a7795",
357 "renesas,rcar-gen3-gpio";
358 reg = <0 0xe6051000 0 0x50>;
359 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
360 #gpio-cells = <2>;
361 gpio-controller;
362 gpio-ranges = <&pfc 0 32 29>;
363 #interrupt-cells = <2>;
364 interrupt-controller;
365 clocks = <&cpg CPG_MOD 911>;
366 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
367 resets = <&cpg 911>;
368 };
369
370 gpio2: gpio@e6052000 {
371 compatible = "renesas,gpio-r8a7795",
372 "renesas,rcar-gen3-gpio";
373 reg = <0 0xe6052000 0 0x50>;
374 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
375 #gpio-cells = <2>;
376 gpio-controller;
377 gpio-ranges = <&pfc 0 64 15>;
378 #interrupt-cells = <2>;
379 interrupt-controller;
380 clocks = <&cpg CPG_MOD 910>;
381 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
382 resets = <&cpg 910>;
383 };
384
385 gpio3: gpio@e6053000 {
386 compatible = "renesas,gpio-r8a7795",
387 "renesas,rcar-gen3-gpio";
388 reg = <0 0xe6053000 0 0x50>;
389 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
390 #gpio-cells = <2>;
391 gpio-controller;
392 gpio-ranges = <&pfc 0 96 16>;
393 #interrupt-cells = <2>;
394 interrupt-controller;
395 clocks = <&cpg CPG_MOD 909>;
396 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
397 resets = <&cpg 909>;
398 };
399
400 gpio4: gpio@e6054000 {
401 compatible = "renesas,gpio-r8a7795",
402 "renesas,rcar-gen3-gpio";
403 reg = <0 0xe6054000 0 0x50>;
404 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
405 #gpio-cells = <2>;
406 gpio-controller;
407 gpio-ranges = <&pfc 0 128 18>;
408 #interrupt-cells = <2>;
409 interrupt-controller;
410 clocks = <&cpg CPG_MOD 908>;
411 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
412 resets = <&cpg 908>;
413 };
414
415 gpio5: gpio@e6055000 {
416 compatible = "renesas,gpio-r8a7795",
417 "renesas,rcar-gen3-gpio";
418 reg = <0 0xe6055000 0 0x50>;
419 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
420 #gpio-cells = <2>;
421 gpio-controller;
422 gpio-ranges = <&pfc 0 160 26>;
423 #interrupt-cells = <2>;
424 interrupt-controller;
425 clocks = <&cpg CPG_MOD 907>;
426 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
427 resets = <&cpg 907>;
428 };
429
430 gpio6: gpio@e6055400 {
431 compatible = "renesas,gpio-r8a7795",
432 "renesas,rcar-gen3-gpio";
433 reg = <0 0xe6055400 0 0x50>;
434 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
435 #gpio-cells = <2>;
436 gpio-controller;
437 gpio-ranges = <&pfc 0 192 32>;
438 #interrupt-cells = <2>;
439 interrupt-controller;
440 clocks = <&cpg CPG_MOD 906>;
441 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
442 resets = <&cpg 906>;
443 };
444
445 gpio7: gpio@e6055800 {
446 compatible = "renesas,gpio-r8a7795",
447 "renesas,rcar-gen3-gpio";
448 reg = <0 0xe6055800 0 0x50>;
449 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
450 #gpio-cells = <2>;
451 gpio-controller;
452 gpio-ranges = <&pfc 0 224 4>;
453 #interrupt-cells = <2>;
454 interrupt-controller;
455 clocks = <&cpg CPG_MOD 905>;
456 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
457 resets = <&cpg 905>;
458 };
459
460 pfc: pin-controller@e6060000 {
461 compatible = "renesas,pfc-r8a7795";
462 reg = <0 0xe6060000 0 0x50c>;
463 };
464
465 cmt0: timer@e60f0000 {
466 compatible = "renesas,r8a7795-cmt0",
467 "renesas,rcar-gen3-cmt0";
468 reg = <0 0xe60f0000 0 0x1004>;
469 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&cpg CPG_MOD 303>;
472 clock-names = "fck";
473 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
474 resets = <&cpg 303>;
475 status = "disabled";
476 };
477
478 cmt1: timer@e6130000 {
479 compatible = "renesas,r8a7795-cmt1",
480 "renesas,rcar-gen3-cmt1";
481 reg = <0 0xe6130000 0 0x1004>;
482 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cpg CPG_MOD 302>;
491 clock-names = "fck";
492 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
493 resets = <&cpg 302>;
494 status = "disabled";
495 };
496
497 cmt2: timer@e6140000 {
498 compatible = "renesas,r8a7795-cmt1",
499 "renesas,rcar-gen3-cmt1";
500 reg = <0 0xe6140000 0 0x1004>;
501 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&cpg CPG_MOD 301>;
510 clock-names = "fck";
511 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
512 resets = <&cpg 301>;
513 status = "disabled";
514 };
515
516 cmt3: timer@e6148000 {
517 compatible = "renesas,r8a7795-cmt1",
518 "renesas,rcar-gen3-cmt1";
519 reg = <0 0xe6148000 0 0x1004>;
520 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cpg CPG_MOD 300>;
529 clock-names = "fck";
530 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
531 resets = <&cpg 300>;
532 status = "disabled";
533 };
534
535 cpg: clock-controller@e6150000 {
536 compatible = "renesas,r8a7795-cpg-mssr";
537 reg = <0 0xe6150000 0 0x1000>;
538 clocks = <&extal_clk>, <&extalr_clk>;
539 clock-names = "extal", "extalr";
540 #clock-cells = <2>;
541 #power-domain-cells = <0>;
542 #reset-cells = <1>;
543 };
544
545 rst: reset-controller@e6160000 {
546 compatible = "renesas,r8a7795-rst";
547 reg = <0 0xe6160000 0 0x0200>;
548 };
549
550 sysc: system-controller@e6180000 {
551 compatible = "renesas,r8a7795-sysc";
552 reg = <0 0xe6180000 0 0x0400>;
553 #power-domain-cells = <1>;
554 };
555
556 tsc: thermal@e6198000 {
557 compatible = "renesas,r8a7795-thermal";
558 reg = <0 0xe6198000 0 0x100>,
559 <0 0xe61a0000 0 0x100>,
560 <0 0xe61a8000 0 0x100>;
561 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&cpg CPG_MOD 522>;
565 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
566 resets = <&cpg 522>;
567 #thermal-sensor-cells = <1>;
568 };
569
570 intc_ex: interrupt-controller@e61c0000 {
571 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";
572 #interrupt-cells = <2>;
573 interrupt-controller;
574 reg = <0 0xe61c0000 0 0x200>;
575 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
576 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
577 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
578 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
579 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
580 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cpg CPG_MOD 407>;
582 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
583 resets = <&cpg 407>;
584 };
585
586 i2c0: i2c@e6500000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "renesas,i2c-r8a7795",
590 "renesas,rcar-gen3-i2c";
591 reg = <0 0xe6500000 0 0x40>;
592 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cpg CPG_MOD 931>;
594 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
595 resets = <&cpg 931>;
596 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
597 <&dmac2 0x91>, <&dmac2 0x90>;
598 dma-names = "tx", "rx", "tx", "rx";
599 i2c-scl-internal-delay-ns = <110>;
600 status = "disabled";
601 };
602
603 i2c1: i2c@e6508000 {
604 #address-cells = <1>;
605 #size-cells = <0>;
606 compatible = "renesas,i2c-r8a7795",
607 "renesas,rcar-gen3-i2c";
608 reg = <0 0xe6508000 0 0x40>;
609 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cpg CPG_MOD 930>;
611 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
612 resets = <&cpg 930>;
613 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
614 <&dmac2 0x93>, <&dmac2 0x92>;
615 dma-names = "tx", "rx", "tx", "rx";
616 i2c-scl-internal-delay-ns = <6>;
617 status = "disabled";
618 };
619
620 i2c2: i2c@e6510000 {
621 #address-cells = <1>;
622 #size-cells = <0>;
623 compatible = "renesas,i2c-r8a7795",
624 "renesas,rcar-gen3-i2c";
625 reg = <0 0xe6510000 0 0x40>;
626 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&cpg CPG_MOD 929>;
628 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
629 resets = <&cpg 929>;
630 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
631 <&dmac2 0x95>, <&dmac2 0x94>;
632 dma-names = "tx", "rx", "tx", "rx";
633 i2c-scl-internal-delay-ns = <6>;
634 status = "disabled";
635 };
636
637 i2c3: i2c@e66d0000 {
638 #address-cells = <1>;
639 #size-cells = <0>;
640 compatible = "renesas,i2c-r8a7795",
641 "renesas,rcar-gen3-i2c";
642 reg = <0 0xe66d0000 0 0x40>;
643 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&cpg CPG_MOD 928>;
645 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
646 resets = <&cpg 928>;
647 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
648 dma-names = "tx", "rx";
649 i2c-scl-internal-delay-ns = <110>;
650 status = "disabled";
651 };
652
653 i2c4: i2c@e66d8000 {
654 #address-cells = <1>;
655 #size-cells = <0>;
656 compatible = "renesas,i2c-r8a7795",
657 "renesas,rcar-gen3-i2c";
658 reg = <0 0xe66d8000 0 0x40>;
659 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&cpg CPG_MOD 927>;
661 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
662 resets = <&cpg 927>;
663 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
664 dma-names = "tx", "rx";
665 i2c-scl-internal-delay-ns = <110>;
666 status = "disabled";
667 };
668
669 i2c5: i2c@e66e0000 {
670 #address-cells = <1>;
671 #size-cells = <0>;
672 compatible = "renesas,i2c-r8a7795",
673 "renesas,rcar-gen3-i2c";
674 reg = <0 0xe66e0000 0 0x40>;
675 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&cpg CPG_MOD 919>;
677 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
678 resets = <&cpg 919>;
679 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
680 dma-names = "tx", "rx";
681 i2c-scl-internal-delay-ns = <110>;
682 status = "disabled";
683 };
684
685 i2c6: i2c@e66e8000 {
686 #address-cells = <1>;
687 #size-cells = <0>;
688 compatible = "renesas,i2c-r8a7795",
689 "renesas,rcar-gen3-i2c";
690 reg = <0 0xe66e8000 0 0x40>;
691 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&cpg CPG_MOD 918>;
693 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
694 resets = <&cpg 918>;
695 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
696 dma-names = "tx", "rx";
697 i2c-scl-internal-delay-ns = <6>;
698 status = "disabled";
699 };
700
701 i2c_dvfs: i2c@e60b0000 {
702 #address-cells = <1>;
703 #size-cells = <0>;
704 compatible = "renesas,iic-r8a7795",
705 "renesas,rcar-gen3-iic",
706 "renesas,rmobile-iic";
707 reg = <0 0xe60b0000 0 0x425>;
708 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cpg CPG_MOD 926>;
710 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
711 resets = <&cpg 926>;
712 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
713 dma-names = "tx", "rx";
714 status = "disabled";
715 };
716
717 hscif0: serial@e6540000 {
718 compatible = "renesas,hscif-r8a7795",
719 "renesas,rcar-gen3-hscif",
720 "renesas,hscif";
721 reg = <0 0xe6540000 0 96>;
722 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&cpg CPG_MOD 520>,
724 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
725 <&scif_clk>;
726 clock-names = "fck", "brg_int", "scif_clk";
727 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
728 <&dmac2 0x31>, <&dmac2 0x30>;
729 dma-names = "tx", "rx", "tx", "rx";
730 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
731 resets = <&cpg 520>;
732 status = "disabled";
733 };
734
735 hscif1: serial@e6550000 {
736 compatible = "renesas,hscif-r8a7795",
737 "renesas,rcar-gen3-hscif",
738 "renesas,hscif";
739 reg = <0 0xe6550000 0 96>;
740 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cpg CPG_MOD 519>,
742 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
743 <&scif_clk>;
744 clock-names = "fck", "brg_int", "scif_clk";
745 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
746 <&dmac2 0x33>, <&dmac2 0x32>;
747 dma-names = "tx", "rx", "tx", "rx";
748 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
749 resets = <&cpg 519>;
750 status = "disabled";
751 };
752
753 hscif2: serial@e6560000 {
754 compatible = "renesas,hscif-r8a7795",
755 "renesas,rcar-gen3-hscif",
756 "renesas,hscif";
757 reg = <0 0xe6560000 0 96>;
758 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&cpg CPG_MOD 518>,
760 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
761 <&scif_clk>;
762 clock-names = "fck", "brg_int", "scif_clk";
763 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
764 <&dmac2 0x35>, <&dmac2 0x34>;
765 dma-names = "tx", "rx", "tx", "rx";
766 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
767 resets = <&cpg 518>;
768 status = "disabled";
769 };
770
771 hscif3: serial@e66a0000 {
772 compatible = "renesas,hscif-r8a7795",
773 "renesas,rcar-gen3-hscif",
774 "renesas,hscif";
775 reg = <0 0xe66a0000 0 96>;
776 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&cpg CPG_MOD 517>,
778 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
779 <&scif_clk>;
780 clock-names = "fck", "brg_int", "scif_clk";
781 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
782 dma-names = "tx", "rx";
783 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
784 resets = <&cpg 517>;
785 status = "disabled";
786 };
787
788 hscif4: serial@e66b0000 {
789 compatible = "renesas,hscif-r8a7795",
790 "renesas,rcar-gen3-hscif",
791 "renesas,hscif";
792 reg = <0 0xe66b0000 0 96>;
793 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&cpg CPG_MOD 516>,
795 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
796 <&scif_clk>;
797 clock-names = "fck", "brg_int", "scif_clk";
798 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
799 dma-names = "tx", "rx";
800 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
801 resets = <&cpg 516>;
802 status = "disabled";
803 };
804
805 hsusb: usb@e6590000 {
806 compatible = "renesas,usbhs-r8a7795",
807 "renesas,rcar-gen3-usbhs";
808 reg = <0 0xe6590000 0 0x200>;
809 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
811 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
812 <&usb_dmac1 0>, <&usb_dmac1 1>;
813 dma-names = "ch0", "ch1", "ch2", "ch3";
814 renesas,buswait = <11>;
815 phys = <&usb2_phy0>;
816 phy-names = "usb";
817 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
818 resets = <&cpg 704>, <&cpg 703>;
819 status = "disabled";
820 };
821
822 hsusb3: usb@e659c000 {
823 compatible = "renesas,usbhs-r8a7795",
824 "renesas,rcar-gen3-usbhs";
825 reg = <0 0xe659c000 0 0x200>;
826 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
828 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
829 <&usb_dmac3 0>, <&usb_dmac3 1>;
830 dma-names = "ch0", "ch1", "ch2", "ch3";
831 renesas,buswait = <11>;
832 phys = <&usb2_phy3>;
833 phy-names = "usb";
834 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
835 resets = <&cpg 705>, <&cpg 700>;
836 status = "disabled";
837 };
838
839 usb_dmac0: dma-controller@e65a0000 {
840 compatible = "renesas,r8a7795-usb-dmac",
841 "renesas,usb-dmac";
842 reg = <0 0xe65a0000 0 0x100>;
843 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
844 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
845 interrupt-names = "ch0", "ch1";
846 clocks = <&cpg CPG_MOD 330>;
847 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
848 resets = <&cpg 330>;
849 #dma-cells = <1>;
850 dma-channels = <2>;
851 };
852
853 usb_dmac1: dma-controller@e65b0000 {
854 compatible = "renesas,r8a7795-usb-dmac",
855 "renesas,usb-dmac";
856 reg = <0 0xe65b0000 0 0x100>;
857 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
858 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
859 interrupt-names = "ch0", "ch1";
860 clocks = <&cpg CPG_MOD 331>;
861 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
862 resets = <&cpg 331>;
863 #dma-cells = <1>;
864 dma-channels = <2>;
865 };
866
867 usb_dmac2: dma-controller@e6460000 {
868 compatible = "renesas,r8a7795-usb-dmac",
869 "renesas,usb-dmac";
870 reg = <0 0xe6460000 0 0x100>;
871 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
872 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
873 interrupt-names = "ch0", "ch1";
874 clocks = <&cpg CPG_MOD 326>;
875 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
876 resets = <&cpg 326>;
877 #dma-cells = <1>;
878 dma-channels = <2>;
879 };
880
881 usb_dmac3: dma-controller@e6470000 {
882 compatible = "renesas,r8a7795-usb-dmac",
883 "renesas,usb-dmac";
884 reg = <0 0xe6470000 0 0x100>;
885 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
886 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-names = "ch0", "ch1";
888 clocks = <&cpg CPG_MOD 329>;
889 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
890 resets = <&cpg 329>;
891 #dma-cells = <1>;
892 dma-channels = <2>;
893 };
894
895 usb3_phy0: usb-phy@e65ee000 {
896 compatible = "renesas,r8a7795-usb3-phy",
897 "renesas,rcar-gen3-usb3-phy";
898 reg = <0 0xe65ee000 0 0x90>;
899 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
900 <&usb_extal_clk>;
901 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
902 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
903 resets = <&cpg 328>;
904 #phy-cells = <0>;
905 status = "disabled";
906 };
907
908 arm_cc630p: crypto@e6601000 {
909 compatible = "arm,cryptocell-630p-ree";
910 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
911 reg = <0x0 0xe6601000 0 0x1000>;
912 clocks = <&cpg CPG_MOD 229>;
913 resets = <&cpg 229>;
914 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
915 };
916
917 dmac0: dma-controller@e6700000 {
918 compatible = "renesas,dmac-r8a7795",
919 "renesas,rcar-dmac";
920 reg = <0 0xe6700000 0 0x10000>;
921 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
922 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
923 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
924 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
925 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
926 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
927 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
928 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
929 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
930 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
931 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
932 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
933 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
934 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
935 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
936 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
937 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
938 interrupt-names = "error",
939 "ch0", "ch1", "ch2", "ch3",
940 "ch4", "ch5", "ch6", "ch7",
941 "ch8", "ch9", "ch10", "ch11",
942 "ch12", "ch13", "ch14", "ch15";
943 clocks = <&cpg CPG_MOD 219>;
944 clock-names = "fck";
945 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
946 resets = <&cpg 219>;
947 #dma-cells = <1>;
948 dma-channels = <16>;
949 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
950 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
951 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
952 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
953 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
954 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
955 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
956 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
957 };
958
959 dmac1: dma-controller@e7300000 {
960 compatible = "renesas,dmac-r8a7795",
961 "renesas,rcar-dmac";
962 reg = <0 0xe7300000 0 0x10000>;
963 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
964 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
965 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
966 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
967 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
968 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
969 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
970 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
971 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
972 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
973 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
974 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
975 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
976 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
977 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
978 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
979 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
980 interrupt-names = "error",
981 "ch0", "ch1", "ch2", "ch3",
982 "ch4", "ch5", "ch6", "ch7",
983 "ch8", "ch9", "ch10", "ch11",
984 "ch12", "ch13", "ch14", "ch15";
985 clocks = <&cpg CPG_MOD 218>;
986 clock-names = "fck";
987 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
988 resets = <&cpg 218>;
989 #dma-cells = <1>;
990 dma-channels = <16>;
991 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
992 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
993 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
994 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
995 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
996 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
997 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
998 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
999 };
1000
1001 dmac2: dma-controller@e7310000 {
1002 compatible = "renesas,dmac-r8a7795",
1003 "renesas,rcar-dmac";
1004 reg = <0 0xe7310000 0 0x10000>;
1005 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
1006 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
1007 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
1008 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
1009 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
1010 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
1011 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
1012 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
1013 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
1014 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
1015 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
1016 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
1017 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
1018 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
1019 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
1020 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
1021 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1022 interrupt-names = "error",
1023 "ch0", "ch1", "ch2", "ch3",
1024 "ch4", "ch5", "ch6", "ch7",
1025 "ch8", "ch9", "ch10", "ch11",
1026 "ch12", "ch13", "ch14", "ch15";
1027 clocks = <&cpg CPG_MOD 217>;
1028 clock-names = "fck";
1029 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1030 resets = <&cpg 217>;
1031 #dma-cells = <1>;
1032 dma-channels = <16>;
1033 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1034 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1035 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1036 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1037 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1038 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1039 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1040 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1041 };
1042
1043 ipmmu_ds0: mmu@e6740000 {
1044 compatible = "renesas,ipmmu-r8a7795";
1045 reg = <0 0xe6740000 0 0x1000>;
1046 renesas,ipmmu-main = <&ipmmu_mm 0>;
1047 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1048 #iommu-cells = <1>;
1049 };
1050
1051 ipmmu_ds1: mmu@e7740000 {
1052 compatible = "renesas,ipmmu-r8a7795";
1053 reg = <0 0xe7740000 0 0x1000>;
1054 renesas,ipmmu-main = <&ipmmu_mm 1>;
1055 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1056 #iommu-cells = <1>;
1057 };
1058
1059 ipmmu_hc: mmu@e6570000 {
1060 compatible = "renesas,ipmmu-r8a7795";
1061 reg = <0 0xe6570000 0 0x1000>;
1062 renesas,ipmmu-main = <&ipmmu_mm 2>;
1063 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1064 #iommu-cells = <1>;
1065 };
1066
1067 ipmmu_ir: mmu@ff8b0000 {
1068 compatible = "renesas,ipmmu-r8a7795";
1069 reg = <0 0xff8b0000 0 0x1000>;
1070 renesas,ipmmu-main = <&ipmmu_mm 3>;
1071 power-domains = <&sysc R8A7795_PD_A3IR>;
1072 #iommu-cells = <1>;
1073 };
1074
1075 ipmmu_mm: mmu@e67b0000 {
1076 compatible = "renesas,ipmmu-r8a7795";
1077 reg = <0 0xe67b0000 0 0x1000>;
1078 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1079 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1080 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1081 #iommu-cells = <1>;
1082 };
1083
1084 ipmmu_mp0: mmu@ec670000 {
1085 compatible = "renesas,ipmmu-r8a7795";
1086 reg = <0 0xec670000 0 0x1000>;
1087 renesas,ipmmu-main = <&ipmmu_mm 4>;
1088 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1089 #iommu-cells = <1>;
1090 };
1091
1092 ipmmu_pv0: mmu@fd800000 {
1093 compatible = "renesas,ipmmu-r8a7795";
1094 reg = <0 0xfd800000 0 0x1000>;
1095 renesas,ipmmu-main = <&ipmmu_mm 6>;
1096 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1097 #iommu-cells = <1>;
1098 };
1099
1100 ipmmu_pv1: mmu@fd950000 {
1101 compatible = "renesas,ipmmu-r8a7795";
1102 reg = <0 0xfd950000 0 0x1000>;
1103 renesas,ipmmu-main = <&ipmmu_mm 7>;
1104 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1105 #iommu-cells = <1>;
1106 };
1107
1108 ipmmu_pv2: mmu@fd960000 {
1109 compatible = "renesas,ipmmu-r8a7795";
1110 reg = <0 0xfd960000 0 0x1000>;
1111 renesas,ipmmu-main = <&ipmmu_mm 8>;
1112 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1113 #iommu-cells = <1>;
1114 };
1115
1116 ipmmu_pv3: mmu@fd970000 {
1117 compatible = "renesas,ipmmu-r8a7795";
1118 reg = <0 0xfd970000 0 0x1000>;
1119 renesas,ipmmu-main = <&ipmmu_mm 9>;
1120 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1121 #iommu-cells = <1>;
1122 };
1123
1124 ipmmu_rt: mmu@ffc80000 {
1125 compatible = "renesas,ipmmu-r8a7795";
1126 reg = <0 0xffc80000 0 0x1000>;
1127 renesas,ipmmu-main = <&ipmmu_mm 10>;
1128 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1129 #iommu-cells = <1>;
1130 };
1131
1132 ipmmu_vc0: mmu@fe6b0000 {
1133 compatible = "renesas,ipmmu-r8a7795";
1134 reg = <0 0xfe6b0000 0 0x1000>;
1135 renesas,ipmmu-main = <&ipmmu_mm 12>;
1136 power-domains = <&sysc R8A7795_PD_A3VC>;
1137 #iommu-cells = <1>;
1138 };
1139
1140 ipmmu_vc1: mmu@fe6f0000 {
1141 compatible = "renesas,ipmmu-r8a7795";
1142 reg = <0 0xfe6f0000 0 0x1000>;
1143 renesas,ipmmu-main = <&ipmmu_mm 13>;
1144 power-domains = <&sysc R8A7795_PD_A3VC>;
1145 #iommu-cells = <1>;
1146 };
1147
1148 ipmmu_vi0: mmu@febd0000 {
1149 compatible = "renesas,ipmmu-r8a7795";
1150 reg = <0 0xfebd0000 0 0x1000>;
1151 renesas,ipmmu-main = <&ipmmu_mm 14>;
1152 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1153 #iommu-cells = <1>;
1154 };
1155
1156 ipmmu_vi1: mmu@febe0000 {
1157 compatible = "renesas,ipmmu-r8a7795";
1158 reg = <0 0xfebe0000 0 0x1000>;
1159 renesas,ipmmu-main = <&ipmmu_mm 15>;
1160 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1161 #iommu-cells = <1>;
1162 };
1163
1164 ipmmu_vp0: mmu@fe990000 {
1165 compatible = "renesas,ipmmu-r8a7795";
1166 reg = <0 0xfe990000 0 0x1000>;
1167 renesas,ipmmu-main = <&ipmmu_mm 16>;
1168 power-domains = <&sysc R8A7795_PD_A3VP>;
1169 #iommu-cells = <1>;
1170 };
1171
1172 ipmmu_vp1: mmu@fe980000 {
1173 compatible = "renesas,ipmmu-r8a7795";
1174 reg = <0 0xfe980000 0 0x1000>;
1175 renesas,ipmmu-main = <&ipmmu_mm 17>;
1176 power-domains = <&sysc R8A7795_PD_A3VP>;
1177 #iommu-cells = <1>;
1178 };
1179
1180 avb: ethernet@e6800000 {
1181 compatible = "renesas,etheravb-r8a7795",
1182 "renesas,etheravb-rcar-gen3";
1183 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1184 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1209 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1210 "ch4", "ch5", "ch6", "ch7",
1211 "ch8", "ch9", "ch10", "ch11",
1212 "ch12", "ch13", "ch14", "ch15",
1213 "ch16", "ch17", "ch18", "ch19",
1214 "ch20", "ch21", "ch22", "ch23",
1215 "ch24";
1216 clocks = <&cpg CPG_MOD 812>;
1217 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1218 resets = <&cpg 812>;
1219 phy-mode = "rgmii";
1220 iommus = <&ipmmu_ds0 16>;
1221 #address-cells = <1>;
1222 #size-cells = <0>;
1223 status = "disabled";
1224 };
1225
1226 can0: can@e6c30000 {
1227 compatible = "renesas,can-r8a7795",
1228 "renesas,rcar-gen3-can";
1229 reg = <0 0xe6c30000 0 0x1000>;
1230 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&cpg CPG_MOD 916>,
1232 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
1233 <&can_clk>;
1234 clock-names = "clkp1", "clkp2", "can_clk";
1235 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
1236 assigned-clock-rates = <40000000>;
1237 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1238 resets = <&cpg 916>;
1239 status = "disabled";
1240 };
1241
1242 can1: can@e6c38000 {
1243 compatible = "renesas,can-r8a7795",
1244 "renesas,rcar-gen3-can";
1245 reg = <0 0xe6c38000 0 0x1000>;
1246 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&cpg CPG_MOD 915>,
1248 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
1249 <&can_clk>;
1250 clock-names = "clkp1", "clkp2", "can_clk";
1251 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
1252 assigned-clock-rates = <40000000>;
1253 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1254 resets = <&cpg 915>;
1255 status = "disabled";
1256 };
1257
1258 canfd: can@e66c0000 {
1259 compatible = "renesas,r8a7795-canfd",
1260 "renesas,rcar-gen3-canfd";
1261 reg = <0 0xe66c0000 0 0x8000>;
1262 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cpg CPG_MOD 914>,
1265 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
1266 <&can_clk>;
1267 clock-names = "fck", "canfd", "can_clk";
1268 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
1269 assigned-clock-rates = <40000000>;
1270 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1271 resets = <&cpg 914>;
1272 status = "disabled";
1273
1274 channel0 {
1275 status = "disabled";
1276 };
1277
1278 channel1 {
1279 status = "disabled";
1280 };
1281 };
1282
1283 pwm0: pwm@e6e30000 {
1284 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1285 reg = <0 0xe6e30000 0 0x8>;
1286 clocks = <&cpg CPG_MOD 523>;
1287 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1288 resets = <&cpg 523>;
1289 #pwm-cells = <2>;
1290 status = "disabled";
1291 };
1292
1293 pwm1: pwm@e6e31000 {
1294 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1295 reg = <0 0xe6e31000 0 0x8>;
1296 clocks = <&cpg CPG_MOD 523>;
1297 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1298 resets = <&cpg 523>;
1299 #pwm-cells = <2>;
1300 status = "disabled";
1301 };
1302
1303 pwm2: pwm@e6e32000 {
1304 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1305 reg = <0 0xe6e32000 0 0x8>;
1306 clocks = <&cpg CPG_MOD 523>;
1307 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1308 resets = <&cpg 523>;
1309 #pwm-cells = <2>;
1310 status = "disabled";
1311 };
1312
1313 pwm3: pwm@e6e33000 {
1314 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1315 reg = <0 0xe6e33000 0 0x8>;
1316 clocks = <&cpg CPG_MOD 523>;
1317 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1318 resets = <&cpg 523>;
1319 #pwm-cells = <2>;
1320 status = "disabled";
1321 };
1322
1323 pwm4: pwm@e6e34000 {
1324 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1325 reg = <0 0xe6e34000 0 0x8>;
1326 clocks = <&cpg CPG_MOD 523>;
1327 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1328 resets = <&cpg 523>;
1329 #pwm-cells = <2>;
1330 status = "disabled";
1331 };
1332
1333 pwm5: pwm@e6e35000 {
1334 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1335 reg = <0 0xe6e35000 0 0x8>;
1336 clocks = <&cpg CPG_MOD 523>;
1337 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1338 resets = <&cpg 523>;
1339 #pwm-cells = <2>;
1340 status = "disabled";
1341 };
1342
1343 pwm6: pwm@e6e36000 {
1344 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1345 reg = <0 0xe6e36000 0 0x8>;
1346 clocks = <&cpg CPG_MOD 523>;
1347 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1348 resets = <&cpg 523>;
1349 #pwm-cells = <2>;
1350 status = "disabled";
1351 };
1352
1353 scif0: serial@e6e60000 {
1354 compatible = "renesas,scif-r8a7795",
1355 "renesas,rcar-gen3-scif", "renesas,scif";
1356 reg = <0 0xe6e60000 0 64>;
1357 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&cpg CPG_MOD 207>,
1359 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1360 <&scif_clk>;
1361 clock-names = "fck", "brg_int", "scif_clk";
1362 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1363 <&dmac2 0x51>, <&dmac2 0x50>;
1364 dma-names = "tx", "rx", "tx", "rx";
1365 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1366 resets = <&cpg 207>;
1367 status = "disabled";
1368 };
1369
1370 scif1: serial@e6e68000 {
1371 compatible = "renesas,scif-r8a7795",
1372 "renesas,rcar-gen3-scif", "renesas,scif";
1373 reg = <0 0xe6e68000 0 64>;
1374 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1375 clocks = <&cpg CPG_MOD 206>,
1376 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1377 <&scif_clk>;
1378 clock-names = "fck", "brg_int", "scif_clk";
1379 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1380 <&dmac2 0x53>, <&dmac2 0x52>;
1381 dma-names = "tx", "rx", "tx", "rx";
1382 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1383 resets = <&cpg 206>;
1384 status = "disabled";
1385 };
1386
1387 scif2: serial@e6e88000 {
1388 compatible = "renesas,scif-r8a7795",
1389 "renesas,rcar-gen3-scif", "renesas,scif";
1390 reg = <0 0xe6e88000 0 64>;
1391 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1392 clocks = <&cpg CPG_MOD 310>,
1393 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1394 <&scif_clk>;
1395 clock-names = "fck", "brg_int", "scif_clk";
1396 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1397 <&dmac2 0x13>, <&dmac2 0x12>;
1398 dma-names = "tx", "rx", "tx", "rx";
1399 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1400 resets = <&cpg 310>;
1401 status = "disabled";
1402 };
1403
1404 scif3: serial@e6c50000 {
1405 compatible = "renesas,scif-r8a7795",
1406 "renesas,rcar-gen3-scif", "renesas,scif";
1407 reg = <0 0xe6c50000 0 64>;
1408 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cpg CPG_MOD 204>,
1410 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1411 <&scif_clk>;
1412 clock-names = "fck", "brg_int", "scif_clk";
1413 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1414 dma-names = "tx", "rx";
1415 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1416 resets = <&cpg 204>;
1417 status = "disabled";
1418 };
1419
1420 scif4: serial@e6c40000 {
1421 compatible = "renesas,scif-r8a7795",
1422 "renesas,rcar-gen3-scif", "renesas,scif";
1423 reg = <0 0xe6c40000 0 64>;
1424 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&cpg CPG_MOD 203>,
1426 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1427 <&scif_clk>;
1428 clock-names = "fck", "brg_int", "scif_clk";
1429 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1430 dma-names = "tx", "rx";
1431 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1432 resets = <&cpg 203>;
1433 status = "disabled";
1434 };
1435
1436 scif5: serial@e6f30000 {
1437 compatible = "renesas,scif-r8a7795",
1438 "renesas,rcar-gen3-scif", "renesas,scif";
1439 reg = <0 0xe6f30000 0 64>;
1440 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&cpg CPG_MOD 202>,
1442 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1443 <&scif_clk>;
1444 clock-names = "fck", "brg_int", "scif_clk";
1445 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1446 <&dmac2 0x5b>, <&dmac2 0x5a>;
1447 dma-names = "tx", "rx", "tx", "rx";
1448 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1449 resets = <&cpg 202>;
1450 status = "disabled";
1451 };
1452
1453 msiof0: spi@e6e90000 {
1454 compatible = "renesas,msiof-r8a7795",
1455 "renesas,rcar-gen3-msiof";
1456 reg = <0 0xe6e90000 0 0x0064>;
1457 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1458 clocks = <&cpg CPG_MOD 211>;
1459 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1460 <&dmac2 0x41>, <&dmac2 0x40>;
1461 dma-names = "tx", "rx", "tx", "rx";
1462 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1463 resets = <&cpg 211>;
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1466 status = "disabled";
1467 };
1468
1469 msiof1: spi@e6ea0000 {
1470 compatible = "renesas,msiof-r8a7795",
1471 "renesas,rcar-gen3-msiof";
1472 reg = <0 0xe6ea0000 0 0x0064>;
1473 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&cpg CPG_MOD 210>;
1475 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1476 <&dmac2 0x43>, <&dmac2 0x42>;
1477 dma-names = "tx", "rx", "tx", "rx";
1478 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1479 resets = <&cpg 210>;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1482 status = "disabled";
1483 };
1484
1485 msiof2: spi@e6c00000 {
1486 compatible = "renesas,msiof-r8a7795",
1487 "renesas,rcar-gen3-msiof";
1488 reg = <0 0xe6c00000 0 0x0064>;
1489 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1490 clocks = <&cpg CPG_MOD 209>;
1491 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1492 dma-names = "tx", "rx";
1493 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1494 resets = <&cpg 209>;
1495 #address-cells = <1>;
1496 #size-cells = <0>;
1497 status = "disabled";
1498 };
1499
1500 msiof3: spi@e6c10000 {
1501 compatible = "renesas,msiof-r8a7795",
1502 "renesas,rcar-gen3-msiof";
1503 reg = <0 0xe6c10000 0 0x0064>;
1504 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&cpg CPG_MOD 208>;
1506 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1507 dma-names = "tx", "rx";
1508 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1509 resets = <&cpg 208>;
1510 #address-cells = <1>;
1511 #size-cells = <0>;
1512 status = "disabled";
1513 };
1514
1515 vin0: video@e6ef0000 {
1516 compatible = "renesas,vin-r8a7795";
1517 reg = <0 0xe6ef0000 0 0x1000>;
1518 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1519 clocks = <&cpg CPG_MOD 811>;
1520 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1521 resets = <&cpg 811>;
1522 renesas,id = <0>;
1523 status = "disabled";
1524
1525 ports {
1526 #address-cells = <1>;
1527 #size-cells = <0>;
1528
1529 port@1 {
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532
1533 reg = <1>;
1534
1535 vin0csi20: endpoint@0 {
1536 reg = <0>;
1537 remote-endpoint = <&csi20vin0>;
1538 };
1539 vin0csi40: endpoint@2 {
1540 reg = <2>;
1541 remote-endpoint = <&csi40vin0>;
1542 };
1543 };
1544 };
1545 };
1546
1547 vin1: video@e6ef1000 {
1548 compatible = "renesas,vin-r8a7795";
1549 reg = <0 0xe6ef1000 0 0x1000>;
1550 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&cpg CPG_MOD 810>;
1552 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1553 resets = <&cpg 810>;
1554 renesas,id = <1>;
1555 status = "disabled";
1556
1557 ports {
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1560
1561 port@1 {
1562 #address-cells = <1>;
1563 #size-cells = <0>;
1564
1565 reg = <1>;
1566
1567 vin1csi20: endpoint@0 {
1568 reg = <0>;
1569 remote-endpoint = <&csi20vin1>;
1570 };
1571 vin1csi40: endpoint@2 {
1572 reg = <2>;
1573 remote-endpoint = <&csi40vin1>;
1574 };
1575 };
1576 };
1577 };
1578
1579 vin2: video@e6ef2000 {
1580 compatible = "renesas,vin-r8a7795";
1581 reg = <0 0xe6ef2000 0 0x1000>;
1582 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1583 clocks = <&cpg CPG_MOD 809>;
1584 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1585 resets = <&cpg 809>;
1586 renesas,id = <2>;
1587 status = "disabled";
1588
1589 ports {
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1592
1593 port@1 {
1594 #address-cells = <1>;
1595 #size-cells = <0>;
1596
1597 reg = <1>;
1598
1599 vin2csi20: endpoint@0 {
1600 reg = <0>;
1601 remote-endpoint = <&csi20vin2>;
1602 };
1603 vin2csi40: endpoint@2 {
1604 reg = <2>;
1605 remote-endpoint = <&csi40vin2>;
1606 };
1607 };
1608 };
1609 };
1610
1611 vin3: video@e6ef3000 {
1612 compatible = "renesas,vin-r8a7795";
1613 reg = <0 0xe6ef3000 0 0x1000>;
1614 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&cpg CPG_MOD 808>;
1616 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1617 resets = <&cpg 808>;
1618 renesas,id = <3>;
1619 status = "disabled";
1620
1621 ports {
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1624
1625 port@1 {
1626 #address-cells = <1>;
1627 #size-cells = <0>;
1628
1629 reg = <1>;
1630
1631 vin3csi20: endpoint@0 {
1632 reg = <0>;
1633 remote-endpoint = <&csi20vin3>;
1634 };
1635 vin3csi40: endpoint@2 {
1636 reg = <2>;
1637 remote-endpoint = <&csi40vin3>;
1638 };
1639 };
1640 };
1641 };
1642
1643 vin4: video@e6ef4000 {
1644 compatible = "renesas,vin-r8a7795";
1645 reg = <0 0xe6ef4000 0 0x1000>;
1646 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1647 clocks = <&cpg CPG_MOD 807>;
1648 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1649 resets = <&cpg 807>;
1650 renesas,id = <4>;
1651 status = "disabled";
1652
1653 ports {
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1656
1657 port@1 {
1658 #address-cells = <1>;
1659 #size-cells = <0>;
1660
1661 reg = <1>;
1662
1663 vin4csi20: endpoint@0 {
1664 reg = <0>;
1665 remote-endpoint = <&csi20vin4>;
1666 };
1667 vin4csi41: endpoint@3 {
1668 reg = <3>;
1669 remote-endpoint = <&csi41vin4>;
1670 };
1671 };
1672 };
1673 };
1674
1675 vin5: video@e6ef5000 {
1676 compatible = "renesas,vin-r8a7795";
1677 reg = <0 0xe6ef5000 0 0x1000>;
1678 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1679 clocks = <&cpg CPG_MOD 806>;
1680 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1681 resets = <&cpg 806>;
1682 renesas,id = <5>;
1683 status = "disabled";
1684
1685 ports {
1686 #address-cells = <1>;
1687 #size-cells = <0>;
1688
1689 port@1 {
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1692
1693 reg = <1>;
1694
1695 vin5csi20: endpoint@0 {
1696 reg = <0>;
1697 remote-endpoint = <&csi20vin5>;
1698 };
1699 vin5csi41: endpoint@3 {
1700 reg = <3>;
1701 remote-endpoint = <&csi41vin5>;
1702 };
1703 };
1704 };
1705 };
1706
1707 vin6: video@e6ef6000 {
1708 compatible = "renesas,vin-r8a7795";
1709 reg = <0 0xe6ef6000 0 0x1000>;
1710 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1711 clocks = <&cpg CPG_MOD 805>;
1712 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1713 resets = <&cpg 805>;
1714 renesas,id = <6>;
1715 status = "disabled";
1716
1717 ports {
1718 #address-cells = <1>;
1719 #size-cells = <0>;
1720
1721 port@1 {
1722 #address-cells = <1>;
1723 #size-cells = <0>;
1724
1725 reg = <1>;
1726
1727 vin6csi20: endpoint@0 {
1728 reg = <0>;
1729 remote-endpoint = <&csi20vin6>;
1730 };
1731 vin6csi41: endpoint@3 {
1732 reg = <3>;
1733 remote-endpoint = <&csi41vin6>;
1734 };
1735 };
1736 };
1737 };
1738
1739 vin7: video@e6ef7000 {
1740 compatible = "renesas,vin-r8a7795";
1741 reg = <0 0xe6ef7000 0 0x1000>;
1742 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&cpg CPG_MOD 804>;
1744 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1745 resets = <&cpg 804>;
1746 renesas,id = <7>;
1747 status = "disabled";
1748
1749 ports {
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1752
1753 port@1 {
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1756
1757 reg = <1>;
1758
1759 vin7csi20: endpoint@0 {
1760 reg = <0>;
1761 remote-endpoint = <&csi20vin7>;
1762 };
1763 vin7csi41: endpoint@3 {
1764 reg = <3>;
1765 remote-endpoint = <&csi41vin7>;
1766 };
1767 };
1768 };
1769 };
1770
1771 drif00: rif@e6f40000 {
1772 compatible = "renesas,r8a7795-drif",
1773 "renesas,rcar-gen3-drif";
1774 reg = <0 0xe6f40000 0 0x64>;
1775 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1776 clocks = <&cpg CPG_MOD 515>;
1777 clock-names = "fck";
1778 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1779 dma-names = "rx", "rx";
1780 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1781 resets = <&cpg 515>;
1782 renesas,bonding = <&drif01>;
1783 status = "disabled";
1784 };
1785
1786 drif01: rif@e6f50000 {
1787 compatible = "renesas,r8a7795-drif",
1788 "renesas,rcar-gen3-drif";
1789 reg = <0 0xe6f50000 0 0x64>;
1790 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1791 clocks = <&cpg CPG_MOD 514>;
1792 clock-names = "fck";
1793 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1794 dma-names = "rx", "rx";
1795 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1796 resets = <&cpg 514>;
1797 renesas,bonding = <&drif00>;
1798 status = "disabled";
1799 };
1800
1801 drif10: rif@e6f60000 {
1802 compatible = "renesas,r8a7795-drif",
1803 "renesas,rcar-gen3-drif";
1804 reg = <0 0xe6f60000 0 0x64>;
1805 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1806 clocks = <&cpg CPG_MOD 513>;
1807 clock-names = "fck";
1808 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1809 dma-names = "rx", "rx";
1810 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1811 resets = <&cpg 513>;
1812 renesas,bonding = <&drif11>;
1813 status = "disabled";
1814 };
1815
1816 drif11: rif@e6f70000 {
1817 compatible = "renesas,r8a7795-drif",
1818 "renesas,rcar-gen3-drif";
1819 reg = <0 0xe6f70000 0 0x64>;
1820 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1821 clocks = <&cpg CPG_MOD 512>;
1822 clock-names = "fck";
1823 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1824 dma-names = "rx", "rx";
1825 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1826 resets = <&cpg 512>;
1827 renesas,bonding = <&drif10>;
1828 status = "disabled";
1829 };
1830
1831 drif20: rif@e6f80000 {
1832 compatible = "renesas,r8a7795-drif",
1833 "renesas,rcar-gen3-drif";
1834 reg = <0 0xe6f80000 0 0x64>;
1835 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1836 clocks = <&cpg CPG_MOD 511>;
1837 clock-names = "fck";
1838 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1839 dma-names = "rx", "rx";
1840 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1841 resets = <&cpg 511>;
1842 renesas,bonding = <&drif21>;
1843 status = "disabled";
1844 };
1845
1846 drif21: rif@e6f90000 {
1847 compatible = "renesas,r8a7795-drif",
1848 "renesas,rcar-gen3-drif";
1849 reg = <0 0xe6f90000 0 0x64>;
1850 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1851 clocks = <&cpg CPG_MOD 510>;
1852 clock-names = "fck";
1853 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1854 dma-names = "rx", "rx";
1855 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1856 resets = <&cpg 510>;
1857 renesas,bonding = <&drif20>;
1858 status = "disabled";
1859 };
1860
1861 drif30: rif@e6fa0000 {
1862 compatible = "renesas,r8a7795-drif",
1863 "renesas,rcar-gen3-drif";
1864 reg = <0 0xe6fa0000 0 0x64>;
1865 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1866 clocks = <&cpg CPG_MOD 509>;
1867 clock-names = "fck";
1868 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1869 dma-names = "rx", "rx";
1870 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1871 resets = <&cpg 509>;
1872 renesas,bonding = <&drif31>;
1873 status = "disabled";
1874 };
1875
1876 drif31: rif@e6fb0000 {
1877 compatible = "renesas,r8a7795-drif",
1878 "renesas,rcar-gen3-drif";
1879 reg = <0 0xe6fb0000 0 0x64>;
1880 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1881 clocks = <&cpg CPG_MOD 508>;
1882 clock-names = "fck";
1883 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1884 dma-names = "rx", "rx";
1885 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1886 resets = <&cpg 508>;
1887 renesas,bonding = <&drif30>;
1888 status = "disabled";
1889 };
1890
1891 rcar_sound: sound@ec500000 {
1892 /*
1893 * #sound-dai-cells is required
1894 *
1895 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1896 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1897 */
1898 /*
1899 * #clock-cells is required for audio_clkout0/1/2/3
1900 *
1901 * clkout : #clock-cells = <0>; <&rcar_sound>;
1902 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1903 */
1904 compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
1905 reg = <0 0xec500000 0 0x1000>, /* SCU */
1906 <0 0xec5a0000 0 0x100>, /* ADG */
1907 <0 0xec540000 0 0x1000>, /* SSIU */
1908 <0 0xec541000 0 0x280>, /* SSI */
1909 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1910 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1911
1912 clocks = <&cpg CPG_MOD 1005>,
1913 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1914 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1915 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1916 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1917 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1918 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1919 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1920 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1921 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1922 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1923 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1924 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1925 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1926 <&audio_clk_a>, <&audio_clk_b>,
1927 <&audio_clk_c>,
1928 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
1929 clock-names = "ssi-all",
1930 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1931 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1932 "ssi.1", "ssi.0",
1933 "src.9", "src.8", "src.7", "src.6",
1934 "src.5", "src.4", "src.3", "src.2",
1935 "src.1", "src.0",
1936 "mix.1", "mix.0",
1937 "ctu.1", "ctu.0",
1938 "dvc.0", "dvc.1",
1939 "clk_a", "clk_b", "clk_c", "clk_i";
1940 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1941 resets = <&cpg 1005>,
1942 <&cpg 1006>, <&cpg 1007>,
1943 <&cpg 1008>, <&cpg 1009>,
1944 <&cpg 1010>, <&cpg 1011>,
1945 <&cpg 1012>, <&cpg 1013>,
1946 <&cpg 1014>, <&cpg 1015>;
1947 reset-names = "ssi-all",
1948 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1949 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1950 "ssi.1", "ssi.0";
1951 status = "disabled";
1952
1953 rcar_sound,dvc {
1954 dvc0: dvc-0 {
1955 dmas = <&audma1 0xbc>;
1956 dma-names = "tx";
1957 };
1958 dvc1: dvc-1 {
1959 dmas = <&audma1 0xbe>;
1960 dma-names = "tx";
1961 };
1962 };
1963
1964 rcar_sound,mix {
1965 mix0: mix-0 { };
1966 mix1: mix-1 { };
1967 };
1968
1969 rcar_sound,ctu {
1970 ctu00: ctu-0 { };
1971 ctu01: ctu-1 { };
1972 ctu02: ctu-2 { };
1973 ctu03: ctu-3 { };
1974 ctu10: ctu-4 { };
1975 ctu11: ctu-5 { };
1976 ctu12: ctu-6 { };
1977 ctu13: ctu-7 { };
1978 };
1979
1980 rcar_sound,src {
1981 src0: src-0 {
1982 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1983 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1984 dma-names = "rx", "tx";
1985 };
1986 src1: src-1 {
1987 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1988 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1989 dma-names = "rx", "tx";
1990 };
1991 src2: src-2 {
1992 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1993 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1994 dma-names = "rx", "tx";
1995 };
1996 src3: src-3 {
1997 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1998 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1999 dma-names = "rx", "tx";
2000 };
2001 src4: src-4 {
2002 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2003 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
2004 dma-names = "rx", "tx";
2005 };
2006 src5: src-5 {
2007 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2008 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
2009 dma-names = "rx", "tx";
2010 };
2011 src6: src-6 {
2012 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2013 dmas = <&audma0 0x91>, <&audma1 0xb4>;
2014 dma-names = "rx", "tx";
2015 };
2016 src7: src-7 {
2017 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2018 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2019 dma-names = "rx", "tx";
2020 };
2021 src8: src-8 {
2022 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2023 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2024 dma-names = "rx", "tx";
2025 };
2026 src9: src-9 {
2027 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2028 dmas = <&audma0 0x97>, <&audma1 0xba>;
2029 dma-names = "rx", "tx";
2030 };
2031 };
2032
2033 rcar_sound,ssiu {
2034 ssiu00: ssiu-0 {
2035 dmas = <&audma0 0x15>, <&audma1 0x16>;
2036 dma-names = "rx", "tx";
2037 };
2038 ssiu01: ssiu-1 {
2039 dmas = <&audma0 0x35>, <&audma1 0x36>;
2040 dma-names = "rx", "tx";
2041 };
2042 ssiu02: ssiu-2 {
2043 dmas = <&audma0 0x37>, <&audma1 0x38>;
2044 dma-names = "rx", "tx";
2045 };
2046 ssiu03: ssiu-3 {
2047 dmas = <&audma0 0x47>, <&audma1 0x48>;
2048 dma-names = "rx", "tx";
2049 };
2050 ssiu04: ssiu-4 {
2051 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2052 dma-names = "rx", "tx";
2053 };
2054 ssiu05: ssiu-5 {
2055 dmas = <&audma0 0x43>, <&audma1 0x44>;
2056 dma-names = "rx", "tx";
2057 };
2058 ssiu06: ssiu-6 {
2059 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2060 dma-names = "rx", "tx";
2061 };
2062 ssiu07: ssiu-7 {
2063 dmas = <&audma0 0x53>, <&audma1 0x54>;
2064 dma-names = "rx", "tx";
2065 };
2066 ssiu10: ssiu-8 {
2067 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2068 dma-names = "rx", "tx";
2069 };
2070 ssiu11: ssiu-9 {
2071 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2072 dma-names = "rx", "tx";
2073 };
2074 ssiu12: ssiu-10 {
2075 dmas = <&audma0 0x57>, <&audma1 0x58>;
2076 dma-names = "rx", "tx";
2077 };
2078 ssiu13: ssiu-11 {
2079 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2080 dma-names = "rx", "tx";
2081 };
2082 ssiu14: ssiu-12 {
2083 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2084 dma-names = "rx", "tx";
2085 };
2086 ssiu15: ssiu-13 {
2087 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2088 dma-names = "rx", "tx";
2089 };
2090 ssiu16: ssiu-14 {
2091 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2092 dma-names = "rx", "tx";
2093 };
2094 ssiu17: ssiu-15 {
2095 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2096 dma-names = "rx", "tx";
2097 };
2098 ssiu20: ssiu-16 {
2099 dmas = <&audma0 0x63>, <&audma1 0x64>;
2100 dma-names = "rx", "tx";
2101 };
2102 ssiu21: ssiu-17 {
2103 dmas = <&audma0 0x67>, <&audma1 0x68>;
2104 dma-names = "rx", "tx";
2105 };
2106 ssiu22: ssiu-18 {
2107 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2108 dma-names = "rx", "tx";
2109 };
2110 ssiu23: ssiu-19 {
2111 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2112 dma-names = "rx", "tx";
2113 };
2114 ssiu24: ssiu-20 {
2115 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2116 dma-names = "rx", "tx";
2117 };
2118 ssiu25: ssiu-21 {
2119 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2120 dma-names = "rx", "tx";
2121 };
2122 ssiu26: ssiu-22 {
2123 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2124 dma-names = "rx", "tx";
2125 };
2126 ssiu27: ssiu-23 {
2127 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2128 dma-names = "rx", "tx";
2129 };
2130 ssiu30: ssiu-24 {
2131 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2132 dma-names = "rx", "tx";
2133 };
2134 ssiu31: ssiu-25 {
2135 dmas = <&audma0 0x21>, <&audma1 0x22>;
2136 dma-names = "rx", "tx";
2137 };
2138 ssiu32: ssiu-26 {
2139 dmas = <&audma0 0x23>, <&audma1 0x24>;
2140 dma-names = "rx", "tx";
2141 };
2142 ssiu33: ssiu-27 {
2143 dmas = <&audma0 0x25>, <&audma1 0x26>;
2144 dma-names = "rx", "tx";
2145 };
2146 ssiu34: ssiu-28 {
2147 dmas = <&audma0 0x27>, <&audma1 0x28>;
2148 dma-names = "rx", "tx";
2149 };
2150 ssiu35: ssiu-29 {
2151 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2152 dma-names = "rx", "tx";
2153 };
2154 ssiu36: ssiu-30 {
2155 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2156 dma-names = "rx", "tx";
2157 };
2158 ssiu37: ssiu-31 {
2159 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2160 dma-names = "rx", "tx";
2161 };
2162 ssiu40: ssiu-32 {
2163 dmas = <&audma0 0x71>, <&audma1 0x72>;
2164 dma-names = "rx", "tx";
2165 };
2166 ssiu41: ssiu-33 {
2167 dmas = <&audma0 0x17>, <&audma1 0x18>;
2168 dma-names = "rx", "tx";
2169 };
2170 ssiu42: ssiu-34 {
2171 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2172 dma-names = "rx", "tx";
2173 };
2174 ssiu43: ssiu-35 {
2175 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2176 dma-names = "rx", "tx";
2177 };
2178 ssiu44: ssiu-36 {
2179 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2180 dma-names = "rx", "tx";
2181 };
2182 ssiu45: ssiu-37 {
2183 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2184 dma-names = "rx", "tx";
2185 };
2186 ssiu46: ssiu-38 {
2187 dmas = <&audma0 0x31>, <&audma1 0x32>;
2188 dma-names = "rx", "tx";
2189 };
2190 ssiu47: ssiu-39 {
2191 dmas = <&audma0 0x33>, <&audma1 0x34>;
2192 dma-names = "rx", "tx";
2193 };
2194 ssiu50: ssiu-40 {
2195 dmas = <&audma0 0x73>, <&audma1 0x74>;
2196 dma-names = "rx", "tx";
2197 };
2198 ssiu60: ssiu-41 {
2199 dmas = <&audma0 0x75>, <&audma1 0x76>;
2200 dma-names = "rx", "tx";
2201 };
2202 ssiu70: ssiu-42 {
2203 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2204 dma-names = "rx", "tx";
2205 };
2206 ssiu80: ssiu-43 {
2207 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2208 dma-names = "rx", "tx";
2209 };
2210 ssiu90: ssiu-44 {
2211 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2212 dma-names = "rx", "tx";
2213 };
2214 ssiu91: ssiu-45 {
2215 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2216 dma-names = "rx", "tx";
2217 };
2218 ssiu92: ssiu-46 {
2219 dmas = <&audma0 0x81>, <&audma1 0x82>;
2220 dma-names = "rx", "tx";
2221 };
2222 ssiu93: ssiu-47 {
2223 dmas = <&audma0 0x83>, <&audma1 0x84>;
2224 dma-names = "rx", "tx";
2225 };
2226 ssiu94: ssiu-48 {
2227 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2228 dma-names = "rx", "tx";
2229 };
2230 ssiu95: ssiu-49 {
2231 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2232 dma-names = "rx", "tx";
2233 };
2234 ssiu96: ssiu-50 {
2235 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2236 dma-names = "rx", "tx";
2237 };
2238 ssiu97: ssiu-51 {
2239 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2240 dma-names = "rx", "tx";
2241 };
2242 };
2243
2244 rcar_sound,ssi {
2245 ssi0: ssi-0 {
2246 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2247 dmas = <&audma0 0x01>, <&audma1 0x02>;
2248 dma-names = "rx", "tx";
2249 };
2250 ssi1: ssi-1 {
2251 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2252 dmas = <&audma0 0x03>, <&audma1 0x04>;
2253 dma-names = "rx", "tx";
2254 };
2255 ssi2: ssi-2 {
2256 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2257 dmas = <&audma0 0x05>, <&audma1 0x06>;
2258 dma-names = "rx", "tx";
2259 };
2260 ssi3: ssi-3 {
2261 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2262 dmas = <&audma0 0x07>, <&audma1 0x08>;
2263 dma-names = "rx", "tx";
2264 };
2265 ssi4: ssi-4 {
2266 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2267 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2268 dma-names = "rx", "tx";
2269 };
2270 ssi5: ssi-5 {
2271 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2272 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2273 dma-names = "rx", "tx";
2274 };
2275 ssi6: ssi-6 {
2276 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2277 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2278 dma-names = "rx", "tx";
2279 };
2280 ssi7: ssi-7 {
2281 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2282 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2283 dma-names = "rx", "tx";
2284 };
2285 ssi8: ssi-8 {
2286 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2287 dmas = <&audma0 0x11>, <&audma1 0x12>;
2288 dma-names = "rx", "tx";
2289 };
2290 ssi9: ssi-9 {
2291 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2292 dmas = <&audma0 0x13>, <&audma1 0x14>;
2293 dma-names = "rx", "tx";
2294 };
2295 };
2296 };
2297
2298 audma0: dma-controller@ec700000 {
2299 compatible = "renesas,dmac-r8a7795",
2300 "renesas,rcar-dmac";
2301 reg = <0 0xec700000 0 0x10000>;
2302 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
2303 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
2304 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
2305 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
2306 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
2307 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
2308 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
2309 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
2310 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
2311 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
2312 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
2313 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
2314 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
2315 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
2316 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
2317 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
2318 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2319 interrupt-names = "error",
2320 "ch0", "ch1", "ch2", "ch3",
2321 "ch4", "ch5", "ch6", "ch7",
2322 "ch8", "ch9", "ch10", "ch11",
2323 "ch12", "ch13", "ch14", "ch15";
2324 clocks = <&cpg CPG_MOD 502>;
2325 clock-names = "fck";
2326 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2327 resets = <&cpg 502>;
2328 #dma-cells = <1>;
2329 dma-channels = <16>;
2330 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2331 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
2332 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
2333 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
2334 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
2335 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
2336 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
2337 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
2338 };
2339
2340 audma1: dma-controller@ec720000 {
2341 compatible = "renesas,dmac-r8a7795",
2342 "renesas,rcar-dmac";
2343 reg = <0 0xec720000 0 0x10000>;
2344 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
2345 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
2346 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
2347 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
2348 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
2349 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
2350 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
2351 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
2352 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
2353 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
2354 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
2355 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
2356 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
2357 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
2358 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
2359 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
2360 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2361 interrupt-names = "error",
2362 "ch0", "ch1", "ch2", "ch3",
2363 "ch4", "ch5", "ch6", "ch7",
2364 "ch8", "ch9", "ch10", "ch11",
2365 "ch12", "ch13", "ch14", "ch15";
2366 clocks = <&cpg CPG_MOD 501>;
2367 clock-names = "fck";
2368 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2369 resets = <&cpg 501>;
2370 #dma-cells = <1>;
2371 dma-channels = <16>;
2372 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
2373 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
2374 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
2375 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
2376 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
2377 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
2378 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
2379 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
2380 };
2381
2382 xhci0: usb@ee000000 {
2383 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
2384 reg = <0 0xee000000 0 0xc00>;
2385 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2386 clocks = <&cpg CPG_MOD 328>;
2387 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2388 resets = <&cpg 328>;
2389 status = "disabled";
2390 };
2391
2392 usb3_peri0: usb@ee020000 {
2393 compatible = "renesas,r8a7795-usb3-peri",
2394 "renesas,rcar-gen3-usb3-peri";
2395 reg = <0 0xee020000 0 0x400>;
2396 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2397 clocks = <&cpg CPG_MOD 328>;
2398 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2399 resets = <&cpg 328>;
2400 status = "disabled";
2401 };
2402
2403 ohci0: usb@ee080000 {
2404 compatible = "generic-ohci";
2405 reg = <0 0xee080000 0 0x100>;
2406 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2407 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2408 phys = <&usb2_phy0>;
2409 phy-names = "usb";
2410 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2411 resets = <&cpg 703>, <&cpg 704>;
2412 status = "disabled";
2413 };
2414
2415 ohci1: usb@ee0a0000 {
2416 compatible = "generic-ohci";
2417 reg = <0 0xee0a0000 0 0x100>;
2418 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2419 clocks = <&cpg CPG_MOD 702>;
2420 phys = <&usb2_phy1>;
2421 phy-names = "usb";
2422 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2423 resets = <&cpg 702>;
2424 status = "disabled";
2425 };
2426
2427 ohci2: usb@ee0c0000 {
2428 compatible = "generic-ohci";
2429 reg = <0 0xee0c0000 0 0x100>;
2430 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
2431 clocks = <&cpg CPG_MOD 701>;
2432 phys = <&usb2_phy2>;
2433 phy-names = "usb";
2434 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2435 resets = <&cpg 701>;
2436 status = "disabled";
2437 };
2438
2439 ohci3: usb@ee0e0000 {
2440 compatible = "generic-ohci";
2441 reg = <0 0xee0e0000 0 0x100>;
2442 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2443 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
2444 phys = <&usb2_phy3>;
2445 phy-names = "usb";
2446 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2447 resets = <&cpg 700>, <&cpg 705>;
2448 status = "disabled";
2449 };
2450
2451 ehci0: usb@ee080100 {
2452 compatible = "generic-ehci";
2453 reg = <0 0xee080100 0 0x100>;
2454 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2455 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2456 phys = <&usb2_phy0>;
2457 phy-names = "usb";
2458 companion = <&ohci0>;
2459 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2460 resets = <&cpg 703>, <&cpg 704>;
2461 status = "disabled";
2462 };
2463
2464 ehci1: usb@ee0a0100 {
2465 compatible = "generic-ehci";
2466 reg = <0 0xee0a0100 0 0x100>;
2467 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2468 clocks = <&cpg CPG_MOD 702>;
2469 phys = <&usb2_phy1>;
2470 phy-names = "usb";
2471 companion = <&ohci1>;
2472 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2473 resets = <&cpg 702>;
2474 status = "disabled";
2475 };
2476
2477 ehci2: usb@ee0c0100 {
2478 compatible = "generic-ehci";
2479 reg = <0 0xee0c0100 0 0x100>;
2480 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
2481 clocks = <&cpg CPG_MOD 701>;
2482 phys = <&usb2_phy2>;
2483 phy-names = "usb";
2484 companion = <&ohci2>;
2485 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2486 resets = <&cpg 701>;
2487 status = "disabled";
2488 };
2489
2490 ehci3: usb@ee0e0100 {
2491 compatible = "generic-ehci";
2492 reg = <0 0xee0e0100 0 0x100>;
2493 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2494 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
2495 phys = <&usb2_phy3>;
2496 phy-names = "usb";
2497 companion = <&ohci3>;
2498 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2499 resets = <&cpg 700>, <&cpg 705>;
2500 status = "disabled";
2501 };
2502
2503 usb2_phy0: usb-phy@ee080200 {
2504 compatible = "renesas,usb2-phy-r8a7795",
2505 "renesas,rcar-gen3-usb2-phy";
2506 reg = <0 0xee080200 0 0x700>;
2507 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2508 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2509 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2510 resets = <&cpg 703>, <&cpg 704>;
2511 #phy-cells = <0>;
2512 status = "disabled";
2513 };
2514
2515 usb2_phy1: usb-phy@ee0a0200 {
2516 compatible = "renesas,usb2-phy-r8a7795",
2517 "renesas,rcar-gen3-usb2-phy";
2518 reg = <0 0xee0a0200 0 0x700>;
2519 clocks = <&cpg CPG_MOD 702>;
2520 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2521 resets = <&cpg 702>;
2522 #phy-cells = <0>;
2523 status = "disabled";
2524 };
2525
2526 usb2_phy2: usb-phy@ee0c0200 {
2527 compatible = "renesas,usb2-phy-r8a7795",
2528 "renesas,rcar-gen3-usb2-phy";
2529 reg = <0 0xee0c0200 0 0x700>;
2530 clocks = <&cpg CPG_MOD 701>;
2531 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2532 resets = <&cpg 701>;
2533 #phy-cells = <0>;
2534 status = "disabled";
2535 };
2536
2537 usb2_phy3: usb-phy@ee0e0200 {
2538 compatible = "renesas,usb2-phy-r8a7795",
2539 "renesas,rcar-gen3-usb2-phy";
2540 reg = <0 0xee0e0200 0 0x700>;
2541 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2542 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
2543 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2544 resets = <&cpg 700>, <&cpg 705>;
2545 #phy-cells = <0>;
2546 status = "disabled";
2547 };
2548
2549 sdhi0: sd@ee100000 {
2550 compatible = "renesas,sdhi-r8a7795",
2551 "renesas,rcar-gen3-sdhi";
2552 reg = <0 0xee100000 0 0x2000>;
2553 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2554 clocks = <&cpg CPG_MOD 314>;
2555 max-frequency = <200000000>;
2556 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2557 resets = <&cpg 314>;
2558 status = "disabled";
2559 };
2560
2561 sdhi1: sd@ee120000 {
2562 compatible = "renesas,sdhi-r8a7795",
2563 "renesas,rcar-gen3-sdhi";
2564 reg = <0 0xee120000 0 0x2000>;
2565 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2566 clocks = <&cpg CPG_MOD 313>;
2567 max-frequency = <200000000>;
2568 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2569 resets = <&cpg 313>;
2570 status = "disabled";
2571 };
2572
2573 sdhi2: sd@ee140000 {
2574 compatible = "renesas,sdhi-r8a7795",
2575 "renesas,rcar-gen3-sdhi";
2576 reg = <0 0xee140000 0 0x2000>;
2577 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2578 clocks = <&cpg CPG_MOD 312>;
2579 max-frequency = <200000000>;
2580 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2581 resets = <&cpg 312>;
2582 status = "disabled";
2583 };
2584
2585 sdhi3: sd@ee160000 {
2586 compatible = "renesas,sdhi-r8a7795",
2587 "renesas,rcar-gen3-sdhi";
2588 reg = <0 0xee160000 0 0x2000>;
2589 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2590 clocks = <&cpg CPG_MOD 311>;
2591 max-frequency = <200000000>;
2592 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2593 resets = <&cpg 311>;
2594 status = "disabled";
2595 };
2596
2597 sata: sata@ee300000 {
2598 compatible = "renesas,sata-r8a7795",
2599 "renesas,rcar-gen3-sata";
2600 reg = <0 0xee300000 0 0x200000>;
2601 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602 clocks = <&cpg CPG_MOD 815>;
2603 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2604 resets = <&cpg 815>;
2605 status = "disabled";
2606 iommus = <&ipmmu_hc 2>;
2607 };
2608
2609 gic: interrupt-controller@f1010000 {
2610 compatible = "arm,gic-400";
2611 #interrupt-cells = <3>;
2612 #address-cells = <0>;
2613 interrupt-controller;
2614 reg = <0x0 0xf1010000 0 0x1000>,
2615 <0x0 0xf1020000 0 0x20000>,
2616 <0x0 0xf1040000 0 0x20000>,
2617 <0x0 0xf1060000 0 0x20000>;
2618 interrupts = <GIC_PPI 9
2619 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2620 clocks = <&cpg CPG_MOD 408>;
2621 clock-names = "clk";
2622 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2623 resets = <&cpg 408>;
2624 };
2625
2626 pciec0: pcie@fe000000 {
2627 compatible = "renesas,pcie-r8a7795",
2628 "renesas,pcie-rcar-gen3";
2629 reg = <0 0xfe000000 0 0x80000>;
2630 #address-cells = <3>;
2631 #size-cells = <2>;
2632 bus-range = <0x00 0xff>;
2633 device_type = "pci";
2634 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
2635 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
2636 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
2637 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2638 /* Map all possible DDR as inbound ranges */
2639 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2640 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2641 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2642 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2643 #interrupt-cells = <1>;
2644 interrupt-map-mask = <0 0 0 0>;
2645 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2646 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2647 clock-names = "pcie", "pcie_bus";
2648 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2649 resets = <&cpg 319>;
2650 status = "disabled";
2651 };
2652
2653 pciec1: pcie@ee800000 {
2654 compatible = "renesas,pcie-r8a7795",
2655 "renesas,pcie-rcar-gen3";
2656 reg = <0 0xee800000 0 0x80000>;
2657 #address-cells = <3>;
2658 #size-cells = <2>;
2659 bus-range = <0x00 0xff>;
2660 device_type = "pci";
2661 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
2662 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
2663 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
2664 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2665 /* Map all possible DDR as inbound ranges */
2666 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2667 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2668 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2669 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2670 #interrupt-cells = <1>;
2671 interrupt-map-mask = <0 0 0 0>;
2672 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2673 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2674 clock-names = "pcie", "pcie_bus";
2675 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2676 resets = <&cpg 318>;
2677 status = "disabled";
2678 };
2679
2680 imr-lx4@fe860000 {
2681 compatible = "renesas,r8a7795-imr-lx4",
2682 "renesas,imr-lx4";
2683 reg = <0 0xfe860000 0 0x2000>;
2684 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2685 clocks = <&cpg CPG_MOD 823>;
2686 power-domains = <&sysc R8A7795_PD_A3VC>;
2687 resets = <&cpg 823>;
2688 };
2689
2690 imr-lx4@fe870000 {
2691 compatible = "renesas,r8a7795-imr-lx4",
2692 "renesas,imr-lx4";
2693 reg = <0 0xfe870000 0 0x2000>;
2694 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2695 clocks = <&cpg CPG_MOD 822>;
2696 power-domains = <&sysc R8A7795_PD_A3VC>;
2697 resets = <&cpg 822>;
2698 };
2699
2700 imr-lx4@fe880000 {
2701 compatible = "renesas,r8a7795-imr-lx4",
2702 "renesas,imr-lx4";
2703 reg = <0 0xfe880000 0 0x2000>;
2704 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
2705 clocks = <&cpg CPG_MOD 821>;
2706 power-domains = <&sysc R8A7795_PD_A3VC>;
2707 resets = <&cpg 821>;
2708 };
2709
2710 imr-lx4@fe890000 {
2711 compatible = "renesas,r8a7795-imr-lx4",
2712 "renesas,imr-lx4";
2713 reg = <0 0xfe890000 0 0x2000>;
2714 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
2715 clocks = <&cpg CPG_MOD 820>;
2716 power-domains = <&sysc R8A7795_PD_A3VC>;
2717 resets = <&cpg 820>;
2718 };
2719
2720 fdp1@fe940000 {
2721 compatible = "renesas,fdp1";
2722 reg = <0 0xfe940000 0 0x2400>;
2723 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2724 clocks = <&cpg CPG_MOD 119>;
2725 power-domains = <&sysc R8A7795_PD_A3VP>;
2726 resets = <&cpg 119>;
2727 renesas,fcp = <&fcpf0>;
2728 };
2729
2730 fdp1@fe944000 {
2731 compatible = "renesas,fdp1";
2732 reg = <0 0xfe944000 0 0x2400>;
2733 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2734 clocks = <&cpg CPG_MOD 118>;
2735 power-domains = <&sysc R8A7795_PD_A3VP>;
2736 resets = <&cpg 118>;
2737 renesas,fcp = <&fcpf1>;
2738 };
2739
2740 fcpf0: fcp@fe950000 {
2741 compatible = "renesas,fcpf";
2742 reg = <0 0xfe950000 0 0x200>;
2743 clocks = <&cpg CPG_MOD 615>;
2744 power-domains = <&sysc R8A7795_PD_A3VP>;
2745 resets = <&cpg 615>;
2746 iommus = <&ipmmu_vp0 0>;
2747 };
2748
2749 fcpf1: fcp@fe951000 {
2750 compatible = "renesas,fcpf";
2751 reg = <0 0xfe951000 0 0x200>;
2752 clocks = <&cpg CPG_MOD 614>;
2753 power-domains = <&sysc R8A7795_PD_A3VP>;
2754 resets = <&cpg 614>;
2755 iommus = <&ipmmu_vp1 1>;
2756 };
2757
2758 fcpvb0: fcp@fe96f000 {
2759 compatible = "renesas,fcpv";
2760 reg = <0 0xfe96f000 0 0x200>;
2761 clocks = <&cpg CPG_MOD 607>;
2762 power-domains = <&sysc R8A7795_PD_A3VP>;
2763 resets = <&cpg 607>;
2764 iommus = <&ipmmu_vp0 5>;
2765 };
2766
2767 fcpvb1: fcp@fe92f000 {
2768 compatible = "renesas,fcpv";
2769 reg = <0 0xfe92f000 0 0x200>;
2770 clocks = <&cpg CPG_MOD 606>;
2771 power-domains = <&sysc R8A7795_PD_A3VP>;
2772 resets = <&cpg 606>;
2773 iommus = <&ipmmu_vp1 7>;
2774 };
2775
2776 fcpvi0: fcp@fe9af000 {
2777 compatible = "renesas,fcpv";
2778 reg = <0 0xfe9af000 0 0x200>;
2779 clocks = <&cpg CPG_MOD 611>;
2780 power-domains = <&sysc R8A7795_PD_A3VP>;
2781 resets = <&cpg 611>;
2782 iommus = <&ipmmu_vp0 8>;
2783 };
2784
2785 fcpvi1: fcp@fe9bf000 {
2786 compatible = "renesas,fcpv";
2787 reg = <0 0xfe9bf000 0 0x200>;
2788 clocks = <&cpg CPG_MOD 610>;
2789 power-domains = <&sysc R8A7795_PD_A3VP>;
2790 resets = <&cpg 610>;
2791 iommus = <&ipmmu_vp1 9>;
2792 };
2793
2794 fcpvd0: fcp@fea27000 {
2795 compatible = "renesas,fcpv";
2796 reg = <0 0xfea27000 0 0x200>;
2797 clocks = <&cpg CPG_MOD 603>;
2798 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2799 resets = <&cpg 603>;
2800 iommus = <&ipmmu_vi0 8>;
2801 };
2802
2803 fcpvd1: fcp@fea2f000 {
2804 compatible = "renesas,fcpv";
2805 reg = <0 0xfea2f000 0 0x200>;
2806 clocks = <&cpg CPG_MOD 602>;
2807 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2808 resets = <&cpg 602>;
2809 iommus = <&ipmmu_vi0 9>;
2810 };
2811
2812 fcpvd2: fcp@fea37000 {
2813 compatible = "renesas,fcpv";
2814 reg = <0 0xfea37000 0 0x200>;
2815 clocks = <&cpg CPG_MOD 601>;
2816 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2817 resets = <&cpg 601>;
2818 iommus = <&ipmmu_vi1 10>;
2819 };
2820
2821 vspbd: vsp@fe960000 {
2822 compatible = "renesas,vsp2";
2823 reg = <0 0xfe960000 0 0x8000>;
2824 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2825 clocks = <&cpg CPG_MOD 626>;
2826 power-domains = <&sysc R8A7795_PD_A3VP>;
2827 resets = <&cpg 626>;
2828
2829 renesas,fcp = <&fcpvb0>;
2830 };
2831
2832 vspbc: vsp@fe920000 {
2833 compatible = "renesas,vsp2";
2834 reg = <0 0xfe920000 0 0x8000>;
2835 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
2836 clocks = <&cpg CPG_MOD 624>;
2837 power-domains = <&sysc R8A7795_PD_A3VP>;
2838 resets = <&cpg 624>;
2839
2840 renesas,fcp = <&fcpvb1>;
2841 };
2842
2843 vspd0: vsp@fea20000 {
2844 compatible = "renesas,vsp2";
2845 reg = <0 0xfea20000 0 0x5000>;
2846 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2847 clocks = <&cpg CPG_MOD 623>;
2848 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2849 resets = <&cpg 623>;
2850
2851 renesas,fcp = <&fcpvd0>;
2852 };
2853
2854 vspd1: vsp@fea28000 {
2855 compatible = "renesas,vsp2";
2856 reg = <0 0xfea28000 0 0x5000>;
2857 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2858 clocks = <&cpg CPG_MOD 622>;
2859 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2860 resets = <&cpg 622>;
2861
2862 renesas,fcp = <&fcpvd1>;
2863 };
2864
2865 vspd2: vsp@fea30000 {
2866 compatible = "renesas,vsp2";
2867 reg = <0 0xfea30000 0 0x5000>;
2868 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2869 clocks = <&cpg CPG_MOD 621>;
2870 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2871 resets = <&cpg 621>;
2872
2873 renesas,fcp = <&fcpvd2>;
2874 };
2875
2876 vspi0: vsp@fe9a0000 {
2877 compatible = "renesas,vsp2";
2878 reg = <0 0xfe9a0000 0 0x8000>;
2879 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2880 clocks = <&cpg CPG_MOD 631>;
2881 power-domains = <&sysc R8A7795_PD_A3VP>;
2882 resets = <&cpg 631>;
2883
2884 renesas,fcp = <&fcpvi0>;
2885 };
2886
2887 vspi1: vsp@fe9b0000 {
2888 compatible = "renesas,vsp2";
2889 reg = <0 0xfe9b0000 0 0x8000>;
2890 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2891 clocks = <&cpg CPG_MOD 630>;
2892 power-domains = <&sysc R8A7795_PD_A3VP>;
2893 resets = <&cpg 630>;
2894
2895 renesas,fcp = <&fcpvi1>;
2896 };
2897
2898 csi20: csi2@fea80000 {
2899 compatible = "renesas,r8a7795-csi2";
2900 reg = <0 0xfea80000 0 0x10000>;
2901 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2902 clocks = <&cpg CPG_MOD 714>;
2903 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2904 resets = <&cpg 714>;
2905 status = "disabled";
2906
2907 ports {
2908 #address-cells = <1>;
2909 #size-cells = <0>;
2910
2911 port@1 {
2912 #address-cells = <1>;
2913 #size-cells = <0>;
2914
2915 reg = <1>;
2916
2917 csi20vin0: endpoint@0 {
2918 reg = <0>;
2919 remote-endpoint = <&vin0csi20>;
2920 };
2921 csi20vin1: endpoint@1 {
2922 reg = <1>;
2923 remote-endpoint = <&vin1csi20>;
2924 };
2925 csi20vin2: endpoint@2 {
2926 reg = <2>;
2927 remote-endpoint = <&vin2csi20>;
2928 };
2929 csi20vin3: endpoint@3 {
2930 reg = <3>;
2931 remote-endpoint = <&vin3csi20>;
2932 };
2933 csi20vin4: endpoint@4 {
2934 reg = <4>;
2935 remote-endpoint = <&vin4csi20>;
2936 };
2937 csi20vin5: endpoint@5 {
2938 reg = <5>;
2939 remote-endpoint = <&vin5csi20>;
2940 };
2941 csi20vin6: endpoint@6 {
2942 reg = <6>;
2943 remote-endpoint = <&vin6csi20>;
2944 };
2945 csi20vin7: endpoint@7 {
2946 reg = <7>;
2947 remote-endpoint = <&vin7csi20>;
2948 };
2949 };
2950 };
2951 };
2952
2953 csi40: csi2@feaa0000 {
2954 compatible = "renesas,r8a7795-csi2";
2955 reg = <0 0xfeaa0000 0 0x10000>;
2956 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2957 clocks = <&cpg CPG_MOD 716>;
2958 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2959 resets = <&cpg 716>;
2960 status = "disabled";
2961
2962 ports {
2963 #address-cells = <1>;
2964 #size-cells = <0>;
2965
2966 port@1 {
2967 #address-cells = <1>;
2968 #size-cells = <0>;
2969
2970 reg = <1>;
2971
2972 csi40vin0: endpoint@0 {
2973 reg = <0>;
2974 remote-endpoint = <&vin0csi40>;
2975 };
2976 csi40vin1: endpoint@1 {
2977 reg = <1>;
2978 remote-endpoint = <&vin1csi40>;
2979 };
2980 csi40vin2: endpoint@2 {
2981 reg = <2>;
2982 remote-endpoint = <&vin2csi40>;
2983 };
2984 csi40vin3: endpoint@3 {
2985 reg = <3>;
2986 remote-endpoint = <&vin3csi40>;
2987 };
2988 };
2989 };
2990 };
2991
2992 csi41: csi2@feab0000 {
2993 compatible = "renesas,r8a7795-csi2";
2994 reg = <0 0xfeab0000 0 0x10000>;
2995 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
2996 clocks = <&cpg CPG_MOD 715>;
2997 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2998 resets = <&cpg 715>;
2999 status = "disabled";
3000
3001 ports {
3002 #address-cells = <1>;
3003 #size-cells = <0>;
3004
3005 port@1 {
3006 #address-cells = <1>;
3007 #size-cells = <0>;
3008
3009 reg = <1>;
3010
3011 csi41vin4: endpoint@0 {
3012 reg = <0>;
3013 remote-endpoint = <&vin4csi41>;
3014 };
3015 csi41vin5: endpoint@1 {
3016 reg = <1>;
3017 remote-endpoint = <&vin5csi41>;
3018 };
3019 csi41vin6: endpoint@2 {
3020 reg = <2>;
3021 remote-endpoint = <&vin6csi41>;
3022 };
3023 csi41vin7: endpoint@3 {
3024 reg = <3>;
3025 remote-endpoint = <&vin7csi41>;
3026 };
3027 };
3028 };
3029 };
3030
3031 hdmi0: hdmi@fead0000 {
3032 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
3033 reg = <0 0xfead0000 0 0x10000>;
3034 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
3035 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
3036 clock-names = "iahb", "isfr";
3037 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3038 resets = <&cpg 729>;
3039 status = "disabled";
3040
3041 ports {
3042 #address-cells = <1>;
3043 #size-cells = <0>;
3044 port@0 {
3045 reg = <0>;
3046 dw_hdmi0_in: endpoint {
3047 remote-endpoint = <&du_out_hdmi0>;
3048 };
3049 };
3050 port@1 {
3051 reg = <1>;
3052 };
3053 port@2 {
3054 /* HDMI sound */
3055 reg = <2>;
3056 };
3057 };
3058 };
3059
3060 hdmi1: hdmi@feae0000 {
3061 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
3062 reg = <0 0xfeae0000 0 0x10000>;
3063 interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
3064 clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>;
3065 clock-names = "iahb", "isfr";
3066 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3067 resets = <&cpg 728>;
3068 status = "disabled";
3069
3070 ports {
3071 #address-cells = <1>;
3072 #size-cells = <0>;
3073 port@0 {
3074 reg = <0>;
3075 dw_hdmi1_in: endpoint {
3076 remote-endpoint = <&du_out_hdmi1>;
3077 };
3078 };
3079 port@1 {
3080 reg = <1>;
3081 };
3082 port@2 {
3083 /* HDMI sound */
3084 reg = <2>;
3085 };
3086 };
3087 };
3088
3089 du: display@feb00000 {
3090 compatible = "renesas,du-r8a7795";
3091 reg = <0 0xfeb00000 0 0x80000>;
3092 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3093 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3094 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3095 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
3096 clocks = <&cpg CPG_MOD 724>,
3097 <&cpg CPG_MOD 723>,
3098 <&cpg CPG_MOD 722>,
3099 <&cpg CPG_MOD 721>;
3100 clock-names = "du.0", "du.1", "du.2", "du.3";
3101 vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
3102 status = "disabled";
3103
3104 ports {
3105 #address-cells = <1>;
3106 #size-cells = <0>;
3107
3108 port@0 {
3109 reg = <0>;
3110 du_out_rgb: endpoint {
3111 };
3112 };
3113 port@1 {
3114 reg = <1>;
3115 du_out_hdmi0: endpoint {
3116 remote-endpoint = <&dw_hdmi0_in>;
3117 };
3118 };
3119 port@2 {
3120 reg = <2>;
3121 du_out_hdmi1: endpoint {
3122 remote-endpoint = <&dw_hdmi1_in>;
3123 };
3124 };
3125 port@3 {
3126 reg = <3>;
3127 du_out_lvds0: endpoint {
3128 remote-endpoint = <&lvds0_in>;
3129 };
3130 };
3131 };
3132 };
3133
3134 lvds0: lvds@feb90000 {
3135 compatible = "renesas,r8a7795-lvds";
3136 reg = <0 0xfeb90000 0 0x14>;
3137 clocks = <&cpg CPG_MOD 727>;
3138 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
3139 resets = <&cpg 727>;
3140 status = "disabled";
3141
3142 ports {
3143 #address-cells = <1>;
3144 #size-cells = <0>;
3145
3146 port@0 {
3147 reg = <0>;
3148 lvds0_in: endpoint {
3149 remote-endpoint = <&du_out_lvds0>;
3150 };
3151 };
3152 port@1 {
3153 reg = <1>;
3154 lvds0_out: endpoint {
3155 };
3156 };
3157 };
3158 };
3159
3160 prr: chipid@fff00044 {
3161 compatible = "renesas,prr";
3162 reg = <0 0xfff00044 0 4>;
3163 };
3164 };
3165
3166 thermal-zones {
3167 sensor_thermal1: sensor-thermal1 {
3168 polling-delay-passive = <250>;
3169 polling-delay = <1000>;
3170 thermal-sensors = <&tsc 0>;
3171
3172 trips {
3173 sensor1_passive: sensor1-passive {
3174 temperature = <95000>;
3175 hysteresis = <1000>;
3176 type = "passive";
3177 };
3178 sensor1_crit: sensor1-crit {
3179 temperature = <120000>;
3180 hysteresis = <1000>;
3181 type = "critical";
3182 };
3183 };
3184
3185 cooling-maps {
3186 map0 {
3187 trip = <&sensor1_passive>;
3188 cooling-device = <&a57_0 4 4>,
3189 <&a57_1 4 4>,
3190 <&a57_2 4 4>,
3191 <&a57_3 4 4>;
3192 };
3193 };
3194 };
3195
3196 sensor_thermal2: sensor-thermal2 {
3197 polling-delay-passive = <250>;
3198 polling-delay = <1000>;
3199 thermal-sensors = <&tsc 1>;
3200
3201 trips {
3202 sensor2_passive: sensor2-passive {
3203 temperature = <95000>;
3204 hysteresis = <1000>;
3205 type = "passive";
3206 };
3207 sensor2_crit: sensor2-crit {
3208 temperature = <120000>;
3209 hysteresis = <1000>;
3210 type = "critical";
3211 };
3212 };
3213
3214 cooling-maps {
3215 map0 {
3216 trip = <&sensor2_passive>;
3217 cooling-device = <&a57_0 4 4>,
3218 <&a57_1 4 4>,
3219 <&a57_2 4 4>,
3220 <&a57_3 4 4>;
3221 };
3222 };
3223 };
3224
3225 sensor_thermal3: sensor-thermal3 {
3226 polling-delay-passive = <250>;
3227 polling-delay = <1000>;
3228 thermal-sensors = <&tsc 2>;
3229
3230 trips {
3231 sensor3_passive: sensor3-passive {
3232 temperature = <95000>;
3233 hysteresis = <1000>;
3234 type = "passive";
3235 };
3236 sensor3_crit: sensor3-crit {
3237 temperature = <120000>;
3238 hysteresis = <1000>;
3239 type = "critical";
3240 };
3241 };
3242
3243 cooling-maps {
3244 map0 {
3245 trip = <&sensor3_passive>;
3246 cooling-device = <&a57_0 4 4>,
3247 <&a57_1 4 4>,
3248 <&a57_2 4 4>,
3249 <&a57_3 4 4>;
3250 };
3251 };
3252 };
3253 };
3254
3255 timer {
3256 compatible = "arm,armv8-timer";
3257 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3258 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3259 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3260 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3261 };
3262
3263 /* External USB clocks - can be overridden by the board */
3264 usb3s0_clk: usb3s0 {
3265 compatible = "fixed-clock";
3266 #clock-cells = <0>;
3267 clock-frequency = <0>;
3268 };
3269
3270 usb_extal_clk: usb_extal {
3271 compatible = "fixed-clock";
3272 #clock-cells = <0>;
3273 clock-frequency = <0>;
3274 };
3275 };
"Das U-Boot" Source Tree