arch/arm/dts/rk3288-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include "rockchip-u-boot.dtsi"
   7 #include "rockchip-optee.dtsi"
   8
   9 / {
  10         aliases {
  11                 gpio0 = &gpio0;
  12                 gpio1 = &gpio1;
  13                 gpio2 = &gpio2;
  14                 gpio3 = &gpio3;
  15                 gpio4 = &gpio4;
  16                 gpio5 = &gpio5;
  17                 gpio6 = &gpio6;
  18                 gpio7 = &gpio7;
  19                 gpio8 = &gpio8;
  20                 mmc0 = &emmc;
  21                 mmc1 = &sdmmc;
  22                 mmc2 = &sdio0;
  23                 mmc3 = &sdio1;
  24         };
  25
  26         chosen {
  27                 u-boot,spl-boot-order = \
  28                         "same-as-spl", &emmc, &sdmmc;
  29         };
  30
  31         dmc: dmc@ff610000 {
  32                 compatible = "rockchip,rk3288-dmc", "syscon";
  33                 reg = <0xff610000 0x3fc
  34                        0xff620000 0x294
  35                        0xff630000 0x3fc
  36                        0xff640000 0x294>;
  37                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
  38                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
  39                          <&cru ARMCLK>;
  40                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
  41                               "pclk_ddrupctl1", "pclk_publ1",
  42                               "arm_clk";
  43                 rockchip,cru = <&cru>;
  44                 rockchip,grf = <&grf>;
  45                 rockchip,noc = <&noc>;
  46                 rockchip,pmu = <&pmu>;
  47                 rockchip,sgrf = <&sgrf>;
  48                 rockchip,sram = <&ddr_sram>;
  49                 bootph-all;
  50         };
  51
  52         noc: syscon@ffac0000 {
  53                 compatible = "rockchip,rk3288-noc", "syscon";
  54                 reg = <0xffac0000 0x2000>;
  55                 bootph-all;
  56         };
  57 };
  58
  59 #if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
  60 &binman {
  61         rom {
  62                 filename = "u-boot.rom";
  63                 size = <0x400000>;
  64                 pad-byte = <0xff>;
  65
  66                 mkimage {
  67                         args = "-n rk3288 -T rkspi";
  68                         u-boot-spl {
  69                         };
  70                 };
  71                 u-boot-img {
  72                         offset = <0x20000>;
  73                 };
  74                 u-boot {
  75                         offset = <0x300000>;
  76                 };
  77                 fdtmap {
  78                 };
  79         };
  80 };
  81 #endif
  82
  83 &bus_intmem {
  84         ddr_sram: ddr-sram@1000 {
  85                 compatible = "rockchip,rk3288-ddr-sram";
  86                 reg = <0x1000 0x4000>;
  87         };
  88 };
  89
  90 &cru {
  91         bootph-all;
  92 };
  93
  94 &gpio7 {
  95         bootph-all;
  96 };
  97
  98 &grf {
  99         bootph-all;
 100 };
 101
 102 &pmu {
 103         bootph-all;
 104 };
 105
 106 &sgrf {
 107         bootph-all;
 108 };
 109
 110 &uart0 {
 111         clock-frequency = <24000000>;
 112 };
 113
 114 &uart1 {
 115         clock-frequency = <24000000>;
 116 };
 117
 118 &uart2 {
 119         clock-frequency = <24000000>;
 120 };
 121
 122 &uart3 {
 123         clock-frequency = <24000000>;
 124 };
 125
 126 &vopb {
 127         bootph-all;
 128 };
 129
 130 &vopl {
 131         bootph-all;
 132 };