arch/arm/dts/rk3288.dtsi

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0+
   3  */
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3288-cru.h>
  10 #include <dt-bindings/power-domain/rk3288.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         compatible = "rockchip,rk3288";
  16
  17         interrupt-parent = <&gic>;
  18         aliases {
  19                 gpio0 = &gpio0;
  20                 gpio1 = &gpio1;
  21                 gpio2 = &gpio2;
  22                 gpio3 = &gpio3;
  23                 gpio4 = &gpio4;
  24                 gpio5 = &gpio5;
  25                 gpio6 = &gpio6;
  26                 gpio7 = &gpio7;
  27                 gpio8 = &gpio8;
  28                 i2c0 = &i2c0;
  29                 i2c1 = &i2c1;
  30                 i2c2 = &i2c2;
  31                 i2c3 = &i2c3;
  32                 i2c4 = &i2c4;
  33                 i2c5 = &i2c5;
  34                 mmc0 = &emmc;
  35                 mmc1 = &sdmmc;
  36                 mmc2 = &sdio0;
  37                 mmc3 = &sdio1;
  38                 mshc0 = &emmc;
  39                 mshc1 = &sdmmc;
  40                 mshc2 = &sdio0;
  41                 mshc3 = &sdio1;
  42                 serial0 = &uart0;
  43                 serial1 = &uart1;
  44                 serial2 = &uart2;
  45                 serial3 = &uart3;
  46                 serial4 = &uart4;
  47                 spi0 = &spi0;
  48                 spi1 = &spi1;
  49                 spi2 = &spi2;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56                 rockchip,pmu = <&pmu>;
  57
  58                 cpu0: cpu@500 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x500>;
  62                         operating-points = <
  63                                 /* KHz    uV */
  64                                 1800000 1400000
  65                                 1704000 1350000
  66                                 1608000 1300000
  67                                 1512000 1250000
  68                                 1416000 1200000
  69                                 1200000 1100000
  70                                 1008000 1050000
  71                                  816000 1000000
  72                                  696000  950000
  73                                  600000  900000
  74                                  408000  900000
  75                                  216000  900000
  76                                  126000  900000
  77                         >;
  78                         #cooling-cells = <2>; /* min followed by max */
  79                         clock-latency = <40000>;
  80                         clocks = <&cru ARMCLK>;
  81                         resets = <&cru SRST_CORE0>;
  82                 };
  83                 cpu@501 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a12";
  86                         reg = <0x501>;
  87                         resets = <&cru SRST_CORE1>;
  88                 };
  89                 cpu@502 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a12";
  92                         reg = <0x502>;
  93                         resets = <&cru SRST_CORE2>;
  94                 };
  95                 cpu@503 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a12";
  98                         reg = <0x503>;
  99                         resets = <&cru SRST_CORE3>;
 100                 };
 101         };
 102
 103         amba {
 104                 compatible = "arm,amba-bus";
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges;
 108
 109                 dmac_peri: dma-controller@ff250000 {
 110                         compatible = "arm,pl330", "arm,primecell";
 111                         broken-no-flushp;
 112                         reg = <0xff250000 0x4000>;
 113                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 114                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 115                         #dma-cells = <1>;
 116                         clocks = <&cru ACLK_DMAC2>;
 117                         clock-names = "apb_pclk";
 118                 };
 119
 120                 dmac_bus_ns: dma-controller@ff600000 {
 121                         compatible = "arm,pl330", "arm,primecell";
 122                         broken-no-flushp;
 123                         reg = <0xff600000 0x4000>;
 124                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 125                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 126                         #dma-cells = <1>;
 127                         clocks = <&cru ACLK_DMAC1>;
 128                         clock-names = "apb_pclk";
 129                         status = "disabled";
 130                 };
 131
 132                 dmac_bus_s: dma-controller@ffb20000 {
 133                         compatible = "arm,pl330", "arm,primecell";
 134                         broken-no-flushp;
 135                         reg = <0xffb20000 0x4000>;
 136                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 138                         #dma-cells = <1>;
 139                         clocks = <&cru ACLK_DMAC1>;
 140                         clock-names = "apb_pclk";
 141                 };
 142         };
 143
 144         xin24m: oscillator {
 145                 compatible = "fixed-clock";
 146                 clock-frequency = <24000000>;
 147                 clock-output-names = "xin24m";
 148                 #clock-cells = <0>;
 149         };
 150
 151         timer {
 152                 arm,use-physical-timer;
 153                 compatible = "arm,armv7-timer";
 154                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 155                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 156                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 157                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 158                 clock-frequency = <24000000>;
 159                 always-on;
 160         };
 161
 162         display-subsystem {
 163                 compatible = "rockchip,display-subsystem";
 164                 ports = <&vopl_out>, <&vopb_out>;
 165         };
 166
 167         sdmmc: dwmmc@ff0c0000 {
 168                 compatible = "rockchip,rk3288-dw-mshc";
 169                 clock-freq-min-max = <400000 150000000>;
 170                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 171                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 172                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 173                 fifo-depth = <0x100>;
 174                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 175                 reg = <0xff0c0000 0x4000>;
 176                 status = "disabled";
 177         };
 178
 179         sdio0: dwmmc@ff0d0000 {
 180                 compatible = "rockchip,rk3288-dw-mshc";
 181                 clock-freq-min-max = <400000 150000000>;
 182                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 183                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 184                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 185                 fifo-depth = <0x100>;
 186                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 187                 reg = <0xff0d0000 0x4000>;
 188                 status = "disabled";
 189         };
 190
 191         sdio1: dwmmc@ff0e0000 {
 192                 compatible = "rockchip,rk3288-dw-mshc";
 193                 clock-freq-min-max = <400000 150000000>;
 194                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 195                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 196                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 197                 fifo-depth = <0x100>;
 198                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 199                 reg = <0xff0e0000 0x4000>;
 200                 status = "disabled";
 201         };
 202
 203         emmc: dwmmc@ff0f0000 {
 204                 compatible = "rockchip,rk3288-dw-mshc";
 205                 clock-freq-min-max = <400000 150000000>;
 206                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 207                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 208                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 209                 fifo-depth = <0x100>;
 210                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 211                 reg = <0xff0f0000 0x4000>;
 212                 status = "disabled";
 213         };
 214
 215         saradc: saradc@ff100000 {
 216                 compatible = "rockchip,saradc";
 217                 reg = <0xff100000 0x100>;
 218                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 219                 #io-channel-cells = <1>;
 220                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 221                 clock-names = "saradc", "apb_pclk";
 222                 status = "disabled";
 223         };
 224
 225         spi0: spi@ff110000 {
 226                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 227                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 228                 clock-names = "spiclk", "apb_pclk";
 229                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 230                 dma-names = "tx", "rx";
 231                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 232                 pinctrl-names = "default";
 233                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 234                 reg = <0xff110000 0x1000>;
 235                 #address-cells = <1>;
 236                 #size-cells = <0>;
 237                 status = "disabled";
 238         };
 239
 240         spi1: spi@ff120000 {
 241                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 242                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 243                 clock-names = "spiclk", "apb_pclk";
 244                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 245                 dma-names = "tx", "rx";
 246                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 249                 reg = <0xff120000 0x1000>;
 250                 #address-cells = <1>;
 251                 #size-cells = <0>;
 252                 status = "disabled";
 253         };
 254
 255         spi2: spi@ff130000 {
 256                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 257                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 258                 clock-names = "spiclk", "apb_pclk";
 259                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 260                 dma-names = "tx", "rx";
 261                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 264                 reg = <0xff130000 0x1000>;
 265                 #address-cells = <1>;
 266                 #size-cells = <0>;
 267                 status = "disabled";
 268         };
 269
 270         i2c1: i2c@ff140000 {
 271                 compatible = "rockchip,rk3288-i2c";
 272                 reg = <0xff140000 0x1000>;
 273                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 clock-names = "i2c";
 277                 clocks = <&cru PCLK_I2C1>;
 278                 pinctrl-names = "default";
 279                 pinctrl-0 = <&i2c1_xfer>;
 280                 status = "disabled";
 281         };
 282
 283         i2c3: i2c@ff150000 {
 284                 compatible = "rockchip,rk3288-i2c";
 285                 reg = <0xff150000 0x1000>;
 286                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289                 clock-names = "i2c";
 290                 clocks = <&cru PCLK_I2C3>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&i2c3_xfer>;
 293                 status = "disabled";
 294         };
 295
 296         i2c4: i2c@ff160000 {
 297                 compatible = "rockchip,rk3288-i2c";
 298                 reg = <0xff160000 0x1000>;
 299                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 clock-names = "i2c";
 303                 clocks = <&cru PCLK_I2C4>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&i2c4_xfer>;
 306                 status = "disabled";
 307         };
 308
 309         i2c5: i2c@ff170000 {
 310                 compatible = "rockchip,rk3288-i2c";
 311                 reg = <0xff170000 0x1000>;
 312                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 clock-names = "i2c";
 316                 clocks = <&cru PCLK_I2C5>;
 317                 pinctrl-names = "default";
 318                 pinctrl-0 = <&i2c5_xfer>;
 319                 status = "disabled";
 320         };
 321         uart0: serial@ff180000 {
 322                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 323                 reg = <0xff180000 0x100>;
 324                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 325                 reg-shift = <2>;
 326                 reg-io-width = <4>;
 327                 clock-frequency = <24000000>;
 328                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 329                 clock-names = "baudclk", "apb_pclk";
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&uart0_xfer>;
 332                 status = "disabled";
 333         };
 334
 335         uart1: serial@ff190000 {
 336                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 337                 reg = <0xff190000 0x100>;
 338                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 339                 reg-shift = <2>;
 340                 reg-io-width = <4>;
 341                 clock-frequency = <24000000>;
 342                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 343                 clock-names = "baudclk", "apb_pclk";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&uart1_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         uart2: serial@ff690000 {
 350                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 351                 reg = <0xff690000 0x100>;
 352                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 353                 reg-shift = <2>;
 354                 reg-io-width = <4>;
 355                 clock-frequency = <24000000>;
 356                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 357                 clock-names = "baudclk", "apb_pclk";
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&uart2_xfer>;
 360                 status = "disabled";
 361         };
 362         uart3: serial@ff1b0000 {
 363                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 364                 reg = <0xff1b0000 0x100>;
 365                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 366                 reg-shift = <2>;
 367                 reg-io-width = <4>;
 368                 clock-frequency = <24000000>;
 369                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 370                 clock-names = "baudclk", "apb_pclk";
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&uart3_xfer>;
 373                 status = "disabled";
 374         };
 375
 376         uart4: serial@ff1c0000 {
 377                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 378                 reg = <0xff1c0000 0x100>;
 379                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 380                 reg-shift = <2>;
 381                 reg-io-width = <4>;
 382                 clock-frequency = <24000000>;
 383                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 384                 clock-names = "baudclk", "apb_pclk";
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&uart4_xfer>;
 387                 status = "disabled";
 388         };
 389         thermal: thermal-zones {
 390                 #include "rk3288-thermal.dtsi"
 391         };
 392
 393         tsadc: tsadc@ff280000 {
 394                 compatible = "rockchip,rk3288-tsadc";
 395                 reg = <0xff280000 0x100>;
 396                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 398                 clock-names = "tsadc", "apb_pclk";
 399                 resets = <&cru SRST_TSADC>;
 400                 reset-names = "tsadc-apb";
 401                 pinctrl-names = "otp_out";
 402                 pinctrl-0 = <&otp_out>;
 403                 #thermal-sensor-cells = <1>;
 404                 hw-shut-temp = <125000>;
 405                 status = "disabled";
 406         };
 407
 408         gmac: ethernet@ff290000 {
 409                 compatible = "rockchip,rk3288-gmac";
 410                 reg = <0xff290000 0x10000>;
 411                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 412                 interrupt-names = "macirq";
 413                 rockchip,grf = <&grf>;
 414                 clocks = <&cru SCLK_MAC>,
 415                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 416                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 417                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 418                 clock-names = "stmmaceth",
 419                         "mac_clk_rx", "mac_clk_tx",
 420                         "clk_mac_ref", "clk_mac_refout",
 421                         "aclk_mac", "pclk_mac";
 422         };
 423
 424         usb_host0_ehci: usb@ff500000 {
 425                 compatible = "generic-ehci";
 426                 reg = <0xff500000 0x100>;
 427                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&cru HCLK_USBHOST0>;
 429                 clock-names = "usbhost";
 430                 phys = <&usbphy1>;
 431                 phy-names = "usb";
 432                 status = "disabled";
 433         };
 434
 435         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 436
 437         usb_host1: usb@ff540000 {
 438                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 439                                 "snps,dwc2";
 440                 reg = <0xff540000 0x40000>;
 441                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&cru HCLK_USBHOST1>;
 443                 clock-names = "otg";
 444                 phys = <&usbphy2>;
 445                 phy-names = "usb2-phy";
 446                 status = "disabled";
 447         };
 448
 449         usb_otg: usb@ff580000 {
 450                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 451                                 "snps,dwc2";
 452                 reg = <0xff580000 0x40000>;
 453                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&cru HCLK_OTG0>;
 455                 clock-names = "otg";
 456                 phys = <&usbphy0>;
 457                 phy-names = "usb2-phy";
 458                 status = "disabled";
 459         };
 460
 461         usb_hsic: usb@ff5c0000 {
 462                 compatible = "generic-ehci";
 463                 reg = <0xff5c0000 0x100>;
 464                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&cru HCLK_HSIC>;
 466                 clock-names = "usbhost";
 467                 status = "disabled";
 468         };
 469
 470         dmc: dmc@ff610000 {
 471                 u-boot,dm-pre-reloc;
 472                 compatible = "rockchip,rk3288-dmc", "syscon";
 473                 rockchip,cru = <&cru>;
 474                 rockchip,grf = <&grf>;
 475                 rockchip,pmu = <&pmu>;
 476                 rockchip,sgrf = <&sgrf>;
 477                 rockchip,noc = <&noc>;
 478                 reg = <0xff610000 0x3fc
 479                        0xff620000 0x294
 480                        0xff630000 0x3fc
 481                        0xff640000 0x294>;
 482                 rockchip,sram = <&ddr_sram>;
 483                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 484                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 485                          <&cru ARMCLK>;
 486                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 487                               "pclk_ddrupctl1", "pclk_publ1",
 488                               "arm_clk";
 489         };
 490
 491         i2c0: i2c@ff650000 {
 492                 compatible = "rockchip,rk3288-i2c";
 493                 reg = <0xff650000 0x1000>;
 494                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 clock-names = "i2c";
 498                 clocks = <&cru PCLK_I2C0>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c0_xfer>;
 501                 status = "disabled";
 502         };
 503
 504         i2c2: i2c@ff660000 {
 505                 compatible = "rockchip,rk3288-i2c";
 506                 reg = <0xff660000 0x1000>;
 507                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 clock-names = "i2c";
 511                 clocks = <&cru PCLK_I2C2>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c2_xfer>;
 514                 status = "disabled";
 515         };
 516
 517         pwm0: pwm@ff680000 {
 518                 compatible = "rockchip,rk3288-pwm";
 519                 reg = <0xff680000 0x10>;
 520                 #pwm-cells = <3>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&pwm0_pin>;
 523                 clocks = <&cru PCLK_PWM>;
 524                 clock-names = "pwm";
 525                 rockchip,grf = <&grf>;
 526                 status = "disabled";
 527         };
 528
 529         pwm1: pwm@ff680010 {
 530                 compatible = "rockchip,rk3288-pwm";
 531                 reg = <0xff680010 0x10>;
 532                 #pwm-cells = <3>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&pwm1_pin>;
 535                 clocks = <&cru PCLK_PWM>;
 536                 clock-names = "pwm";
 537                 rockchip,grf = <&grf>;
 538                 status = "disabled";
 539         };
 540
 541         pwm2: pwm@ff680020 {
 542                 compatible = "rockchip,rk3288-pwm";
 543                 reg = <0xff680020 0x10>;
 544                 #pwm-cells = <3>;
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&pwm2_pin>;
 547                 clocks = <&cru PCLK_PWM>;
 548                 clock-names = "pwm";
 549                 rockchip,grf = <&grf>;
 550                 status = "disabled";
 551         };
 552
 553         pwm3: pwm@ff680030 {
 554                 compatible = "rockchip,rk3288-pwm";
 555                 reg = <0xff680030 0x10>;
 556                 #pwm-cells = <2>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&pwm3_pin>;
 559                 clocks = <&cru PCLK_PWM>;
 560                 clock-names = "pwm";
 561                 rockchip,grf = <&grf>;
 562                 status = "disabled";
 563         };
 564
 565         bus_intmem@ff700000 {
 566                 compatible = "mmio-sram";
 567                 reg = <0xff700000 0x18000>;
 568                 #address-cells = <1>;
 569                 #size-cells = <1>;
 570                 ranges = <0 0xff700000 0x18000>;
 571                 smp-sram@0 {
 572                         compatible = "rockchip,rk3066-smp-sram";
 573                         reg = <0x00 0x10>;
 574                 };
 575                 ddr_sram: ddr-sram@1000 {
 576                         compatible = "rockchip,rk3288-ddr-sram";
 577                         reg = <0x1000 0x4000>;
 578                 };
 579         };
 580
 581         sram@ff720000 {
 582                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 583                 reg = <0xff720000 0x1000>;
 584         };
 585
 586         pmu: power-management@ff730000 {
 587                 u-boot,dm-pre-reloc;
 588                 compatible = "rockchip,rk3288-pmu", "syscon";
 589                 reg = <0xff730000 0x100>;
 590         };
 591
 592         sgrf: syscon@ff740000 {
 593                 u-boot,dm-pre-reloc;
 594                 compatible = "rockchip,rk3288-sgrf", "syscon";
 595                 reg = <0xff740000 0x1000>;
 596         };
 597
 598         cru: clock-controller@ff760000 {
 599                 compatible = "rockchip,rk3288-cru";
 600                 reg = <0xff760000 0x1000>;
 601                 rockchip,grf = <&grf>;
 602                 u-boot,dm-pre-reloc;
 603                 #clock-cells = <1>;
 604                 #reset-cells = <1>;
 605                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 606                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 607                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 608                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 609                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 610                                   <&cru PCLK_PERI>;
 611                 assigned-clock-rates = <0>, <0>,
 612                                        <594000000>, <400000000>,
 613                                        <500000000>, <300000000>,
 614                                        <150000000>, <75000000>,
 615                                        <300000000>, <150000000>,
 616                                        <75000000>;
 617                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 618         };
 619
 620         grf: syscon@ff770000 {
 621                 u-boot,dm-pre-reloc;
 622                 compatible = "rockchip,rk3288-grf", "syscon";
 623                 reg = <0xff770000 0x1000>;
 624         };
 625
 626         wdt: watchdog@ff800000 {
 627                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 628                 reg = <0xff800000 0x100>;
 629                 clocks = <&cru PCLK_WDT>;
 630                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 631                 status = "disabled";
 632         };
 633
 634         i2s: i2s@ff890000 {
 635                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 636                 reg = <0xff890000 0x10000>;
 637                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 638                 #address-cells = <1>;
 639                 #size-cells = <0>;
 640                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 641                 dma-names = "tx", "rx";
 642                 clock-names = "i2s_hclk", "i2s_clk";
 643                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&i2s0_bus>;
 646                 status = "disabled";
 647         };
 648
 649         vopb: vop@ff930000 {
 650                 compatible = "rockchip,rk3288-vop";
 651                 reg = <0xff930000 0x19c>;
 652                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 654                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 655                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 656                 reset-names = "axi", "ahb", "dclk";
 657                 iommus = <&vopb_mmu>;
 658                 power-domains = <&power RK3288_PD_VIO>;
 659                 status = "disabled";
 660                 vopb_out: port {
 661                         #address-cells = <1>;
 662                         #size-cells = <0>;
 663                         vopb_out_edp: endpoint@0 {
 664                                 reg = <0>;
 665                                 remote-endpoint = <&edp_in_vopb>;
 666                         };
 667                         vopb_out_hdmi: endpoint@1 {
 668                                 reg = <1>;
 669                                 remote-endpoint = <&hdmi_in_vopb>;
 670                         };
 671                 };
 672         };
 673
 674         vopb_mmu: iommu@ff930300 {
 675                 compatible = "rockchip,iommu";
 676                 reg = <0xff930300 0x100>;
 677                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 678                 interrupt-names = "vopb_mmu";
 679                 power-domains = <&power RK3288_PD_VIO>;
 680                 #iommu-cells = <0>;
 681                 status = "disabled";
 682         };
 683
 684         vopl: vop@ff940000 {
 685                 compatible = "rockchip,rk3288-vop";
 686                 reg = <0xff940000 0x19c>;
 687                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 689                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 690                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 691                 reset-names = "axi", "ahb", "dclk";
 692                 iommus = <&vopl_mmu>;
 693                 power-domains = <&power RK3288_PD_VIO>;
 694                 status = "disabled";
 695                 vopl_out: port {
 696                         #address-cells = <1>;
 697                         #size-cells = <0>;
 698                         vopl_out_edp: endpoint@0 {
 699                                 reg = <0>;
 700                                 remote-endpoint = <&edp_in_vopl>;
 701                         };
 702                         vopl_out_hdmi: endpoint@1 {
 703                                 reg = <1>;
 704                                 remote-endpoint = <&hdmi_in_vopl>;
 705                         };
 706
 707                 };
 708         };
 709
 710         vopl_mmu: iommu@ff940300 {
 711                 compatible = "rockchip,iommu";
 712                 reg = <0xff940300 0x100>;
 713                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 714                 interrupt-names = "vopl_mmu";
 715                 power-domains = <&power RK3288_PD_VIO>;
 716                 #iommu-cells = <0>;
 717                 status = "disabled";
 718         };
 719
 720         edp: edp@ff970000 {
 721                 compatible = "rockchip,rk3288-edp";
 722                 reg = <0xff970000 0x4000>;
 723                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 724                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
 725                 rockchip,grf = <&grf>;
 726                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 727                 resets = <&cru 111>;
 728                 reset-names = "edp";
 729                 power-domains = <&power RK3288_PD_VIO>;
 730                 status = "disabled";
 731                 ports {
 732                         edp_in: port {
 733                                 #address-cells = <1>;
 734                                 #size-cells = <0>;
 735                                 edp_in_vopb: endpoint@0 {
 736                                         reg = <0>;
 737                                         remote-endpoint = <&vopb_out_edp>;
 738                                 };
 739                                 edp_in_vopl: endpoint@1 {
 740                                         reg = <1>;
 741                                         remote-endpoint = <&vopl_out_edp>;
 742                                 };
 743                         };
 744                 };
 745         };
 746
 747         hdmi: hdmi@ff980000 {
 748                 compatible = "rockchip,rk3288-dw-hdmi";
 749                 reg = <0xff980000 0x20000>;
 750                 reg-io-width = <4>;
 751                 ddc-i2c-bus = <&i2c5>;
 752                 rockchip,grf = <&grf>;
 753                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 754                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 755                 clock-names = "iahb", "isfr";
 756                 status = "disabled";
 757                 ports {
 758                         hdmi_in: port {
 759                                 #address-cells = <1>;
 760                                 #size-cells = <0>;
 761                                 hdmi_in_vopb: endpoint@0 {
 762                                         reg = <0>;
 763                                         remote-endpoint = <&vopb_out_hdmi>;
 764                                 };
 765                                 hdmi_in_vopl: endpoint@1 {
 766                                         reg = <1>;
 767                                         remote-endpoint = <&vopl_out_hdmi>;
 768                                 };
 769                         };
 770                 };
 771         };
 772
 773         hdmi_audio: hdmi_audio {
 774                 compatible = "rockchip,rk3288-hdmi-audio";
 775                 i2s-controller = <&i2s>;
 776                 status = "disable";
 777         };
 778
 779         vpu: video-codec@ff9a0000 {
 780                 compatible = "rockchip,rk3288-vpu";
 781                 reg = <0xff9a0000 0x800>;
 782                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 783                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 784                 interrupt-names = "vepu", "vdpu";
 785                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 786                 clock-names = "aclk_vcodec", "hclk_vcodec";
 787                 power-domains = <&power RK3288_PD_VIDEO>;
 788                 iommus = <&vpu_mmu>;
 789         };
 790
 791         vpu_mmu: iommu@ff9a0800 {
 792                 compatible = "rockchip,iommu";
 793                 reg = <0xff9a0800 0x100>;
 794                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 795                 interrupt-names = "vpu_mmu";
 796                 power-domains = <&power RK3288_PD_VIDEO>;
 797                 #iommu-cells = <0>;
 798         };
 799
 800         gpu: gpu@ffa30000 {
 801                 compatible = "arm,malit764",
 802                              "arm,malit76x",
 803                              "arm,malit7xx",
 804                              "arm,mali-midgard";
 805                 reg = <0xffa30000 0x10000>;
 806                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 807                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 808                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 809                 interrupt-names = "JOB", "MMU", "GPU";
 810                 clocks = <&cru ACLK_GPU>;
 811                 clock-names = "aclk_gpu";
 812                 operating-points = <
 813                         /* KHz uV */
 814                         100000 950000
 815                         200000 950000
 816                         300000 1000000
 817                         400000 1100000
 818                         /* 500000 1200000 - See crosbug.com/p/33857 */
 819                         600000 1250000
 820                 >;
 821                 power-domains = <&power RK3288_PD_GPU>;
 822                 status = "disabled";
 823         };
 824
 825         noc: syscon@ffac0000 {
 826                 u-boot,dm-pre-reloc;
 827                 compatible = "rockchip,rk3288-noc", "syscon";
 828                 reg = <0xffac0000 0x2000>;
 829         };
 830
 831         efuse: efuse@ffb40000 {
 832                 compatible = "rockchip,rk3288-efuse";
 833                 reg = <0xffb40000 0x10000>;
 834                 status = "disabled";
 835         };
 836
 837         gic: interrupt-controller@ffc01000 {
 838                 compatible = "arm,gic-400";
 839                 interrupt-controller;
 840                 #interrupt-cells = <3>;
 841                 #address-cells = <0>;
 842
 843                 reg = <0xffc01000 0x1000>,
 844                       <0xffc02000 0x1000>,
 845                       <0xffc04000 0x2000>,
 846                       <0xffc06000 0x2000>;
 847                 interrupts = <GIC_PPI 9 0xf04>;
 848         };
 849
 850         cpuidle: cpuidle {
 851                 compatible = "rockchip,rk3288-cpuidle";
 852         };
 853
 854         usbphy: phy {
 855                 compatible = "rockchip,rk3288-usb-phy";
 856                 rockchip,grf = <&grf>;
 857                 #address-cells = <1>;
 858                 #size-cells = <0>;
 859                 status = "disabled";
 860
 861                 usbphy0: usb-phy0 {
 862                         #phy-cells = <0>;
 863                         reg = <0x320>;
 864                         clocks = <&cru SCLK_OTGPHY0>;
 865                         clock-names = "phyclk";
 866                 };
 867
 868                 usbphy1: usb-phy1 {
 869                         #phy-cells = <0>;
 870                         reg = <0x334>;
 871                         clocks = <&cru SCLK_OTGPHY1>;
 872                         clock-names = "phyclk";
 873                 };
 874
 875                 usbphy2: usb-phy2 {
 876                         #phy-cells = <0>;
 877                         reg = <0x348>;
 878                         clocks = <&cru SCLK_OTGPHY2>;
 879                         clock-names = "phyclk";
 880                 };
 881         };
 882
 883         pinctrl: pinctrl {
 884                 compatible = "rockchip,rk3288-pinctrl";
 885                 rockchip,grf = <&grf>;
 886                 rockchip,pmu = <&pmu>;
 887                 #address-cells = <1>;
 888                 #size-cells = <1>;
 889                 ranges;
 890
 891                 gpio0: gpio0@ff750000 {
 892                         compatible = "rockchip,gpio-bank";
 893                         reg =   <0xff750000 0x100>;
 894                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 895                         clocks = <&cru PCLK_GPIO0>;
 896
 897                         gpio-controller;
 898                         #gpio-cells = <2>;
 899
 900                         interrupt-controller;
 901                         #interrupt-cells = <2>;
 902                 };
 903
 904                 gpio1: gpio1@ff780000 {
 905                         compatible = "rockchip,gpio-bank";
 906                         reg = <0xff780000 0x100>;
 907                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 908                         clocks = <&cru PCLK_GPIO1>;
 909
 910                         gpio-controller;
 911                         #gpio-cells = <2>;
 912
 913                         interrupt-controller;
 914                         #interrupt-cells = <2>;
 915                 };
 916
 917                 gpio2: gpio2@ff790000 {
 918                         compatible = "rockchip,gpio-bank";
 919                         reg = <0xff790000 0x100>;
 920                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 921                         clocks = <&cru PCLK_GPIO2>;
 922
 923                         gpio-controller;
 924                         #gpio-cells = <2>;
 925
 926                         interrupt-controller;
 927                         #interrupt-cells = <2>;
 928                 };
 929
 930                 gpio3: gpio3@ff7a0000 {
 931                         compatible = "rockchip,gpio-bank";
 932                         reg = <0xff7a0000 0x100>;
 933                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 934                         clocks = <&cru PCLK_GPIO3>;
 935
 936                         gpio-controller;
 937                         #gpio-cells = <2>;
 938
 939                         interrupt-controller;
 940                         #interrupt-cells = <2>;
 941                 };
 942
 943                 gpio4: gpio4@ff7b0000 {
 944                         compatible = "rockchip,gpio-bank";
 945                         reg = <0xff7b0000 0x100>;
 946                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 947                         clocks = <&cru PCLK_GPIO4>;
 948
 949                         gpio-controller;
 950                         #gpio-cells = <2>;
 951
 952                         interrupt-controller;
 953                         #interrupt-cells = <2>;
 954                 };
 955
 956                 gpio5: gpio5@ff7c0000 {
 957                         compatible = "rockchip,gpio-bank";
 958                         reg = <0xff7c0000 0x100>;
 959                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 960                         clocks = <&cru PCLK_GPIO5>;
 961
 962                         gpio-controller;
 963                         #gpio-cells = <2>;
 964
 965                         interrupt-controller;
 966                         #interrupt-cells = <2>;
 967                 };
 968
 969                 gpio6: gpio6@ff7d0000 {
 970                         compatible = "rockchip,gpio-bank";
 971                         reg = <0xff7d0000 0x100>;
 972                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 973                         clocks = <&cru PCLK_GPIO6>;
 974
 975                         gpio-controller;
 976                         #gpio-cells = <2>;
 977
 978                         interrupt-controller;
 979                         #interrupt-cells = <2>;
 980                 };
 981
 982                 gpio7: gpio7@ff7e0000 {
 983                         compatible = "rockchip,gpio-bank";
 984                         reg = <0xff7e0000 0x100>;
 985                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 986                         clocks = <&cru PCLK_GPIO7>;
 987
 988                         gpio-controller;
 989                         #gpio-cells = <2>;
 990
 991                         interrupt-controller;
 992                         #interrupt-cells = <2>;
 993                 };
 994
 995                 gpio8: gpio8@ff7f0000 {
 996                         compatible = "rockchip,gpio-bank";
 997                         reg = <0xff7f0000 0x100>;
 998                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 999                         clocks = <&cru PCLK_GPIO8>;
1000
1001                         gpio-controller;
1002                         #gpio-cells = <2>;
1003
1004                         interrupt-controller;
1005                         #interrupt-cells = <2>;
1006                 };
1007
1008                 pcfg_pull_up: pcfg-pull-up {
1009                         bias-pull-up;
1010                 };
1011
1012                 pcfg_pull_down: pcfg-pull-down {
1013                         bias-pull-down;
1014                 };
1015
1016                 pcfg_pull_none: pcfg-pull-none {
1017                         bias-disable;
1018                 };
1019
1020                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1021                         bias-disable;
1022                         drive-strength = <12>;
1023                 };
1024
1025                 sleep {
1026                         global_pwroff: global-pwroff {
1027                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1028                         };
1029
1030                         ddrio_pwroff: ddrio-pwroff {
1031                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1032                         };
1033
1034                         ddr0_retention: ddr0-retention {
1035                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1036                         };
1037
1038                         ddr1_retention: ddr1-retention {
1039                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1040                         };
1041                 };
1042
1043                 i2c0 {
1044                         i2c0_xfer: i2c0-xfer {
1045                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1046                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1047                         };
1048                 };
1049
1050                 i2c1 {
1051                         i2c1_xfer: i2c1-xfer {
1052                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1053                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1054                         };
1055                 };
1056
1057                 i2c2 {
1058                         i2c2_xfer: i2c2-xfer {
1059                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1060                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1061                         };
1062                 };
1063
1064                 i2c3 {
1065                         i2c3_xfer: i2c3-xfer {
1066                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1067                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1068                         };
1069                 };
1070
1071                 i2c4 {
1072                         i2c4_xfer: i2c4-xfer {
1073                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1074                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076                 };
1077
1078                 i2c5 {
1079                         i2c5_xfer: i2c5-xfer {
1080                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1081                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1082                         };
1083                 };
1084
1085                 i2s0 {
1086                         i2s0_bus: i2s0-bus {
1087                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1088                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1089                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1090                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1091                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1092                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 sdmmc {
1097                         sdmmc_clk: sdmmc-clk {
1098                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1099                         };
1100
1101                         sdmmc_cmd: sdmmc-cmd {
1102                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1103                         };
1104
1105                         sdmmc_cd: sdmcc-cd {
1106                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1107                         };
1108
1109                         sdmmc_bus1: sdmmc-bus1 {
1110                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1111                         };
1112
1113                         sdmmc_bus4: sdmmc-bus4 {
1114                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1115                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1116                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1117                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1118                         };
1119                 };
1120
1121                 sdio0 {
1122                         sdio0_bus1: sdio0-bus1 {
1123                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1124                         };
1125
1126                         sdio0_bus4: sdio0-bus4 {
1127                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1128                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1129                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1130                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1131                         };
1132
1133                         sdio0_cmd: sdio0-cmd {
1134                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1135                         };
1136
1137                         sdio0_clk: sdio0-clk {
1138                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1139                         };
1140
1141                         sdio0_cd: sdio0-cd {
1142                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1143                         };
1144
1145                         sdio0_wp: sdio0-wp {
1146                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1147                         };
1148
1149                         sdio0_pwr: sdio0-pwr {
1150                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1151                         };
1152
1153                         sdio0_bkpwr: sdio0-bkpwr {
1154                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1155                         };
1156
1157                         sdio0_int: sdio0-int {
1158                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1159                         };
1160                 };
1161
1162                 sdio1 {
1163                         sdio1_bus1: sdio1-bus1 {
1164                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1165                         };
1166
1167                         sdio1_bus4: sdio1-bus4 {
1168                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1169                                                 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1170                                                 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1171                                                 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1172                         };
1173
1174                         sdio1_cd: sdio1-cd {
1175                                 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1176                         };
1177
1178                         sdio1_wp: sdio1-wp {
1179                                 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1180                         };
1181
1182                         sdio1_bkpwr: sdio1-bkpwr {
1183                                 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1184                         };
1185
1186                         sdio1_int: sdio1-int {
1187                                 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1188                         };
1189
1190                         sdio1_cmd: sdio1-cmd {
1191                                 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1192                         };
1193
1194                         sdio1_clk: sdio1-clk {
1195                                 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1196                         };
1197
1198                         sdio1_pwr: sdio1-pwr {
1199                                 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1200                         };
1201                 };
1202
1203                 emmc {
1204                         emmc_clk: emmc-clk {
1205                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1206                         };
1207
1208                         emmc_cmd: emmc-cmd {
1209                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1210                         };
1211
1212                         emmc_pwr: emmc-pwr {
1213                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1214                         };
1215
1216                         emmc_bus1: emmc-bus1 {
1217                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1218                         };
1219
1220                         emmc_bus4: emmc-bus4 {
1221                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1222                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1223                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1224                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1225                         };
1226
1227                         emmc_bus8: emmc-bus8 {
1228                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1229                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1230                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1231                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1232                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1233                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1234                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1235                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1236                         };
1237                 };
1238
1239                 spi0 {
1240                         spi0_clk: spi0-clk {
1241                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1242                         };
1243                         spi0_cs0: spi0-cs0 {
1244                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1245                         };
1246                         spi0_tx: spi0-tx {
1247                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1248                         };
1249                         spi0_rx: spi0-rx {
1250                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1251                         };
1252                         spi0_cs1: spi0-cs1 {
1253                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1254                         };
1255                 };
1256                 spi1 {
1257                         spi1_clk: spi1-clk {
1258                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1259                         };
1260                         spi1_cs0: spi1-cs0 {
1261                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1262                         };
1263                         spi1_rx: spi1-rx {
1264                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1265                         };
1266                         spi1_tx: spi1-tx {
1267                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1268                         };
1269                 };
1270
1271                 spi2 {
1272                         spi2_cs1: spi2-cs1 {
1273                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1274                         };
1275                         spi2_clk: spi2-clk {
1276                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1277                         };
1278                         spi2_cs0: spi2-cs0 {
1279                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1280                         };
1281                         spi2_rx: spi2-rx {
1282                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1283                         };
1284                         spi2_tx: spi2-tx {
1285                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1286                         };
1287                 };
1288
1289                 uart0 {
1290                         uart0_xfer: uart0-xfer {
1291                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1292                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1293                         };
1294
1295                         uart0_cts: uart0-cts {
1296                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1297                         };
1298
1299                         uart0_rts: uart0-rts {
1300                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1301                         };
1302                 };
1303
1304                 uart1 {
1305                         uart1_xfer: uart1-xfer {
1306                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1307                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1308                         };
1309
1310                         uart1_cts: uart1-cts {
1311                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1312                         };
1313
1314                         uart1_rts: uart1-rts {
1315                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1316                         };
1317                 };
1318
1319                 uart2 {
1320                         uart2_xfer: uart2-xfer {
1321                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1322                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1323                         };
1324                         /* no rts / cts for uart2 */
1325                 };
1326
1327                 uart3 {
1328                         uart3_xfer: uart3-xfer {
1329                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1330                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1331                         };
1332
1333                         uart3_cts: uart3-cts {
1334                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1335                         };
1336
1337                         uart3_rts: uart3-rts {
1338                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1339                         };
1340                 };
1341
1342                 uart4 {
1343                         uart4_xfer: uart4-xfer {
1344                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1345                                                 <5 13 3 &pcfg_pull_none>;
1346                         };
1347
1348                         uart4_cts: uart4-cts {
1349                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1350                         };
1351
1352                         uart4_rts: uart4-rts {
1353                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1354                         };
1355                 };
1356
1357                 tsadc {
1358                         otp_out: otp-out {
1359                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1360                         };
1361                 };
1362
1363                 pwm0 {
1364                         pwm0_pin: pwm0-pin {
1365                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1366                         };
1367                 };
1368
1369                 pwm1 {
1370                         pwm1_pin: pwm1-pin {
1371                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1372                         };
1373                 };
1374
1375                 pwm2 {
1376                         pwm2_pin: pwm2-pin {
1377                                 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1378                         };
1379                 };
1380
1381                 pwm3 {
1382                         pwm3_pin: pwm3-pin {
1383                                 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1384                         };
1385                 };
1386
1387                 gmac {
1388                         rgmii_pins: rgmii-pins {
1389                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1390                                                 <3 31 3 &pcfg_pull_none>,
1391                                                 <3 26 3 &pcfg_pull_none>,
1392                                                 <3 27 3 &pcfg_pull_none>,
1393                                                 <3 28 3 &pcfg_pull_none_12ma>,
1394                                                 <3 29 3 &pcfg_pull_none_12ma>,
1395                                                 <3 24 3 &pcfg_pull_none_12ma>,
1396                                                 <3 25 3 &pcfg_pull_none_12ma>,
1397                                                 <4 0 3 &pcfg_pull_none>,
1398                                                 <4 5 3 &pcfg_pull_none>,
1399                                                 <4 6 3 &pcfg_pull_none>,
1400                                                 <4 9 3 &pcfg_pull_none_12ma>,
1401                                                 <4 4 3 &pcfg_pull_none_12ma>,
1402                                                 <4 1 3 &pcfg_pull_none>,
1403                                                 <4 3 3 &pcfg_pull_none>;
1404                         };
1405
1406                         rmii_pins: rmii-pins {
1407                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1408                                                 <3 31 3 &pcfg_pull_none>,
1409                                                 <3 28 3 &pcfg_pull_none>,
1410                                                 <3 29 3 &pcfg_pull_none>,
1411                                                 <4 0 3 &pcfg_pull_none>,
1412                                                 <4 5 3 &pcfg_pull_none>,
1413                                                 <4 4 3 &pcfg_pull_none>,
1414                                                 <4 1 3 &pcfg_pull_none>,
1415                                                 <4 2 3 &pcfg_pull_none>,
1416                                                 <4 3 3 &pcfg_pull_none>;
1417                         };
1418                 };
1419         };
1420
1421         power: power-controller {
1422                 compatible = "rockchip,rk3288-power-controller";
1423                 #power-domain-cells = <1>;
1424                 rockchip,pmu = <&pmu>;
1425                 #address-cells = <1>;
1426                 #size-cells = <0>;
1427
1428                 pd_gpu {
1429                         reg = <RK3288_PD_GPU>;
1430                         clocks = <&cru ACLK_GPU>;
1431                 };
1432
1433                 pd_hevc {
1434                         reg = <RK3288_PD_HEVC>;
1435                         clocks = <&cru ACLK_HEVC>,
1436                                  <&cru SCLK_HEVC_CABAC>,
1437                                  <&cru SCLK_HEVC_CORE>,
1438                                  <&cru HCLK_HEVC>;
1439                 };
1440
1441                 pd_vio {
1442                         reg = <RK3288_PD_VIO>;
1443                         clocks = <&cru ACLK_IEP>,
1444                                  <&cru ACLK_ISP>,
1445                                  <&cru ACLK_RGA>,
1446                                  <&cru ACLK_VIP>,
1447                                  <&cru ACLK_VOP0>,
1448                                  <&cru ACLK_VOP1>,
1449                                  <&cru DCLK_VOP0>,
1450                                  <&cru DCLK_VOP1>,
1451                                  <&cru HCLK_IEP>,
1452                                  <&cru HCLK_ISP>,
1453                                  <&cru HCLK_RGA>,
1454                                  <&cru HCLK_VIP>,
1455                                  <&cru HCLK_VOP0>,
1456                                  <&cru HCLK_VOP1>,
1457                                  <&cru PCLK_EDP_CTRL>,
1458                                  <&cru PCLK_HDMI_CTRL>,
1459                                  <&cru PCLK_LVDS_PHY>,
1460                                  <&cru PCLK_MIPI_CSI>,
1461                                  <&cru PCLK_MIPI_DSI0>,
1462                                  <&cru PCLK_MIPI_DSI1>,
1463                                  <&cru SCLK_EDP_24M>,
1464                                  <&cru SCLK_EDP>,
1465                                  <&cru SCLK_HDMI_CEC>,
1466                                  <&cru SCLK_HDMI_HDCP>,
1467                                  <&cru SCLK_ISP_JPE>,
1468                                  <&cru SCLK_ISP>,
1469                                  <&cru SCLK_RGA>;
1470                 };
1471
1472                 pd_video {
1473                         reg = <RK3288_PD_VIDEO>;
1474                         clocks = <&cru ACLK_VCODEC>,
1475                                  <&cru HCLK_VCODEC>;
1476                 };
1477         };
1478 };