arch/arm/dts/rz-g2-beacon-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
   4  */
   5
   6 / {
   7         aliases {
   8                 spi0 = &rpc;
   9         };
  10
  11         soc {
  12                 bootph-all;
  13         };
  14 };
  15
  16 &cpg {
  17         bootph-all;
  18 };
  19
  20 &ehci0 {
  21         clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
  22 };
  23
  24 &ehci1 {
  25         clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
  26 };
  27
  28 &extal_clk {
  29         bootph-all;
  30 };
  31
  32 &extalr_clk {
  33         bootph-all;
  34 };
  35
  36 &pfc {
  37         qspi_pins: qspi {
  38                 groups = "qspi_ctrl", "qspi_data4";
  39                 function = "qspi";
  40         };
  41 };
  42
  43 &prr {
  44         bootph-all;
  45 };
  46
  47 &rpc {
  48         pinctrl-0 = <&qspi_pins>;
  49         pinctrl-names = "default";
  50         num-cs = <1>;
  51         spi-max-frequency = <40000000>;
  52         #address-cells = <1>;
  53         #size-cells = <0>;
  54         status = "okay";
  55
  56         flash0: spi-flash@0 {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 reg = <0>;
  60                 compatible = "spi-flash", "jedec,spi-nor";
  61                 spi-max-frequency = <40000000>;
  62                 spi-tx-bus-width = <1>;
  63                 spi-rx-bus-width = <1>;
  64         };
  65 };
  66
  67 &sdhi0 {
  68         /delete-property/ cd-gpios;
  69         sd-uhs-sdr12;
  70         sd-uhs-sdr25;
  71         sd-uhs-sdr104;
  72         max-frequency = <208000000>;
  73 };
  74
  75 &sdhi2 {
  76         status = "disabled";
  77 };
  78
  79 &sdhi3 {
  80         mmc-ddr-1_8v;
  81         mmc-hs200-1_8v;
  82         mmc-hs400-1_8v;
  83 };