]> git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/dts/socfpga_arria10.dtsi
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
arm: dts: Add dts and dtsi for Arria 10
[people/ms/u-boot.git] / arch / arm / dts / socfpga_arria10.dtsi
1 /*
2 * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include "skeleton.dtsi"
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
20
21 / {
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 ethernet0 = &gmac0;
27 ethernet1 = &gmac1;
28 ethernet2 = &gmac2;
29 serial0 = &uart0;
30 serial1 = &uart1;
31 timer0 = &timer0;
32 timer1 = &timer1;
33 timer2 = &timer2;
34 timer3 = &timer3;
35 spi0 = &spi0;
36 spi1 = &spi1;
37 };
38
39 memory {
40 name = "memory";
41 device_type = "memory";
42 reg = <0x0 0x40000000>; /* 1GB */
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu@0 {
50 compatible = "arm,cortex-a9";
51 device_type = "cpu";
52 reg = <0>;
53 next-level-cache = <&L2>;
54 };
55 cpu@1 {
56 compatible = "arm,cortex-a9";
57 device_type = "cpu";
58 reg = <1>;
59 next-level-cache = <&L2>;
60 };
61 };
62
63 intc: intc@ffffd000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
66 interrupt-controller;
67 reg = <0xffffd000 0x1000>,
68 <0xffffc100 0x100>;
69 };
70
71 soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "simple-bus";
75 device_type = "soc";
76 interrupt-parent = <&intc>;
77 ranges;
78
79 amba {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84
85 pdma: pdma@ffda1000 {
86 compatible = "arm,pl330", "arm,primecell";
87 reg = <0xffda1000 0x1000>;
88 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
89 <0 84 IRQ_TYPE_LEVEL_HIGH>,
90 <0 85 IRQ_TYPE_LEVEL_HIGH>,
91 <0 86 IRQ_TYPE_LEVEL_HIGH>,
92 <0 87 IRQ_TYPE_LEVEL_HIGH>,
93 <0 88 IRQ_TYPE_LEVEL_HIGH>,
94 <0 89 IRQ_TYPE_LEVEL_HIGH>,
95 <0 90 IRQ_TYPE_LEVEL_HIGH>,
96 <0 91 IRQ_TYPE_LEVEL_HIGH>;
97 #dma-cells = <1>;
98 #dma-channels = <8>;
99 #dma-requests = <32>;
100 clocks = <&l4_main_clk>;
101 clock-names = "apb_pclk";
102 };
103 };
104
105 clkmgr@ffd04000 {
106 compatible = "altr,clk-mgr";
107 reg = <0xffd04000 0x1000>;
108 reg-names = "soc_clock_manager_OCP_SLV";
109
110 clocks {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
117 };
118
119 cb_intosc_ls_clk: cb_intosc_ls_clk {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
122 };
123
124 f2s_free_clk: f2s_free_clk {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 };
128
129 osc1: osc1 {
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 };
133
134 main_pll: main_pll {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 #clock-cells = <0>;
138 compatible = "altr,socfpga-a10-pll-clock";
139 clocks = <&osc1>, <&cb_intosc_ls_clk>,
140 <&f2s_free_clk>;
141 reg = <0x40>;
142
143 main_mpu_base_clk: main_mpu_base_clk {
144 #clock-cells = <0>;
145 compatible = "altr,socfpga-a10-perip-clk";
146 clocks = <&main_pll>;
147 div-reg = <0x140 0 11>;
148 };
149
150 main_noc_base_clk: main_noc_base_clk {
151 #clock-cells = <0>;
152 compatible = "altr,socfpga-a10-perip-clk";
153 clocks = <&main_pll>;
154 div-reg = <0x144 0 11>;
155 };
156
157 main_emaca_clk: main_emaca_clk {
158 #clock-cells = <0>;
159 compatible = "altr,socfpga-a10-perip-clk";
160 clocks = <&main_pll>;
161 reg = <0x68>;
162 };
163
164 main_emacb_clk: main_emacb_clk {
165 #clock-cells = <0>;
166 compatible = "altr,socfpga-a10-perip-clk";
167 clocks = <&main_pll>;
168 reg = <0x6C>;
169 };
170
171 main_emac_ptp_clk: main_emac_ptp_clk {
172 #clock-cells = <0>;
173 compatible = "altr,socfpga-a10-perip-clk";
174 clocks = <&main_pll>;
175 reg = <0x70>;
176 };
177
178 main_gpio_db_clk: main_gpio_db_clk {
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-a10-perip-clk";
181 clocks = <&main_pll>;
182 reg = <0x74>;
183 };
184
185 main_sdmmc_clk: main_sdmmc_clk {
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-a10-perip-clk";
188 clocks = <&main_pll>;
189 reg = <0x78>;
190 };
191
192 main_s2f_usr0_clk: main_s2f_usr0_clk {
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-a10-perip-clk";
195 clocks = <&main_pll>;
196 reg = <0x7C>;
197 };
198
199 main_s2f_usr1_clk: main_s2f_usr1_clk {
200 #clock-cells = <0>;
201 compatible = "altr,socfpga-a10-perip-clk";
202 clocks = <&main_pll>;
203 reg = <0x80>;
204 };
205
206 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
207 #clock-cells = <0>;
208 compatible = "altr,socfpga-a10-perip-clk";
209 clocks = <&main_pll>;
210 reg = <0x84>;
211 };
212
213 main_periph_ref_clk: main_periph_ref_clk {
214 #clock-cells = <0>;
215 compatible = "altr,socfpga-a10-perip-clk";
216 clocks = <&main_pll>;
217 reg = <0x9C>;
218 };
219 };
220
221 periph_pll: periph_pll {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 #clock-cells = <0>;
225 compatible = "altr,socfpga-a10-pll-clock";
226 clocks = <&osc1>, <&cb_intosc_ls_clk>,
227 <&f2s_free_clk>, <&main_periph_ref_clk>;
228 reg = <0xC0>;
229
230 peri_mpu_base_clk: peri_mpu_base_clk {
231 #clock-cells = <0>;
232 compatible = "altr,socfpga-a10-perip-clk";
233 clocks = <&periph_pll>;
234 div-reg = <0x140 16 11>;
235 };
236
237 peri_noc_base_clk: peri_noc_base_clk {
238 #clock-cells = <0>;
239 compatible = "altr,socfpga-a10-perip-clk";
240 clocks = <&periph_pll>;
241 div-reg = <0x144 16 11>;
242 };
243
244 peri_emaca_clk: peri_emaca_clk {
245 #clock-cells = <0>;
246 compatible = "altr,socfpga-a10-perip-clk";
247 clocks = <&periph_pll>;
248 reg = <0xE8>;
249 };
250
251 peri_emacb_clk: peri_emacb_clk {
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-a10-perip-clk";
254 clocks = <&periph_pll>;
255 reg = <0xEC>;
256 };
257
258 peri_emac_ptp_clk: peri_emac_ptp_clk {
259 #clock-cells = <0>;
260 compatible = "altr,socfpga-a10-perip-clk";
261 clocks = <&periph_pll>;
262 reg = <0xF0>;
263 };
264
265 peri_gpio_db_clk: peri_gpio_db_clk {
266 #clock-cells = <0>;
267 compatible = "altr,socfpga-a10-perip-clk";
268 clocks = <&periph_pll>;
269 reg = <0xF4>;
270 };
271
272 peri_sdmmc_clk: peri_sdmmc_clk {
273 #clock-cells = <0>;
274 compatible = "altr,socfpga-a10-perip-clk";
275 clocks = <&periph_pll>;
276 reg = <0xF8>;
277 };
278
279 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
280 #clock-cells = <0>;
281 compatible = "altr,socfpga-a10-perip-clk";
282 clocks = <&periph_pll>;
283 reg = <0xFC>;
284 };
285
286 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
287 #clock-cells = <0>;
288 compatible = "altr,socfpga-a10-perip-clk";
289 clocks = <&periph_pll>;
290 reg = <0x100>;
291 };
292
293 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
294 #clock-cells = <0>;
295 compatible = "altr,socfpga-a10-perip-clk";
296 clocks = <&periph_pll>;
297 reg = <0x104>;
298 };
299 };
300
301 mpu_free_clk: mpu_free_clk {
302 #clock-cells = <0>;
303 compatible = "altr,socfpga-a10-perip-clk";
304 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
305 <&osc1>, <&cb_intosc_hs_div2_clk>,
306 <&f2s_free_clk>;
307 reg = <0x60>;
308 };
309
310 noc_free_clk: noc_free_clk {
311 #clock-cells = <0>;
312 compatible = "altr,socfpga-a10-perip-clk";
313 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
314 <&osc1>, <&cb_intosc_hs_div2_clk>,
315 <&f2s_free_clk>;
316 reg = <0x64>;
317 };
318
319 s2f_user1_free_clk: s2f_user1_free_clk {
320 #clock-cells = <0>;
321 compatible = "altr,socfpga-a10-perip-clk";
322 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
323 <&osc1>, <&cb_intosc_hs_div2_clk>,
324 <&f2s_free_clk>;
325 reg = <0x104>;
326 };
327
328 sdmmc_free_clk: sdmmc_free_clk {
329 #clock-cells = <0>;
330 compatible = "altr,socfpga-a10-perip-clk";
331 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
332 <&osc1>, <&cb_intosc_hs_div2_clk>,
333 <&f2s_free_clk>;
334 fixed-divider = <4>;
335 reg = <0xF8>;
336 };
337
338 l4_sys_free_clk: l4_sys_free_clk {
339 #clock-cells = <0>;
340 compatible = "altr,socfpga-a10-perip-clk";
341 clocks = <&noc_free_clk>;
342 fixed-divider = <4>;
343 };
344
345 l4_main_clk: l4_main_clk {
346 #clock-cells = <0>;
347 compatible = "altr,socfpga-a10-gate-clk";
348 clocks = <&noc_free_clk>;
349 div-reg = <0xA8 0 2>;
350 clk-gate = <0x48 1>;
351 };
352
353 l4_mp_clk: l4_mp_clk {
354 #clock-cells = <0>;
355 compatible = "altr,socfpga-a10-gate-clk";
356 clocks = <&noc_free_clk>;
357 div-reg = <0xA8 8 2>;
358 clk-gate = <0x48 2>;
359 };
360
361 l4_sp_clk: l4_sp_clk {
362 #clock-cells = <0>;
363 compatible = "altr,socfpga-a10-gate-clk";
364 clocks = <&noc_free_clk>;
365 div-reg = <0xA8 16 2>;
366 clk-gate = <0x48 3>;
367 };
368
369 mpu_periph_clk: mpu_periph_clk {
370 #clock-cells = <0>;
371 compatible = "altr,socfpga-a10-gate-clk";
372 clocks = <&mpu_free_clk>;
373 fixed-divider = <4>;
374 clk-gate = <0x48 0>;
375 };
376
377 sdmmc_clk: sdmmc_clk {
378 #clock-cells = <0>;
379 compatible = "altr,socfpga-a10-gate-clk";
380 clocks = <&sdmmc_free_clk>;
381 clk-gate = <0xC8 5>;
382 clk-phase = <0 135>;
383 };
384
385 qspi_clk: qspi_clk {
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-a10-gate-clk";
388 clocks = <&l4_main_clk>;
389 clk-gate = <0xC8 11>;
390 };
391
392 nand_clk: nand_clk {
393 #clock-cells = <0>;
394 compatible = "altr,socfpga-a10-gate-clk";
395 clocks = <&l4_mp_clk>;
396 clk-gate = <0xC8 10>;
397 };
398
399 spi_m_clk: spi_m_clk {
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-a10-gate-clk";
402 clocks = <&l4_main_clk>;
403 clk-gate = <0xC8 9>;
404 };
405
406 usb_clk: usb_clk {
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-a10-gate-clk";
409 clocks = <&l4_mp_clk>;
410 clk-gate = <0xC8 8>;
411 };
412
413 s2f_usr1_clk: s2f_usr1_clk {
414 #clock-cells = <0>;
415 compatible = "altr,socfpga-a10-gate-clk";
416 clocks = <&peri_s2f_usr1_clk>;
417 clk-gate = <0xC8 6>;
418 };
419 };
420 };
421
422 gmac0: ethernet@ff800000 {
423 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
425 reg = <0xff800000 0x2000>;
426 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "macirq";
428 /* Filled in by bootloader */
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
434 clocks = <&l4_mp_clk>;
435 clock-names = "stmmaceth";
436 resets = <&rst EMAC0_RESET>;
437 reset-names = "stmmaceth";
438 status = "disabled";
439 };
440
441 gmac1: ethernet@ff802000 {
442 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
443 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
444 reg = <0xff802000 0x2000>;
445 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "macirq";
447 /* Filled in by bootloader */
448 mac-address = [00 00 00 00 00 00];
449 snps,multicast-filter-bins = <256>;
450 snps,perfect-filter-entries = <128>;
451 tx-fifo-depth = <4096>;
452 rx-fifo-depth = <16384>;
453 clocks = <&l4_mp_clk>;
454 clock-names = "stmmaceth";
455 resets = <&rst EMAC1_RESET>;
456 reset-names = "stmmaceth";
457 status = "disabled";
458 };
459
460 gmac2: ethernet@ff804000 {
461 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
462 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
463 reg = <0xff804000 0x2000>;
464 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "macirq";
466 /* Filled in by bootloader */
467 mac-address = [00 00 00 00 00 00];
468 snps,multicast-filter-bins = <256>;
469 snps,perfect-filter-entries = <128>;
470 tx-fifo-depth = <4096>;
471 rx-fifo-depth = <16384>;
472 clocks = <&l4_mp_clk>;
473 clock-names = "stmmaceth";
474 status = "disabled";
475 };
476
477 gpio0: gpio@ffc02900 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 compatible = "snps,dw-apb-gpio";
481 reg = <0xffc02900 0x100>;
482 status = "disabled";
483
484 porta: gpio-controller@0 {
485 compatible = "snps,dw-apb-gpio-port";
486 gpio-controller;
487 #gpio-cells = <2>;
488 snps,nr-gpios = <29>;
489 reg = <0>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
493 };
494 };
495
496 gpio1: gpio@ffc02a00 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "snps,dw-apb-gpio";
500 reg = <0xffc02a00 0x100>;
501 status = "disabled";
502
503 portb: gpio-controller@0 {
504 compatible = "snps,dw-apb-gpio-port";
505 gpio-controller;
506 #gpio-cells = <2>;
507 snps,nr-gpios = <29>;
508 reg = <0>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
512 };
513 };
514
515 gpio2: gpio@ffc02b00 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "snps,dw-apb-gpio";
519 reg = <0xffc02b00 0x100>;
520 status = "disabled";
521
522 portc: gpio-controller@0 {
523 compatible = "snps,dw-apb-gpio-port";
524 gpio-controller;
525 #gpio-cells = <2>;
526 snps,nr-gpios = <27>;
527 reg = <0>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
531 };
532 };
533
534 fpga_mgr: fpga-mgr@ffd03000 {
535 compatible = "altr,socfpga-a10-fpga-mgr";
536 reg = <0xffd03000 0x100
537 0xffcfe400 0x20>;
538 clocks = <&l4_mp_clk>;
539 resets = <&rst FPGAMGR_RESET>;
540 reset-names = "fpgamgr";
541 };
542
543 i2c0: i2c@ffc02200 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "snps,designware-i2c";
547 reg = <0xffc02200 0x100>;
548 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&l4_sp_clk>;
550 status = "disabled";
551 };
552
553 i2c1: i2c@ffc02300 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "snps,designware-i2c";
557 reg = <0xffc02300 0x100>;
558 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&l4_sp_clk>;
560 status = "disabled";
561 };
562
563 i2c2: i2c@ffc02400 {
564 #address-cells = <1>;
565 #size-cells = <0>;
566 compatible = "snps,designware-i2c";
567 reg = <0xffc02400 0x100>;
568 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&l4_sp_clk>;
570 status = "disabled";
571 };
572
573 i2c3: i2c@ffc02500 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "snps,designware-i2c";
577 reg = <0xffc02500 0x100>;
578 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&l4_sp_clk>;
580 status = "disabled";
581 };
582
583 i2c4: i2c@ffc02600 {
584 #address-cells = <1>;
585 #size-cells = <0>;
586 compatible = "snps,designware-i2c";
587 reg = <0xffc02600 0x100>;
588 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&l4_sp_clk>;
590 status = "disabled";
591 };
592
593 sdr: sdr@0xffcfb100 {
594 compatible = "syscon";
595 reg = <0xffcfb100 0x80>;
596 };
597
598 spi0: spi@ffda4000 {
599 compatible = "snps,dw-apb-ssi";
600 #address-cells = <1>;
601 #size-cells = <0>;
602 reg = <0xffda4000 0x100>;
603 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
604 num-chipselect = <4>;
605 bus-num = <0>;
606 tx-dma-channel = <&pdma 16>;
607 rx-dma-channel = <&pdma 17>;
608 clocks = <&spi_m_clk>;
609 status = "disabled";
610 };
611
612 spi1: spi@ffda5000 {
613 compatible = "snps,dw-apb-ssi";
614 #address-cells = <1>;
615 #size-cells = <0>;
616 reg = <0xffda5000 0x100>;
617 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
618 num-chipselect = <4>;
619 bus-num = <0>;
620 tx-dma-channel = <&pdma 20>;
621 rx-dma-channel = <&pdma 21>;
622 clocks = <&spi_m_clk>;
623 status = "disabled";
624 };
625
626 L2: l2-cache@fffff000 {
627 compatible = "arm,pl310-cache";
628 reg = <0xfffff000 0x1000>;
629 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
630 cache-unified;
631 cache-level = <2>;
632 };
633
634 mmc: dwmmc0@ff808000 {
635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "altr,socfpga-dw-mshc";
638 reg = <0xff808000 0x1000>;
639 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
640 fifo-depth = <0x400>;
641 bus-width = <4>;
642 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
643 clock-names = "biu", "ciu";
644 status = "disabled";
645 };
646
647 ocram: sram@ffe00000 {
648 compatible = "mmio-sram";
649 reg = <0xffe00000 0x40000>;
650 };
651
652 eccmgr: eccmgr@ffd06000 {
653 compatible = "altr,socfpga-a10-ecc-manager";
654 altr,sysmgr-syscon = <&sysmgr>;
655 #address-cells = <1>;
656 #size-cells = <1>;
657 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
658 <0 0 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-controller;
660 #interrupt-cells = <2>;
661 ranges;
662
663 sdramedac {
664 compatible = "altr,sdram-edac-a10";
665 altr,sdr-syscon = <&sdr>;
666 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
667 <49 IRQ_TYPE_LEVEL_HIGH>;
668 };
669
670 l2-ecc@ffd06010 {
671 compatible = "altr,socfpga-a10-l2-ecc";
672 reg = <0xffd06010 0x4>;
673 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
674 <32 IRQ_TYPE_LEVEL_HIGH>;
675 };
676
677 ocram-ecc@ff8c3000 {
678 compatible = "altr,socfpga-a10-ocram-ecc";
679 reg = <0xff8c3000 0x400>;
680 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
681 <33 IRQ_TYPE_LEVEL_HIGH>;
682 };
683
684 sdmmca-ecc@ff8c2c00 {
685 compatible = "altr,socfpga-sdmmc-ecc";
686 reg = <0xff8c2c00 0x400>;
687 altr,ecc-parent = <&mmc>;
688 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
689 <47 IRQ_TYPE_LEVEL_HIGH>,
690 <16 IRQ_TYPE_LEVEL_HIGH>,
691 <48 IRQ_TYPE_LEVEL_HIGH>;
692 };
693
694 emac0-rx-ecc@ff8c0800 {
695 compatible = "altr,socfpga-eth-mac-ecc";
696 reg = <0xff8c0800 0x400>;
697 altr,ecc-parent = <&gmac0>;
698 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
699 <36 IRQ_TYPE_LEVEL_HIGH>;
700 };
701
702 emac0-tx-ecc@ff8c0c00 {
703 compatible = "altr,socfpga-eth-mac-ecc";
704 reg = <0xff8c0c00 0x400>;
705 altr,ecc-parent = <&gmac0>;
706 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
707 <37 IRQ_TYPE_LEVEL_HIGH>;
708 };
709
710 dma-ecc@ff8c8000 {
711 compatible = "altr,socfpga-dma-ecc";
712 reg = <0xff8c8000 0x400>;
713 altr,ecc-parent = <&pdma>;
714 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
715 <42 IRQ_TYPE_LEVEL_HIGH>;
716 };
717
718 usb0-ecc@ff8c8800 {
719 compatible = "altr,socfpga-usb-ecc";
720 reg = <0xff8c8800 0x400>;
721 altr,ecc-parent = <&usb0>;
722 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
723 <34 IRQ_TYPE_LEVEL_HIGH>;
724 };
725 };
726
727 qspi: qspi@ff809000 {
728 #address-cells = <1>;
729 #size-cells = <0>;
730 compatible = "cadence,qspi";
731 reg = <0xff809000 0x100>,
732 <0xffa00000 0x100000>;
733 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&l4_main_clk>;
735 ext-decoder = <0>; /* external decoder */
736 num-chipselect = <4>;
737 fifo-depth = <128>;
738 sram-size = <512>;
739 bus-num = <2>;
740 status = "disabled";
741 };
742
743 rst: rstmgr@ffd05000 {
744 #reset-cells = <1>;
745 compatible = "altr,rst-mgr";
746 reg = <0xffd05000 0x100>;
747 altr,modrst-offset = <0x20>;
748 };
749
750 scu: snoop-control-unit@ffffc000 {
751 compatible = "arm,cortex-a9-scu";
752 reg = <0xffffc000 0x100>;
753 };
754
755 sysmgr: sysmgr@ffd06000 {
756 compatible = "altr,sys-mgr", "syscon";
757 reg = <0xffd06000 0x300>;
758 cpu1-start-addr = <0xffd06230>;
759 };
760
761 /* Local timer */
762 timer@ffffc600 {
763 compatible = "arm,cortex-a9-twd-timer";
764 reg = <0xffffc600 0x100>;
765 interrupts = <1 13 0xf04>;
766 clocks = <&mpu_periph_clk>;
767 };
768
769 timer0: timer0@ffc02700 {
770 compatible = "snps,dw-apb-timer";
771 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
772 reg = <0xffc02700 0x100>;
773 clocks = <&l4_sp_clk>;
774 clock-names = "timer";
775 };
776
777 timer1: timer1@ffc02800 {
778 compatible = "snps,dw-apb-timer";
779 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
780 reg = <0xffc02800 0x100>;
781 clocks = <&l4_sp_clk>;
782 clock-names = "timer";
783 };
784
785 timer2: timer2@ffd00000 {
786 compatible = "snps,dw-apb-timer";
787 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
788 reg = <0xffd00000 0x100>;
789 clocks = <&l4_sys_free_clk>;
790 clock-names = "timer";
791 };
792
793 timer3: timer3@ffd00100 {
794 compatible = "snps,dw-apb-timer";
795 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0xffd01000 0x100>;
797 clocks = <&l4_sys_free_clk>;
798 clock-names = "timer";
799 };
800
801 uart0: serial0@ffc02000 {
802 compatible = "snps,dw-apb-uart";
803 reg = <0xffc02000 0x100>;
804 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
805 reg-shift = <2>;
806 reg-io-width = <4>;
807 clocks = <&l4_sp_clk>;
808 status = "disabled";
809 };
810
811 uart1: serial1@ffc02100 {
812 compatible = "snps,dw-apb-uart";
813 reg = <0xffc02100 0x100>;
814 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
815 reg-shift = <2>;
816 reg-io-width = <4>;
817 clocks = <&l4_sp_clk>;
818 status = "disabled";
819 };
820
821 usbphy0: usbphy@0 {
822 #phy-cells = <0>;
823 compatible = "usb-nop-xceiv";
824 status = "okay";
825 };
826
827 usb0: usb@ffb00000 {
828 compatible = "snps,dwc2";
829 reg = <0xffb00000 0xffff>;
830 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&usb_clk>;
832 clock-names = "otg";
833 resets = <&rst USB0_RESET>;
834 reset-names = "dwc2";
835 phys = <&usbphy0>;
836 phy-names = "usb2-phy";
837 status = "disabled";
838 };
839
840 usb1: usb@ffb40000 {
841 compatible = "snps,dwc2";
842 reg = <0xffb40000 0xffff>;
843 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&usb_clk>;
845 clock-names = "otg";
846 resets = <&rst USB1_RESET>;
847 reset-names = "dwc2";
848 phys = <&usbphy0>;
849 phy-names = "usb2-phy";
850 status = "disabled";
851 };
852
853 watchdog0: watchdog@ffd00200 {
854 compatible = "snps,dw-wdt";
855 reg = <0xffd00200 0x100>;
856 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&l4_sys_free_clk>;
858 status = "disabled";
859 };
860
861 watchdog1: watchdog@ffd00300 {
862 compatible = "snps,dw-wdt";
863 reg = <0xffd00300 0x100>;
864 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&l4_sys_free_clk>;
866 status = "disabled";
867 };
868 };
869 };
"Das U-Boot" Source Tree