arch/arm/dts/socfpga_arria5_secu1.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016-2020 Hitachi Power Grids
   4  */
   5
   6 #include "socfpga_arria5.dtsi"
   7 #include "socfpga-common-u-boot.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         model = "Hitachi PG SoC SECU1 Board";
  12         compatible = "altr,socfpga-secu1", "altr,socfpga";
  13
  14         chosen {
  15                 stdout-path = "serial0:115200n8";
  16                 bootargs = "console=ttyS0,115200";
  17         };
  18
  19         memory {
  20                 name = "memory";
  21                 device_type = "memory";
  22                 reg = <0x0 0x20000000>; /* 512MB */
  23         };
  24
  25         aliases {
  26                 /*
  27                  * this allow the ethaddr uboot environment variable contents
  28                  * to be added to the gmac0 device tree blob.
  29                  */
  30                 ethernet0 = &gmac0;
  31                 spi0 = &spi1;
  32         };
  33
  34         bootcount@0 {
  35                 compatible = "u-boot,bootcount-rtc";
  36                 rtc = <&rtc>;
  37                 offset = <0x9e>;
  38         };
  39
  40         i2c_gpio: i2c@0 {
  41                 compatible = "i2c-gpio";
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44                 gpios = <&portc 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)    /* SDA */
  45                          &portc 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;  /* SCL */
  46                 i2c-gpio,delay-us = <5>;        /* ~100 kHz */
  47                 i2c-gpio,deblock;
  48
  49                 temp_sensor@48 {
  50                         compatible = "national,lm75";
  51                         reg = <0x48>;
  52                 };
  53
  54                 eeprom@50 {
  55                         compatible = "at,24c08";
  56                         reg = <0x50>;
  57                 };
  58
  59                 rtc: rtc@68 {
  60                         compatible = "st,m41st87";
  61                         reg = <0x68>;
  62                         interrupt-parent = <&intc>;
  63                         interrupts = <0 42 0x4>;
  64                 };
  65         };
  66
  67         regulator_3_3v: 3-3-v-regulator {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "3.3V";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72         };
  73 };
  74
  75 &gmac0 {
  76         status = "okay";
  77         phy-mode = "rgmii";
  78         fixed-link {
  79                 speed = <1000>;
  80                 full-duplex;
  81         };
  82 };
  83
  84 &gpio0 {
  85         status = "okay";
  86 };
  87
  88 &gpio1 {
  89         status = "okay";
  90 };
  91
  92 &gpio2 {
  93         status = "okay";
  94 };
  95
  96 &mmc0 {
  97         vmmc-supply = <&regulator_3_3v>;
  98         vqmmc-supply = <&regulator_3_3v>;
  99         bus-width = <4>;
 100         bootph-all;
 101 };
 102
 103 &nand0 {
 104         status = "okay";
 105 };
 106
 107 &porta {
 108         bank-name = "porta";
 109 };
 110
 111 &portb {
 112         bank-name = "portb";
 113 };
 114
 115 &portc {
 116         bank-name = "portc";
 117 };
 118
 119 &spi1 {
 120         status = "okay";
 121 };
 122
 123 &uart0 {
 124         clock-frequency = <100000000>;
 125         bootph-all;
 126         status = "okay";
 127 };
 128
 129 &uart1 {
 130         clock-frequency = <100000000>;
 131 };
 132
 133 &watchdog0 {
 134         bootph-all;
 135         status = "okay";
 136 };