arch/arm/dts/socfpga_cyclone5_de1_soc.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright Altera Corporation (C) 2015
   4  */
   5
   6 #include "socfpga_cyclone5.dtsi"
   7 #include "socfpga-common-u-boot.dtsi"
   8
   9 / {
  10         model = "Terasic DE1-SoC";
  11         compatible = "altr,socfpga-cyclone5", "altr,socfpga";
  12
  13         chosen {
  14                 bootargs = "console=ttyS0,115200";
  15                 stdout-path = "serial0:115200n8";
  16         };
  17
  18         aliases {
  19                 ethernet0 = &gmac1;
  20                 udc0 = &usb1;
  21         };
  22
  23         memory {
  24                 name = "memory";
  25                 device_type = "memory";
  26                 reg = <0x0 0x40000000>; /* 1GB */
  27         };
  28 };
  29
  30 &gmac1 {
  31         status = "okay";
  32         phy-mode = "rgmii";
  33
  34         rxd0-skew-ps = <420>;
  35         rxd1-skew-ps = <420>;
  36         rxd2-skew-ps = <420>;
  37         rxd3-skew-ps = <420>;
  38         txen-skew-ps = <0>;
  39         txc-skew-ps = <1860>;
  40         rxdv-skew-ps = <420>;
  41         rxc-skew-ps = <1680>;
  42 };
  43
  44 &gpio0 {
  45         status = "okay";
  46 };
  47
  48 &gpio1 {
  49         status = "okay";
  50 };
  51
  52 &gpio2 {
  53         status = "okay";
  54 };
  55
  56 &porta {
  57         bank-name = "porta";
  58 };
  59
  60 &portb {
  61         bank-name = "portb";
  62 };
  63
  64 &portc {
  65         bank-name = "portc";
  66 };
  67
  68 &mmc0 {
  69         status = "okay";
  70         bootph-all;
  71 };
  72
  73 &usb1 {
  74         status = "okay";
  75 };
  76
  77 &uart0 {
  78         clock-frequency = <100000000>;
  79         bootph-all;
  80 };
  81
  82 &watchdog0 {
  83         status = "disabled";
  84 };