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Merge git://git.denx.de/u-boot-imx
[people/ms/u-boot.git] / arch / arm / dts / sun8i-a23-a33.dtsi
1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48
49 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
50 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
51
52 / {
53 interrupt-parent = <&gic>;
54
55 chosen {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges;
59
60 simplefb_lcd: framebuffer@0 {
61 compatible = "allwinner,simple-framebuffer",
62 "simple-framebuffer";
63 allwinner,pipeline = "de_be0-lcd0";
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
67 status = "disabled";
68 };
69 };
70
71 timer {
72 compatible = "arm,armv7-timer";
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
77 clock-frequency = <24000000>;
78 arm,cpu-registers-not-fw-configured;
79 };
80
81 cpus {
82 enable-method = "allwinner,sun8i-a23";
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 cpu0: cpu@0 {
87 compatible = "arm,cortex-a7";
88 device_type = "cpu";
89 reg = <0>;
90 };
91
92 cpu@1 {
93 compatible = "arm,cortex-a7";
94 device_type = "cpu";
95 reg = <1>;
96 };
97 };
98
99 clocks {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 osc24M: osc24M_clk {
105 #clock-cells = <0>;
106 compatible = "fixed-clock";
107 clock-frequency = <24000000>;
108 clock-accuracy = <50000>;
109 clock-output-names = "osc24M";
110 };
111
112 ext_osc32k: ext_osc32k_clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <32768>;
116 clock-accuracy = <50000>;
117 clock-output-names = "ext-osc32k";
118 };
119 };
120
121 soc@01c00000 {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges;
126
127 dma: dma-controller@01c02000 {
128 compatible = "allwinner,sun8i-a23-dma";
129 reg = <0x01c02000 0x1000>;
130 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&ccu CLK_BUS_DMA>;
132 resets = <&ccu RST_BUS_DMA>;
133 #dma-cells = <1>;
134 };
135
136 mmc0: mmc@01c0f000 {
137 compatible = "allwinner,sun7i-a20-mmc";
138 reg = <0x01c0f000 0x1000>;
139 clocks = <&ccu CLK_BUS_MMC0>,
140 <&ccu CLK_MMC0>,
141 <&ccu CLK_MMC0_OUTPUT>,
142 <&ccu CLK_MMC0_SAMPLE>;
143 clock-names = "ahb",
144 "mmc",
145 "output",
146 "sample";
147 resets = <&ccu RST_BUS_MMC0>;
148 reset-names = "ahb";
149 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
150 status = "disabled";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154
155 mmc1: mmc@01c10000 {
156 compatible = "allwinner,sun7i-a20-mmc";
157 reg = <0x01c10000 0x1000>;
158 clocks = <&ccu CLK_BUS_MMC1>,
159 <&ccu CLK_MMC1>,
160 <&ccu CLK_MMC1_OUTPUT>,
161 <&ccu CLK_MMC1_SAMPLE>;
162 clock-names = "ahb",
163 "mmc",
164 "output",
165 "sample";
166 resets = <&ccu RST_BUS_MMC1>;
167 reset-names = "ahb";
168 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
169 status = "disabled";
170 #address-cells = <1>;
171 #size-cells = <0>;
172 };
173
174 mmc2: mmc@01c11000 {
175 compatible = "allwinner,sun7i-a20-mmc";
176 reg = <0x01c11000 0x1000>;
177 clocks = <&ccu CLK_BUS_MMC2>,
178 <&ccu CLK_MMC2>,
179 <&ccu CLK_MMC2_OUTPUT>,
180 <&ccu CLK_MMC2_SAMPLE>;
181 clock-names = "ahb",
182 "mmc",
183 "output",
184 "sample";
185 resets = <&ccu RST_BUS_MMC2>;
186 reset-names = "ahb";
187 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
188 status = "disabled";
189 #address-cells = <1>;
190 #size-cells = <0>;
191 };
192
193 nfc: nand@01c03000 {
194 compatible = "allwinner,sun4i-a10-nand";
195 reg = <0x01c03000 0x1000>;
196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
198 clock-names = "ahb", "mod";
199 resets = <&ccu RST_BUS_NAND>;
200 reset-names = "ahb";
201 status = "disabled";
202 #address-cells = <1>;
203 #size-cells = <0>;
204 };
205
206 usb_otg: usb@01c19000 {
207 /* compatible gets set in SoC specific dtsi file */
208 reg = <0x01c19000 0x0400>;
209 clocks = <&ccu CLK_BUS_OTG>;
210 resets = <&ccu RST_BUS_OTG>;
211 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
212 interrupt-names = "mc";
213 phys = <&usbphy 0>;
214 phy-names = "usb";
215 extcon = <&usbphy 0>;
216 status = "disabled";
217 };
218
219 usbphy: phy@01c19400 {
220 /*
221 * compatible and address regions get set in
222 * SoC specific dtsi file
223 */
224 clocks = <&ccu CLK_USB_PHY0>,
225 <&ccu CLK_USB_PHY1>;
226 clock-names = "usb0_phy",
227 "usb1_phy";
228 resets = <&ccu RST_USB_PHY0>,
229 <&ccu RST_USB_PHY1>;
230 reset-names = "usb0_reset",
231 "usb1_reset";
232 status = "disabled";
233 #phy-cells = <1>;
234 };
235
236 ehci0: usb@01c1a000 {
237 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
238 reg = <0x01c1a000 0x100>;
239 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&ccu CLK_BUS_EHCI>;
241 resets = <&ccu RST_BUS_EHCI>;
242 phys = <&usbphy 1>;
243 phy-names = "usb";
244 status = "disabled";
245 };
246
247 ohci0: usb@01c1a400 {
248 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
249 reg = <0x01c1a400 0x100>;
250 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
252 resets = <&ccu RST_BUS_OHCI>;
253 phys = <&usbphy 1>;
254 phy-names = "usb";
255 status = "disabled";
256 };
257
258 ccu: clock@01c20000 {
259 reg = <0x01c20000 0x400>;
260 clocks = <&osc24M>, <&rtc 0>;
261 clock-names = "hosc", "losc";
262 #clock-cells = <1>;
263 #reset-cells = <1>;
264 };
265
266 pio: pinctrl@01c20800 {
267 /* compatible gets set in SoC specific dtsi file */
268 reg = <0x01c20800 0x400>;
269 /* interrupts get set in SoC specific dtsi file */
270 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
271 clock-names = "apb", "hosc", "losc";
272 gpio-controller;
273 interrupt-controller;
274 #interrupt-cells = <3>;
275 #gpio-cells = <3>;
276
277 uart0_pins_a: uart0@0 {
278 pins = "PF2", "PF4";
279 function = "uart0";
280 };
281
282 uart1_pins_a: uart1@0 {
283 pins = "PG6", "PG7";
284 function = "uart1";
285 };
286
287 uart1_pins_cts_rts_a: uart1-cts-rts@0 {
288 pins = "PG8", "PG9";
289 function = "uart1";
290 };
291
292 mmc0_pins_a: mmc0@0 {
293 pins = "PF0", "PF1", "PF2",
294 "PF3", "PF4", "PF5";
295 function = "mmc0";
296 drive-strength = <30>;
297 bias-pull-up;
298 };
299
300 mmc1_pins_a: mmc1@0 {
301 pins = "PG0", "PG1", "PG2",
302 "PG3", "PG4", "PG5";
303 function = "mmc1";
304 drive-strength = <30>;
305 bias-pull-up;
306 };
307
308 mmc2_8bit_pins: mmc2_8bit {
309 pins = "PC5", "PC6", "PC8",
310 "PC9", "PC10", "PC11",
311 "PC12", "PC13", "PC14",
312 "PC15", "PC16";
313 function = "mmc2";
314 drive-strength = <30>;
315 bias-pull-up;
316 };
317
318 pwm0_pins: pwm0 {
319 pins = "PH0";
320 function = "pwm0";
321 };
322
323 i2c0_pins_a: i2c0@0 {
324 pins = "PH2", "PH3";
325 function = "i2c0";
326 };
327
328 i2c1_pins_a: i2c1@0 {
329 pins = "PH4", "PH5";
330 function = "i2c1";
331 };
332
333 i2c2_pins_a: i2c2@0 {
334 pins = "PE12", "PE13";
335 function = "i2c2";
336 };
337
338 lcd_rgb666_pins: lcd-rgb666@0 {
339 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
340 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
341 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
342 "PD24", "PD25", "PD26", "PD27";
343 function = "lcd0";
344 };
345 };
346
347 timer@01c20c00 {
348 compatible = "allwinner,sun4i-a10-timer";
349 reg = <0x01c20c00 0xa0>;
350 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&osc24M>;
353 };
354
355 wdt0: watchdog@01c20ca0 {
356 compatible = "allwinner,sun6i-a31-wdt";
357 reg = <0x01c20ca0 0x20>;
358 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
359 };
360
361 pwm: pwm@01c21400 {
362 compatible = "allwinner,sun7i-a20-pwm";
363 reg = <0x01c21400 0xc>;
364 clocks = <&osc24M>;
365 #pwm-cells = <3>;
366 status = "disabled";
367 };
368
369 lradc: lradc@01c22800 {
370 compatible = "allwinner,sun4i-a10-lradc-keys";
371 reg = <0x01c22800 0x100>;
372 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
373 status = "disabled";
374 };
375
376 uart0: serial@01c28000 {
377 compatible = "snps,dw-apb-uart";
378 reg = <0x01c28000 0x400>;
379 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
380 reg-shift = <2>;
381 reg-io-width = <4>;
382 clocks = <&ccu CLK_BUS_UART0>;
383 resets = <&ccu RST_BUS_UART0>;
384 dmas = <&dma 6>, <&dma 6>;
385 dma-names = "rx", "tx";
386 status = "disabled";
387 };
388
389 uart1: serial@01c28400 {
390 compatible = "snps,dw-apb-uart";
391 reg = <0x01c28400 0x400>;
392 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
393 reg-shift = <2>;
394 reg-io-width = <4>;
395 clocks = <&ccu CLK_BUS_UART1>;
396 resets = <&ccu RST_BUS_UART1>;
397 dmas = <&dma 7>, <&dma 7>;
398 dma-names = "rx", "tx";
399 status = "disabled";
400 };
401
402 uart2: serial@01c28800 {
403 compatible = "snps,dw-apb-uart";
404 reg = <0x01c28800 0x400>;
405 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
406 reg-shift = <2>;
407 reg-io-width = <4>;
408 clocks = <&ccu CLK_BUS_UART2>;
409 resets = <&ccu RST_BUS_UART2>;
410 dmas = <&dma 8>, <&dma 8>;
411 dma-names = "rx", "tx";
412 status = "disabled";
413 };
414
415 uart3: serial@01c28c00 {
416 compatible = "snps,dw-apb-uart";
417 reg = <0x01c28c00 0x400>;
418 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
419 reg-shift = <2>;
420 reg-io-width = <4>;
421 clocks = <&ccu CLK_BUS_UART3>;
422 resets = <&ccu RST_BUS_UART3>;
423 dmas = <&dma 9>, <&dma 9>;
424 dma-names = "rx", "tx";
425 status = "disabled";
426 };
427
428 uart4: serial@01c29000 {
429 compatible = "snps,dw-apb-uart";
430 reg = <0x01c29000 0x400>;
431 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
432 reg-shift = <2>;
433 reg-io-width = <4>;
434 clocks = <&ccu CLK_BUS_UART4>;
435 resets = <&ccu RST_BUS_UART4>;
436 dmas = <&dma 10>, <&dma 10>;
437 dma-names = "rx", "tx";
438 status = "disabled";
439 };
440
441 i2c0: i2c@01c2ac00 {
442 compatible = "allwinner,sun6i-a31-i2c";
443 reg = <0x01c2ac00 0x400>;
444 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_BUS_I2C0>;
446 resets = <&ccu RST_BUS_I2C0>;
447 status = "disabled";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 };
451
452 i2c1: i2c@01c2b000 {
453 compatible = "allwinner,sun6i-a31-i2c";
454 reg = <0x01c2b000 0x400>;
455 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&ccu CLK_BUS_I2C1>;
457 resets = <&ccu RST_BUS_I2C1>;
458 status = "disabled";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 };
462
463 i2c2: i2c@01c2b400 {
464 compatible = "allwinner,sun6i-a31-i2c";
465 reg = <0x01c2b400 0x400>;
466 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&ccu CLK_BUS_I2C2>;
468 resets = <&ccu RST_BUS_I2C2>;
469 status = "disabled";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 };
473
474 mali: gpu@1c40000 {
475 compatible = "allwinner,sun8i-a23-mali",
476 "allwinner,sun7i-a20-mali", "arm,mali-400";
477 reg = <0x01c40000 0x10000>;
478 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "gp",
486 "gpmmu",
487 "pp0",
488 "ppmmu0",
489 "pp1",
490 "ppmmu1",
491 "pmu";
492 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
493 clock-names = "bus", "core";
494 resets = <&ccu RST_BUS_GPU>;
495 #cooling-cells = <2>;
496
497 assigned-clocks = <&ccu CLK_GPU>;
498 assigned-clock-rates = <384000000>;
499 };
500
501 gic: interrupt-controller@01c81000 {
502 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
503 reg = <0x01c81000 0x1000>,
504 <0x01c82000 0x2000>,
505 <0x01c84000 0x2000>,
506 <0x01c86000 0x2000>;
507 interrupt-controller;
508 #interrupt-cells = <3>;
509 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
510 };
511
512 rtc: rtc@01f00000 {
513 compatible = "allwinner,sun6i-a31-rtc";
514 reg = <0x01f00000 0x54>;
515 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
517 clock-output-names = "osc32k";
518 clocks = <&ext_osc32k>;
519 #clock-cells = <1>;
520 };
521
522 nmi_intc: interrupt-controller@1f00c00 {
523 compatible = "allwinner,sun6i-a31-r-intc";
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 reg = <0x01f00c00 0x400>;
527 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
528 };
529
530 prcm@01f01400 {
531 compatible = "allwinner,sun8i-a23-prcm";
532 reg = <0x01f01400 0x200>;
533
534 ar100: ar100_clk {
535 compatible = "fixed-factor-clock";
536 #clock-cells = <0>;
537 clock-div = <1>;
538 clock-mult = <1>;
539 clocks = <&osc24M>;
540 clock-output-names = "ar100";
541 };
542
543 ahb0: ahb0_clk {
544 compatible = "fixed-factor-clock";
545 #clock-cells = <0>;
546 clock-div = <1>;
547 clock-mult = <1>;
548 clocks = <&ar100>;
549 clock-output-names = "ahb0";
550 };
551
552 apb0: apb0_clk {
553 compatible = "allwinner,sun8i-a23-apb0-clk";
554 #clock-cells = <0>;
555 clocks = <&ahb0>;
556 clock-output-names = "apb0";
557 };
558
559 apb0_gates: apb0_gates_clk {
560 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
561 #clock-cells = <1>;
562 clocks = <&apb0>;
563 clock-output-names = "apb0_pio", "apb0_timer",
564 "apb0_rsb", "apb0_uart",
565 "apb0_i2c";
566 };
567
568 apb0_rst: apb0_rst {
569 compatible = "allwinner,sun6i-a31-clock-reset";
570 #reset-cells = <1>;
571 };
572
573 codec_analog: codec-analog {
574 compatible = "allwinner,sun8i-a23-codec-analog";
575 };
576 };
577
578 cpucfg@01f01c00 {
579 compatible = "allwinner,sun8i-a23-cpuconfig";
580 reg = <0x01f01c00 0x300>;
581 };
582
583 r_uart: serial@01f02800 {
584 compatible = "snps,dw-apb-uart";
585 reg = <0x01f02800 0x400>;
586 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
587 reg-shift = <2>;
588 reg-io-width = <4>;
589 clocks = <&apb0_gates 4>;
590 resets = <&apb0_rst 4>;
591 status = "disabled";
592 };
593
594 r_pio: pinctrl@01f02c00 {
595 compatible = "allwinner,sun8i-a23-r-pinctrl";
596 reg = <0x01f02c00 0x400>;
597 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
599 clock-names = "apb", "hosc", "losc";
600 resets = <&apb0_rst 0>;
601 gpio-controller;
602 interrupt-controller;
603 #interrupt-cells = <3>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 #gpio-cells = <3>;
607
608 r_rsb_pins: r_rsb {
609 pins = "PL0", "PL1";
610 function = "s_rsb";
611 drive-strength = <20>;
612 bias-pull-up;
613 };
614
615 r_uart_pins_a: r_uart@0 {
616 pins = "PL2", "PL3";
617 function = "s_uart";
618 };
619 };
620
621 r_rsb: rsb@01f03400 {
622 compatible = "allwinner,sun8i-a23-rsb";
623 reg = <0x01f03400 0x400>;
624 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&apb0_gates 3>;
626 clock-frequency = <3000000>;
627 resets = <&apb0_rst 3>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&r_rsb_pins>;
630 status = "disabled";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 };
634 };
635 };
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