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tegra: dts: Sync tegra20 device tree files with Linux
[people/ms/u-boot.git] / arch / arm / dts / tegra20-seaboard.dts
1 /dts-v1/;
2
3 #include <dt-bindings/input/input.h>
4 #include "tegra20.dtsi"
5
6 / {
7 model = "NVIDIA Seaboard";
8 compatible = "nvidia,seaboard", "nvidia,tegra20";
9
10 aliases {
11 /* This defines the order of our ports */
12 usb0 = "/usb@c5008000";
13 usb1 = "/usb@c5000000";
14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 rtc0 = "/i2c@7000d000/tps6586x@34";
19 rtc1 = "/rtc@7000e000";
20 serial0 = &uartd;
21 sdhci0 = "/sdhci@c8000600";
22 sdhci1 = "/sdhci@c8000400";
23 };
24
25 chosen {
26 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
27 };
28
29 chosen {
30 stdout-path = &uartd;
31 };
32
33 memory {
34 reg = <0x00000000 0x40000000>;
35 };
36
37 host1x@50000000 {
38 status = "okay";
39 dc@54200000 {
40 status = "okay";
41 rgb {
42 status = "okay";
43
44 nvidia,panel = <&panel>;
45 };
46 };
47
48 hdmi@54280000 {
49 status = "okay";
50
51 vdd-supply = <&hdmi_vdd_reg>;
52 pll-supply = <&hdmi_pll_reg>;
53 hdmi-supply = <&vdd_hdmi>;
54
55 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
56 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
57 GPIO_ACTIVE_HIGH>;
58 };
59 };
60
61 pinmux@70000014 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&state_default>;
64
65 state_default: pinmux {
66 ata {
67 nvidia,pins = "ata";
68 nvidia,function = "ide";
69 };
70 atb {
71 nvidia,pins = "atb", "gma", "gme";
72 nvidia,function = "sdio4";
73 };
74 atc {
75 nvidia,pins = "atc";
76 nvidia,function = "nand";
77 };
78 atd {
79 nvidia,pins = "atd", "ate", "gmb", "spia",
80 "spib", "spic";
81 nvidia,function = "gmi";
82 };
83 cdev1 {
84 nvidia,pins = "cdev1";
85 nvidia,function = "plla_out";
86 };
87 cdev2 {
88 nvidia,pins = "cdev2";
89 nvidia,function = "pllp_out4";
90 };
91 crtp {
92 nvidia,pins = "crtp", "lm1";
93 nvidia,function = "crt";
94 };
95 csus {
96 nvidia,pins = "csus";
97 nvidia,function = "vi_sensor_clk";
98 };
99 dap1 {
100 nvidia,pins = "dap1";
101 nvidia,function = "dap1";
102 };
103 dap2 {
104 nvidia,pins = "dap2";
105 nvidia,function = "dap2";
106 };
107 dap3 {
108 nvidia,pins = "dap3";
109 nvidia,function = "dap3";
110 };
111 dap4 {
112 nvidia,pins = "dap4";
113 nvidia,function = "dap4";
114 };
115 dta {
116 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
117 nvidia,function = "vi";
118 };
119 dtf {
120 nvidia,pins = "dtf";
121 nvidia,function = "i2c3";
122 };
123 gmc {
124 nvidia,pins = "gmc";
125 nvidia,function = "uartd";
126 };
127 gmd {
128 nvidia,pins = "gmd";
129 nvidia,function = "sflash";
130 };
131 gpu {
132 nvidia,pins = "gpu";
133 nvidia,function = "pwm";
134 };
135 gpu7 {
136 nvidia,pins = "gpu7";
137 nvidia,function = "rtck";
138 };
139 gpv {
140 nvidia,pins = "gpv", "slxa", "slxk";
141 nvidia,function = "pcie";
142 };
143 hdint {
144 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
145 "lsck", "lsda";
146 nvidia,function = "hdmi";
147 };
148 i2cp {
149 nvidia,pins = "i2cp";
150 nvidia,function = "i2cp";
151 };
152 irrx {
153 nvidia,pins = "irrx", "irtx";
154 nvidia,function = "uartb";
155 };
156 kbca {
157 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
158 "kbce", "kbcf";
159 nvidia,function = "kbc";
160 };
161 lcsn {
162 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
163 "lsdi", "lvp0";
164 nvidia,function = "rsvd4";
165 };
166 ld0 {
167 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
168 "ld5", "ld6", "ld7", "ld8", "ld9",
169 "ld10", "ld11", "ld12", "ld13", "ld14",
170 "ld15", "ld16", "ld17", "ldi", "lhp0",
171 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
172 "lspi", "lvp1", "lvs";
173 nvidia,function = "displaya";
174 };
175 owc {
176 nvidia,pins = "owc", "spdi", "spdo", "uac";
177 nvidia,function = "rsvd2";
178 };
179 pmc {
180 nvidia,pins = "pmc";
181 nvidia,function = "pwr_on";
182 };
183 rm {
184 nvidia,pins = "rm";
185 nvidia,function = "i2c1";
186 };
187 sdb {
188 nvidia,pins = "sdb", "sdc", "sdd";
189 nvidia,function = "sdio3";
190 };
191 sdio1 {
192 nvidia,pins = "sdio1";
193 nvidia,function = "sdio1";
194 };
195 slxc {
196 nvidia,pins = "slxc", "slxd";
197 nvidia,function = "spdif";
198 };
199 spid {
200 nvidia,pins = "spid", "spie", "spif";
201 nvidia,function = "spi1";
202 };
203 spig {
204 nvidia,pins = "spig", "spih";
205 nvidia,function = "spi2_alt";
206 };
207 uaa {
208 nvidia,pins = "uaa", "uab", "uda";
209 nvidia,function = "ulpi";
210 };
211 uad {
212 nvidia,pins = "uad";
213 nvidia,function = "irda";
214 };
215 uca {
216 nvidia,pins = "uca", "ucb";
217 nvidia,function = "uartc";
218 };
219 conf_ata {
220 nvidia,pins = "ata", "atb", "atc", "atd",
221 "cdev1", "cdev2", "dap1", "dap2",
222 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
223 "gme", "gpu", "gpu7", "i2cp", "irrx",
224 "irtx", "pta", "rm", "sdc", "sdd",
225 "slxd", "slxk", "spdi", "spdo", "uac",
226 "uad", "uca", "ucb", "uda";
227 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
228 nvidia,tristate = <TEGRA_PIN_DISABLE>;
229 };
230 conf_ate {
231 nvidia,pins = "ate", "csus", "dap3",
232 "gpv", "owc", "slxc", "spib", "spid",
233 "spie";
234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
236 };
237 conf_ck32 {
238 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
239 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 };
242 conf_crtp {
243 nvidia,pins = "crtp", "gmb", "slxa", "spia",
244 "spig", "spih";
245 nvidia,pull = <TEGRA_PIN_PULL_UP>;
246 nvidia,tristate = <TEGRA_PIN_ENABLE>;
247 };
248 conf_dta {
249 nvidia,pins = "dta", "dtb", "dtc", "dtd";
250 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
252 };
253 conf_dte {
254 nvidia,pins = "dte", "spif";
255 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
256 nvidia,tristate = <TEGRA_PIN_ENABLE>;
257 };
258 conf_hdint {
259 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
260 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
261 "lvp0";
262 nvidia,tristate = <TEGRA_PIN_ENABLE>;
263 };
264 conf_kbca {
265 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
266 "kbce", "kbcf", "sdio1", "spic", "uaa",
267 "uab";
268 nvidia,pull = <TEGRA_PIN_PULL_UP>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 };
271 conf_lc {
272 nvidia,pins = "lc", "ls";
273 nvidia,pull = <TEGRA_PIN_PULL_UP>;
274 };
275 conf_ld0 {
276 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
277 "ld5", "ld6", "ld7", "ld8", "ld9",
278 "ld10", "ld11", "ld12", "ld13", "ld14",
279 "ld15", "ld16", "ld17", "ldi", "lhp0",
280 "lhp1", "lhp2", "lhs", "lm0", "lpp",
281 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
282 "lvs", "pmc", "sdb";
283 nvidia,tristate = <TEGRA_PIN_DISABLE>;
284 };
285 conf_ld17_0 {
286 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
287 "ld23_22";
288 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
289 };
290 drive_sdio1 {
291 nvidia,pins = "drive_sdio1";
292 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
293 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
294 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
295 nvidia,pull-down-strength = <31>;
296 nvidia,pull-up-strength = <31>;
297 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
298 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
299 };
300 };
301
302 state_i2cmux_ddc: pinmux_i2cmux_ddc {
303 ddc {
304 nvidia,pins = "ddc";
305 nvidia,function = "i2c2";
306 };
307 pta {
308 nvidia,pins = "pta";
309 nvidia,function = "rsvd4";
310 };
311 };
312
313 state_i2cmux_pta: pinmux_i2cmux_pta {
314 ddc {
315 nvidia,pins = "ddc";
316 nvidia,function = "rsvd4";
317 };
318 pta {
319 nvidia,pins = "pta";
320 nvidia,function = "i2c2";
321 };
322 };
323
324 state_i2cmux_idle: pinmux_i2cmux_idle {
325 ddc {
326 nvidia,pins = "ddc";
327 nvidia,function = "rsvd4";
328 };
329 pta {
330 nvidia,pins = "pta";
331 nvidia,function = "rsvd4";
332 };
333 };
334 };
335
336 i2s@70002800 {
337 status = "okay";
338 };
339
340 serial@70006300 {
341 status = "okay";
342 clock-frequency = < 216000000 >;
343 };
344
345 nand-controller@70008000 {
346 nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
347 nvidia,width = <8>;
348 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
349 nand@0 {
350 reg = <0>;
351 compatible = "hynix,hy27uf4g2b", "nand-flash";
352 };
353 };
354
355 pwm: pwm@7000a000 {
356 status = "okay";
357 };
358
359 i2c@7000c000 {
360 status = "okay";
361 clock-frequency = <400000>;
362
363 wm8903: wm8903@1a {
364 compatible = "wlf,wm8903";
365 reg = <0x1a>;
366 interrupt-parent = <&gpio>;
367 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
368
369 gpio-controller;
370 #gpio-cells = <2>;
371
372 micdet-cfg = <0>;
373 micdet-delay = <100>;
374 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
375 };
376
377 /* ALS and proximity sensor */
378 isl29018@44 {
379 compatible = "isil,isl29018";
380 reg = <0x44>;
381 interrupt-parent = <&gpio>;
382 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
383 };
384
385 gyrometer@68 {
386 compatible = "invn,mpu3050";
387 reg = <0x68>;
388 interrupt-parent = <&gpio>;
389 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
390 };
391 };
392
393 i2c@7000c400 {
394 status = "okay";
395 clock-frequency = <100000>;
396 };
397
398 i2cmux {
399 compatible = "i2c-mux-pinctrl";
400 #address-cells = <1>;
401 #size-cells = <0>;
402
403 i2c-parent = <&{/i2c@7000c400}>;
404
405 pinctrl-names = "ddc", "pta", "idle";
406 pinctrl-0 = <&state_i2cmux_ddc>;
407 pinctrl-1 = <&state_i2cmux_pta>;
408 pinctrl-2 = <&state_i2cmux_idle>;
409
410 hdmi_ddc: i2c@0 {
411 reg = <0>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 };
415
416 lvds_ddc: i2c@1 {
417 reg = <1>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420
421 smart-battery@b {
422 compatible = "ti,bq20z75", "smart-battery-1.1";
423 reg = <0xb>;
424 ti,i2c-retry-count = <2>;
425 ti,poll-retry-count = <10>;
426 };
427 };
428 };
429
430 i2c@7000c500 {
431 status = "okay";
432 clock-frequency = <400000>;
433 };
434
435 i2c@7000d000 {
436 status = "okay";
437 clock-frequency = <400000>;
438
439 magnetometer@c {
440 compatible = "asahi-kasei,ak8975";
441 reg = <0xc>;
442 interrupt-parent = <&gpio>;
443 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
444 };
445
446 pmic: tps6586x@34 {
447 compatible = "ti,tps6586x";
448 reg = <0x34>;
449 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
450
451 ti,system-power-controller;
452
453 #gpio-cells = <2>;
454 gpio-controller;
455
456 sys-supply = <&vdd_5v0_reg>;
457 vin-sm0-supply = <&sys_reg>;
458 vin-sm1-supply = <&sys_reg>;
459 vin-sm2-supply = <&sys_reg>;
460 vinldo01-supply = <&sm2_reg>;
461 vinldo23-supply = <&sm2_reg>;
462 vinldo4-supply = <&sm2_reg>;
463 vinldo678-supply = <&sm2_reg>;
464 vinldo9-supply = <&sm2_reg>;
465
466 regulators {
467 sys_reg: sys {
468 regulator-name = "vdd_sys";
469 regulator-always-on;
470 };
471
472 sm0 {
473 regulator-name = "vdd_sm0,vdd_core";
474 regulator-min-microvolt = <1300000>;
475 regulator-max-microvolt = <1300000>;
476 regulator-always-on;
477 };
478
479 sm1 {
480 regulator-name = "vdd_sm1,vdd_cpu";
481 regulator-min-microvolt = <1125000>;
482 regulator-max-microvolt = <1125000>;
483 regulator-always-on;
484 };
485
486 sm2_reg: sm2 {
487 regulator-name = "vdd_sm2,vin_ldo*";
488 regulator-min-microvolt = <3700000>;
489 regulator-max-microvolt = <3700000>;
490 regulator-always-on;
491 };
492
493 /* LDO0 is not connected to anything */
494
495 ldo1 {
496 regulator-name = "vdd_ldo1,avdd_pll*";
497 regulator-min-microvolt = <1100000>;
498 regulator-max-microvolt = <1100000>;
499 regulator-always-on;
500 };
501
502 ldo2 {
503 regulator-name = "vdd_ldo2,vdd_rtc";
504 regulator-min-microvolt = <1200000>;
505 regulator-max-microvolt = <1200000>;
506 };
507
508 ldo3 {
509 regulator-name = "vdd_ldo3,avdd_usb*";
510 regulator-min-microvolt = <3300000>;
511 regulator-max-microvolt = <3300000>;
512 regulator-always-on;
513 };
514
515 ldo4 {
516 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
517 regulator-min-microvolt = <1800000>;
518 regulator-max-microvolt = <1800000>;
519 regulator-always-on;
520 };
521
522 ldo5 {
523 regulator-name = "vdd_ldo5,vcore_mmc";
524 regulator-min-microvolt = <2850000>;
525 regulator-max-microvolt = <2850000>;
526 regulator-always-on;
527 };
528
529 ldo6 {
530 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
531 regulator-min-microvolt = <1800000>;
532 regulator-max-microvolt = <1800000>;
533 };
534
535 hdmi_vdd_reg: ldo7 {
536 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
537 regulator-min-microvolt = <3300000>;
538 regulator-max-microvolt = <3300000>;
539 };
540
541 hdmi_pll_reg: ldo8 {
542 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
543 regulator-min-microvolt = <1800000>;
544 regulator-max-microvolt = <1800000>;
545 };
546
547 ldo9 {
548 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
549 regulator-min-microvolt = <2850000>;
550 regulator-max-microvolt = <2850000>;
551 regulator-always-on;
552 };
553
554 ldo_rtc {
555 regulator-name = "vdd_rtc_out,vdd_cell";
556 regulator-min-microvolt = <3300000>;
557 regulator-max-microvolt = <3300000>;
558 regulator-always-on;
559 };
560 };
561 };
562
563 temperature-sensor@4c {
564 compatible = "onnn,nct1008";
565 reg = <0x4c>;
566 };
567 };
568
569 kbc@7000e200 {
570 status = "okay";
571 nvidia,debounce-delay-ms = <32>;
572 nvidia,repeat-delay-ms = <160>;
573 nvidia,ghost-filter;
574 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
575 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
576 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
577 MATRIX_KEY(0x00, 0x03, KEY_S)
578 MATRIX_KEY(0x00, 0x04, KEY_A)
579 MATRIX_KEY(0x00, 0x05, KEY_Z)
580 MATRIX_KEY(0x00, 0x07, KEY_FN)
581
582 MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
583 MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
584 MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
585
586 MATRIX_KEY(0x03, 0x00, KEY_5)
587 MATRIX_KEY(0x03, 0x01, KEY_4)
588 MATRIX_KEY(0x03, 0x02, KEY_R)
589 MATRIX_KEY(0x03, 0x03, KEY_E)
590 MATRIX_KEY(0x03, 0x04, KEY_F)
591 MATRIX_KEY(0x03, 0x05, KEY_D)
592 MATRIX_KEY(0x03, 0x06, KEY_X)
593
594 MATRIX_KEY(0x04, 0x00, KEY_7)
595 MATRIX_KEY(0x04, 0x01, KEY_6)
596 MATRIX_KEY(0x04, 0x02, KEY_T)
597 MATRIX_KEY(0x04, 0x03, KEY_H)
598 MATRIX_KEY(0x04, 0x04, KEY_G)
599 MATRIX_KEY(0x04, 0x05, KEY_V)
600 MATRIX_KEY(0x04, 0x06, KEY_C)
601 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
602
603 MATRIX_KEY(0x05, 0x00, KEY_9)
604 MATRIX_KEY(0x05, 0x01, KEY_8)
605 MATRIX_KEY(0x05, 0x02, KEY_U)
606 MATRIX_KEY(0x05, 0x03, KEY_Y)
607 MATRIX_KEY(0x05, 0x04, KEY_J)
608 MATRIX_KEY(0x05, 0x05, KEY_N)
609 MATRIX_KEY(0x05, 0x06, KEY_B)
610 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
611
612 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
613 MATRIX_KEY(0x06, 0x01, KEY_0)
614 MATRIX_KEY(0x06, 0x02, KEY_O)
615 MATRIX_KEY(0x06, 0x03, KEY_I)
616 MATRIX_KEY(0x06, 0x04, KEY_L)
617 MATRIX_KEY(0x06, 0x05, KEY_K)
618 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
619 MATRIX_KEY(0x06, 0x07, KEY_M)
620
621 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
622 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
623 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
624 MATRIX_KEY(0x07, 0x07, KEY_MENU)
625
626 MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
627 MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
628
629 MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
630 MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
631
632 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
633 MATRIX_KEY(0x0B, 0x01, KEY_P)
634 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
635 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
636 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
637 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
638
639 MATRIX_KEY(0x0C, 0x00, KEY_F10)
640 MATRIX_KEY(0x0C, 0x01, KEY_F9)
641 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
642 MATRIX_KEY(0x0C, 0x03, KEY_3)
643 MATRIX_KEY(0x0C, 0x04, KEY_2)
644 MATRIX_KEY(0x0C, 0x05, KEY_UP)
645 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
646 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
647
648 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
649 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
650 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
651 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
652 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
653 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
654 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
655
656 MATRIX_KEY(0x0E, 0x00, KEY_F11)
657 MATRIX_KEY(0x0E, 0x01, KEY_F12)
658 MATRIX_KEY(0x0E, 0x02, KEY_F8)
659 MATRIX_KEY(0x0E, 0x03, KEY_Q)
660 MATRIX_KEY(0x0E, 0x04, KEY_F4)
661 MATRIX_KEY(0x0E, 0x05, KEY_F3)
662 MATRIX_KEY(0x0E, 0x06, KEY_1)
663 MATRIX_KEY(0x0E, 0x07, KEY_F7)
664
665 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
666 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
667 MATRIX_KEY(0x0F, 0x02, KEY_F5)
668 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
669 MATRIX_KEY(0x0F, 0x04, KEY_F1)
670 MATRIX_KEY(0x0F, 0x05, KEY_F2)
671 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
672 MATRIX_KEY(0x0F, 0x07, KEY_F6)
673
674 /* Software Handled Function Keys */
675 MATRIX_KEY(0x14, 0x00, KEY_KP7)
676
677 MATRIX_KEY(0x15, 0x00, KEY_KP9)
678 MATRIX_KEY(0x15, 0x01, KEY_KP8)
679 MATRIX_KEY(0x15, 0x02, KEY_KP4)
680 MATRIX_KEY(0x15, 0x04, KEY_KP1)
681
682 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
683 MATRIX_KEY(0x16, 0x02, KEY_KP6)
684 MATRIX_KEY(0x16, 0x03, KEY_KP5)
685 MATRIX_KEY(0x16, 0x04, KEY_KP3)
686 MATRIX_KEY(0x16, 0x05, KEY_KP2)
687 MATRIX_KEY(0x16, 0x07, KEY_KP0)
688
689 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
690 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
691 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
692 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
693
694 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
695
696 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
697 MATRIX_KEY(0x1D, 0x04, KEY_END)
698 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
699 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
700 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
701
702 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
703 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
704 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
705
706 MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
707 };
708
709 pmc@7000e400 {
710 nvidia,invert-interrupt;
711 nvidia,suspend-mode = <1>;
712 nvidia,cpu-pwr-good-time = <5000>;
713 nvidia,cpu-pwr-off-time = <5000>;
714 nvidia,core-pwr-good-time = <3845 3845>;
715 nvidia,core-pwr-off-time = <3875>;
716 nvidia,sys-clock-req-active-high;
717 };
718
719 memory-controller@7000f400 {
720 emc-table@190000 {
721 reg = <190000>;
722 compatible = "nvidia,tegra20-emc-table";
723 clock-frequency = <190000>;
724 nvidia,emc-registers = <0x0000000c 0x00000026
725 0x00000009 0x00000003 0x00000004 0x00000004
726 0x00000002 0x0000000c 0x00000003 0x00000003
727 0x00000002 0x00000001 0x00000004 0x00000005
728 0x00000004 0x00000009 0x0000000d 0x0000059f
729 0x00000000 0x00000003 0x00000003 0x00000003
730 0x00000003 0x00000001 0x0000000b 0x000000c8
731 0x00000003 0x00000007 0x00000004 0x0000000f
732 0x00000002 0x00000000 0x00000000 0x00000002
733 0x00000000 0x00000000 0x00000083 0xa06204ae
734 0x007dc010 0x00000000 0x00000000 0x00000000
735 0x00000000 0x00000000 0x00000000 0x00000000>;
736 };
737
738 emc-table@380000 {
739 reg = <380000>;
740 compatible = "nvidia,tegra20-emc-table";
741 clock-frequency = <380000>;
742 nvidia,emc-registers = <0x00000017 0x0000004b
743 0x00000012 0x00000006 0x00000004 0x00000005
744 0x00000003 0x0000000c 0x00000006 0x00000006
745 0x00000003 0x00000001 0x00000004 0x00000005
746 0x00000004 0x00000009 0x0000000d 0x00000b5f
747 0x00000000 0x00000003 0x00000003 0x00000006
748 0x00000006 0x00000001 0x00000011 0x000000c8
749 0x00000003 0x0000000e 0x00000007 0x0000000f
750 0x00000002 0x00000000 0x00000000 0x00000002
751 0x00000000 0x00000000 0x00000083 0xe044048b
752 0x007d8010 0x00000000 0x00000000 0x00000000
753 0x00000000 0x00000000 0x00000000 0x00000000>;
754 };
755 };
756
757 usb@c5000000 {
758 status = "okay";
759 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
760 dr_mode = "otg";
761 };
762
763 usb-phy@c5000000 {
764 status = "okay";
765 vbus-supply = <&vbus_reg>;
766 dr_mode = "otg";
767 };
768
769 usb@c5004000 {
770 status = "disabled";
771 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
772 GPIO_ACTIVE_LOW>;
773 };
774
775 usb-phy@c5004000 {
776 status = "okay";
777 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
778 GPIO_ACTIVE_LOW>;
779 };
780
781 usb@c5008000 {
782 status = "okay";
783 };
784
785 usb-phy@c5008000 {
786 status = "okay";
787 };
788
789 sdhci@c8000000 {
790 status = "okay";
791 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
792 bus-width = <4>;
793 keep-power-in-suspend;
794 };
795
796 sdhci@c8000400 {
797 status = "okay";
798 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
799 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
800 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
801 bus-width = <4>;
802 };
803
804 sdhci@c8000600 {
805 status = "okay";
806 bus-width = <8>;
807 non-removable;
808 };
809
810 backlight: backlight {
811 compatible = "pwm-backlight";
812
813 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
814 power-supply = <&vdd_bl_reg>;
815 pwms = <&pwm 2 5000000>;
816
817 brightness-levels = <0 4 8 16 32 64 128 255>;
818 default-brightness-level = <6>;
819 };
820
821 clocks {
822 compatible = "simple-bus";
823 #address-cells = <1>;
824 #size-cells = <0>;
825
826 clk32k_in: clock@0 {
827 compatible = "fixed-clock";
828 reg=<0>;
829 #clock-cells = <0>;
830 clock-frequency = <32768>;
831 };
832 };
833
834 gpio-keys {
835 compatible = "gpio-keys";
836
837 power {
838 label = "Power";
839 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
840 linux,code = <KEY_POWER>;
841 gpio-key,wakeup;
842 };
843
844 lid {
845 label = "Lid";
846 gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
847 linux,input-type = <5>; /* EV_SW */
848 linux,code = <0>; /* SW_LID */
849 debounce-interval = <1>;
850 gpio-key,wakeup;
851 };
852 };
853
854 panel: panel {
855 /* Seaboard has 1366x768 */
856 clock = <70600000>;
857 xres = <1366>;
858 yres = <768>;
859 left-margin = <58>;
860 right-margin = <58>;
861 hsync-len = <58>;
862 lower-margin = <4>;
863 upper-margin = <4>;
864 vsync-len = <4>;
865 hsync-active-high;
866 nvidia,bits-per-pixel = <16>;
867 nvidia,pwm = <&pwm 2 0>;
868 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
869 GPIO_ACTIVE_HIGH>;
870 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
871 GPIO_ACTIVE_HIGH>;
872 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
873 GPIO_ACTIVE_HIGH>;
874 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
875 GPIO_ACTIVE_HIGH>;
876 nvidia,panel-timings = <400 4 203 17 15>;
877 };
878
879 regulators {
880 compatible = "simple-bus";
881 #address-cells = <1>;
882 #size-cells = <0>;
883
884 vdd_5v0_reg: regulator@0 {
885 compatible = "regulator-fixed";
886 reg = <0>;
887 regulator-name = "vdd_5v0";
888 regulator-min-microvolt = <5000000>;
889 regulator-max-microvolt = <5000000>;
890 regulator-always-on;
891 };
892
893 regulator@1 {
894 compatible = "regulator-fixed";
895 reg = <1>;
896 regulator-name = "vdd_1v5";
897 regulator-min-microvolt = <1500000>;
898 regulator-max-microvolt = <1500000>;
899 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
900 };
901
902 regulator@2 {
903 compatible = "regulator-fixed";
904 reg = <2>;
905 regulator-name = "vdd_1v2";
906 regulator-min-microvolt = <1200000>;
907 regulator-max-microvolt = <1200000>;
908 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
909 enable-active-high;
910 };
911
912 vbus_reg: regulator@3 {
913 compatible = "regulator-fixed";
914 reg = <3>;
915 regulator-name = "vdd_vbus_wup1";
916 regulator-min-microvolt = <5000000>;
917 regulator-max-microvolt = <5000000>;
918 enable-active-high;
919 gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
920 regulator-always-on;
921 regulator-boot-on;
922 };
923
924 vdd_pnl_reg: regulator@4 {
925 compatible = "regulator-fixed";
926 reg = <4>;
927 regulator-name = "vdd_pnl";
928 regulator-min-microvolt = <2800000>;
929 regulator-max-microvolt = <2800000>;
930 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
931 enable-active-high;
932 };
933
934 vdd_bl_reg: regulator@5 {
935 compatible = "regulator-fixed";
936 reg = <5>;
937 regulator-name = "vdd_bl";
938 regulator-min-microvolt = <2800000>;
939 regulator-max-microvolt = <2800000>;
940 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
941 enable-active-high;
942 };
943
944 vdd_hdmi: regulator@6 {
945 compatible = "regulator-fixed";
946 reg = <6>;
947 regulator-name = "VDDIO_HDMI";
948 regulator-min-microvolt = <5000000>;
949 regulator-max-microvolt = <5000000>;
950 gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
951 enable-active-high;
952 vin-supply = <&vdd_5v0_reg>;
953 };
954 };
955
956 sound {
957 compatible = "nvidia,tegra-audio-wm8903-seaboard",
958 "nvidia,tegra-audio-wm8903";
959 nvidia,model = "NVIDIA Tegra Seaboard";
960
961 nvidia,audio-routing =
962 "Headphone Jack", "HPOUTR",
963 "Headphone Jack", "HPOUTL",
964 "Int Spk", "ROP",
965 "Int Spk", "RON",
966 "Int Spk", "LOP",
967 "Int Spk", "LON",
968 "Mic Jack", "MICBIAS",
969 "IN1R", "Mic Jack";
970
971 nvidia,i2s-controller = <&tegra_i2s1>;
972 nvidia,audio-codec = <&wm8903>;
973
974 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
975 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
976
977 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
978 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
979 <&tegra_car TEGRA20_CLK_CDEV1>;
980 clock-names = "pll_a", "pll_a_out0", "mclk";
981 };
982 };
"Das U-Boot" Source Tree