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ARM: dts: UniPhier: sync device trees with the Linux kernel
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1 /*
2 * Device Tree Source for UniPhier PH1-Pro4 SoC
3 *
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 /include/ "skeleton.dtsi"
10
11 / {
12 compatible = "socionext,ph1-pro4";
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "socionext,uniphier-smp";
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 };
24
25 cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <1>;
29 };
30 };
31
32 clocks {
33 arm_timer_clk: arm_timer_clk {
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <50000000>;
37 };
38 };
39
40 soc {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 ranges;
45 interrupt-parent = <&intc>;
46
47 extbus: extbus {
48 compatible = "simple-bus";
49 #address-cells = <2>;
50 #size-cells = <1>;
51 };
52
53 uart0: serial@54006800 {
54 compatible = "socionext,uniphier-uart";
55 status = "disabled";
56 reg = <0x54006800 0x20>;
57 clock-frequency = <73728000>;
58 };
59
60 uart1: serial@54006900 {
61 compatible = "socionext,uniphier-uart";
62 status = "disabled";
63 reg = <0x54006900 0x20>;
64 clock-frequency = <73728000>;
65 };
66
67 uart2: serial@54006a00 {
68 compatible = "socionext,uniphier-uart";
69 status = "disabled";
70 reg = <0x54006a00 0x20>;
71 clock-frequency = <73728000>;
72 };
73
74 uart3: serial@54006b00 {
75 compatible = "socionext,uniphier-uart";
76 status = "disabled";
77 reg = <0x54006b00 0x20>;
78 clock-frequency = <73728000>;
79 };
80
81 i2c0: i2c@58780000 {
82 compatible = "socionext,uniphier-fi2c";
83 #address-cells = <1>;
84 #size-cells = <0>;
85 reg = <0x58780000 0x80>;
86 clock-frequency = <100000>;
87 status = "disabled";
88 };
89
90 i2c1: i2c@58781000 {
91 compatible = "socionext,uniphier-fi2c";
92 #address-cells = <1>;
93 #size-cells = <0>;
94 reg = <0x58781000 0x80>;
95 clock-frequency = <100000>;
96 status = "disabled";
97 };
98
99 i2c2: i2c@58782000 {
100 compatible = "socionext,uniphier-fi2c";
101 #address-cells = <1>;
102 #size-cells = <0>;
103 reg = <0x58782000 0x80>;
104 clock-frequency = <100000>;
105 status = "disabled";
106 };
107
108 i2c3: i2c@58783000 {
109 compatible = "socionext,uniphier-fi2c";
110 #address-cells = <1>;
111 #size-cells = <0>;
112 reg = <0x58783000 0x80>;
113 clock-frequency = <100000>;
114 status = "disabled";
115 };
116
117 /* i2c4 does not exist */
118
119 i2c5: i2c@58785000 {
120 compatible = "socionext,uniphier-fi2c";
121 #address-cells = <1>;
122 #size-cells = <0>;
123 reg = <0x58785000 0x80>;
124 clock-frequency = <400000>;
125 status = "ok";
126 };
127
128 i2c6: i2c@58786000 {
129 compatible = "socionext,uniphier-fi2c";
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <0x58786000 0x80>;
133 clock-frequency = <400000>;
134 status = "ok";
135 };
136
137 system-bus-controller-misc@59800000 {
138 compatible = "socionext,uniphier-system-bus-controller-misc",
139 "syscon";
140 reg = <0x59800000 0x2000>;
141 };
142
143 usb2: usb@5a800100 {
144 compatible = "socionext,uniphier-ehci", "generic-ehci";
145 status = "disabled";
146 reg = <0x5a800100 0x100>;
147 };
148
149 usb3: usb@5a810100 {
150 compatible = "socionext,uniphier-ehci", "generic-ehci";
151 status = "disabled";
152 reg = <0x5a810100 0x100>;
153 };
154
155 usb0: usb@65a00000 {
156 compatible = "socionext,uniphier-xhci", "generic-xhci";
157 status = "disabled";
158 reg = <0x65a00000 0x100>;
159 };
160
161 usb1: usb@65c00000 {
162 compatible = "socionext,uniphier-xhci", "generic-xhci";
163 status = "disabled";
164 reg = <0x65c00000 0x100>;
165 };
166
167 timer@60000200 {
168 compatible = "arm,cortex-a9-global-timer";
169 reg = <0x60000200 0x20>;
170 interrupts = <1 11 0x304>;
171 clocks = <&arm_timer_clk>;
172 };
173
174 timer@60000600 {
175 compatible = "arm,cortex-a9-twd-timer";
176 reg = <0x60000600 0x20>;
177 interrupts = <1 13 0x304>;
178 clocks = <&arm_timer_clk>;
179 };
180
181 intc: interrupt-controller@60001000 {
182 compatible = "arm,cortex-a9-gic";
183 #interrupt-cells = <3>;
184 interrupt-controller;
185 reg = <0x60001000 0x1000>,
186 <0x60000100 0x100>;
187 };
188
189 nand: nand@68000000 {
190 compatible = "denali,denali-nand-dt";
191 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
192 reg-names = "nand_data", "denali_reg";
193 };
194 };
195 };