arch/arm/dts/zynqmp-sck-kv-g-revB.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for KV260 revA Carrier Card
   4  *
   5  * (C) Copyright 2020 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  14
  15 /dts-v1/;
  16 /plugin/;
  17
  18 &{/} {
  19         compatible = "xlnx,zynqmp-sk-kv260-rev1",
  20                      "xlnx,zynqmp-sk-kv260-revB",
  21                      "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
  22         model = "ZynqMP KV260 revB";
  23 };
  24
  25 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
  26         #address-cells = <1>;
  27         #size-cells = <0>;
  28         pinctrl-names = "default", "gpio";
  29         pinctrl-0 = <&pinctrl_i2c1_default>;
  30         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  31         scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
  32         sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
  33
  34         u14: ina260@40 { /* u14 */
  35                 compatible = "ti,ina260";
  36                 #io-channel-cells = <1>;
  37                 label = "ina260-u14";
  38                 reg = <0x40>;
  39         };
  40         /* u43 - 0x2d - USB hub */
  41         /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
  42 };
  43
  44 &amba {
  45         ina260-u14 {
  46                 compatible = "iio-hwmon";
  47                 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
  48         };
  49
  50         si5332_0: si5332_0 { /* u17 */
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <125000000>;
  54         };
  55
  56         si5332_1: si5332_1 { /* u17 */
  57                 compatible = "fixed-clock";
  58                 #clock-cells = <0>;
  59                 clock-frequency = <25000000>;
  60         };
  61
  62         si5332_2: si5332_2 { /* u17 */
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <48000000>;
  66         };
  67
  68         si5332_3: si5332_3 { /* u17 */
  69                 compatible = "fixed-clock";
  70                 #clock-cells = <0>;
  71                 clock-frequency = <24000000>;
  72         };
  73
  74         si5332_4: si5332_4 { /* u17 */
  75                 compatible = "fixed-clock";
  76                 #clock-cells = <0>;
  77                 clock-frequency = <26000000>;
  78         };
  79
  80         si5332_5: si5332_5 { /* u17 */
  81                 compatible = "fixed-clock";
  82                 #clock-cells = <0>;
  83                 clock-frequency = <27000000>;
  84         };
  85 };
  86
  87 /* DP/USB 3.0 */
  88 &psgtr {
  89         status = "okay";
  90         /* pcie, usb3, sata */
  91         clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
  92         clock-names = "ref0", "ref1", "ref2";
  93 };
  94
  95 &zynqmp_dpsub {
  96         status = "okay";
  97         phy-names = "dp-phy0", "dp-phy1";
  98         phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
  99         assigned-clock-rates = <27000000>, <25000000>, <300000000>;
 100 };
 101
 102 &zynqmp_dpdma {
 103         status = "okay";
 104         assigned-clock-rates = <600000000>;
 105 };
 106
 107 &usb0 {
 108         status = "okay";
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_usb0_default>;
 111         phy-names = "usb3-phy";
 112         phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
 113         assigned-clock-rates = <250000000>, <20000000>;
 114
 115         usb5744: usb-hub { /* u43 */
 116                 status = "okay";
 117                 compatible = "microchip,usb5744";
 118                 i2c-bus = <&i2c1>;
 119                 reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 120         };
 121 };
 122
 123 &dwc3_0 {
 124         status = "okay";
 125         dr_mode = "host";
 126         snps,usb3_lpm_capable;
 127         maximum-speed = "super-speed";
 128 };
 129
 130 &sdhci1 { /* on CC with tuned parameters */
 131         status = "okay";
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_sdhci1_default>;
 134         /*
 135          * SD 3.0 requires level shifter and this property
 136          * should be removed if the board has level shifter and
 137          * need to work in UHS mode
 138          */
 139         no-1-8-v;
 140         disable-wp;
 141         xlnx,mio-bank = <1>;
 142         clk-phase-sd-hs = <126>, <60>;
 143         clk-phase-uhs-sdr25 = <120>, <60>;
 144         clk-phase-uhs-ddr50 = <126>, <48>;
 145         assigned-clock-rates = <187498123>;
 146         bus-width = <8>;
 147 };
 148
 149 &gem3 { /* required by spec */
 150         status = "okay";
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_gem3_default>;
 153         phy-handle = <&phy0>;
 154         phy-mode = "rgmii-id";
 155
 156         mdio: mdio {
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159
 160                 phy0: ethernet-phy@1 {
 161                         #phy-cells = <1>;
 162                         reg = <1>;
 163                         compatible = "ethernet-phy-id2000.a231";
 164                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 165                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 166                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 167                         ti,dp83867-rxctrl-strap-quirk;
 168                         reset-assert-us = <100>;
 169                         reset-deassert-us = <280>;
 170                         reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
 171                 };
 172         };
 173 };
 174
 175 &pinctrl0 { /* required by spec */
 176         status = "okay";
 177
 178         pinctrl_uart1_default: uart1-default {
 179                 conf {
 180                         groups = "uart1_9_grp";
 181                         slew-rate = <SLEW_RATE_SLOW>;
 182                         power-source = <IO_STANDARD_LVCMOS18>;
 183                         drive-strength = <12>;
 184                 };
 185
 186                 conf-rx {
 187                         pins = "MIO37";
 188                         bias-high-impedance;
 189                 };
 190
 191                 conf-tx {
 192                         pins = "MIO36";
 193                         bias-disable;
 194                 };
 195
 196                 mux {
 197                         groups = "uart1_9_grp";
 198                         function = "uart1";
 199                 };
 200         };
 201
 202         pinctrl_i2c1_default: i2c1-default {
 203                 conf {
 204                         groups = "i2c1_6_grp";
 205                         bias-pull-up;
 206                         slew-rate = <SLEW_RATE_SLOW>;
 207                         power-source = <IO_STANDARD_LVCMOS18>;
 208                 };
 209
 210                 mux {
 211                         groups = "i2c1_6_grp";
 212                         function = "i2c1";
 213                 };
 214         };
 215
 216         pinctrl_i2c1_gpio: i2c1-gpio {
 217                 conf {
 218                         groups = "gpio0_24_grp", "gpio0_25_grp";
 219                         slew-rate = <SLEW_RATE_SLOW>;
 220                         power-source = <IO_STANDARD_LVCMOS18>;
 221                 };
 222
 223                 mux {
 224                         groups = "gpio0_24_grp", "gpio0_25_grp";
 225                         function = "gpio0";
 226                 };
 227         };
 228
 229         pinctrl_gem3_default: gem3-default {
 230                 conf {
 231                         groups = "ethernet3_0_grp";
 232                         slew-rate = <SLEW_RATE_SLOW>;
 233                         power-source = <IO_STANDARD_LVCMOS18>;
 234                 };
 235
 236                 conf-rx {
 237                         pins = "MIO70", "MIO72", "MIO74";
 238                         bias-high-impedance;
 239                         low-power-disable;
 240                 };
 241
 242                 conf-bootstrap {
 243                         pins = "MIO71", "MIO73", "MIO75";
 244                         bias-disable;
 245                         low-power-disable;
 246                 };
 247
 248                 conf-tx {
 249                         pins = "MIO64", "MIO65", "MIO66",
 250                                 "MIO67", "MIO68", "MIO69";
 251                         bias-disable;
 252                         low-power-enable;
 253                 };
 254
 255                 conf-mdio {
 256                         groups = "mdio3_0_grp";
 257                         slew-rate = <SLEW_RATE_SLOW>;
 258                         power-source = <IO_STANDARD_LVCMOS18>;
 259                         bias-disable;
 260                 };
 261
 262                 mux-mdio {
 263                         function = "mdio3";
 264                         groups = "mdio3_0_grp";
 265                 };
 266
 267                 mux {
 268                         function = "ethernet3";
 269                         groups = "ethernet3_0_grp";
 270                 };
 271         };
 272
 273         pinctrl_usb0_default: usb0-default {
 274                 conf {
 275                         groups = "usb0_0_grp";
 276                         power-source = <IO_STANDARD_LVCMOS18>;
 277                 };
 278
 279                 conf-rx {
 280                         pins = "MIO52", "MIO53", "MIO55";
 281                         bias-high-impedance;
 282                         drive-strength = <12>;
 283                         slew-rate = <SLEW_RATE_FAST>;
 284                 };
 285
 286                 conf-tx {
 287                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 288                         "MIO60", "MIO61", "MIO62", "MIO63";
 289                         bias-disable;
 290                         drive-strength = <4>;
 291                         slew-rate = <SLEW_RATE_SLOW>;
 292                 };
 293
 294                 mux {
 295                         groups = "usb0_0_grp";
 296                         function = "usb0";
 297                 };
 298         };
 299
 300         pinctrl_sdhci1_default: sdhci1-default {
 301                 conf {
 302                         groups = "sdio1_0_grp";
 303                         slew-rate = <SLEW_RATE_SLOW>;
 304                         power-source = <IO_STANDARD_LVCMOS18>;
 305                         bias-disable;
 306                 };
 307
 308                 conf-cd {
 309                         groups = "sdio1_cd_0_grp";
 310                         bias-high-impedance;
 311                         bias-pull-up;
 312                         slew-rate = <SLEW_RATE_SLOW>;
 313                         power-source = <IO_STANDARD_LVCMOS18>;
 314                 };
 315
 316                 mux-cd {
 317                         groups = "sdio1_cd_0_grp";
 318                         function = "sdio1_cd";
 319                 };
 320
 321                 mux {
 322                         groups = "sdio1_0_grp";
 323                         function = "sdio1";
 324                 };
 325         };
 326 };
 327
 328 &uart1 {
 329         status = "okay";
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&pinctrl_uart1_default>;
 332 };