2 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
4 * (C) Copyright 2015 - 2016, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
17 model = "ZynqMP zc1751-xm018-dc4";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
55 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
130 phy-mode = "rgmii-id";
131 phy-handle = <ðernet_phy0>;
132 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
135 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
138 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
141 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
148 phy-mode = "rgmii-id";
149 phy-handle = <ðernet_phy7>;
154 phy-mode = "rgmii-id";
155 phy-handle = <ðernet_phy3>;
160 phy-mode = "rgmii-id";
161 phy-handle = <ðernet_phy8>;
173 clock-frequency = <400000>;
178 clock-frequency = <400000>;