arch/arm/imx-common/cpu.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <bootm.h>
  11 #include <common.h>
  12 #include <netdev.h>
  13 #include <asm/errno.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <imx_thermal.h>
  20 #include <ipu_pixfmt.h>
  21 #include <thermal.h>
  22 #include <sata.h>
  23
  24 #ifdef CONFIG_FSL_ESDHC
  25 #include <fsl_esdhc.h>
  26 #endif
  27
  28 #if defined(CONFIG_DISPLAY_CPUINFO)
  29 static u32 reset_cause = -1;
  30
  31 static char *get_reset_cause(void)
  32 {
  33         u32 cause;
  34         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  35
  36         cause = readl(&src_regs->srsr);
  37         writel(cause, &src_regs->srsr);
  38         reset_cause = cause;
  39
  40         switch (cause) {
  41         case 0x00001:
  42         case 0x00011:
  43                 return "POR";
  44         case 0x00004:
  45                 return "CSU";
  46         case 0x00008:
  47                 return "IPP USER";
  48         case 0x00010:
  49                 return "WDOG";
  50         case 0x00020:
  51                 return "JTAG HIGH-Z";
  52         case 0x00040:
  53                 return "JTAG SW";
  54         case 0x10000:
  55                 return "WARM BOOT";
  56         default:
  57                 return "unknown reset";
  58         }
  59 }
  60
  61 u32 get_imx_reset_cause(void)
  62 {
  63         return reset_cause;
  64 }
  65 #endif
  66
  67 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  68 #if defined(CONFIG_MX53)
  69 #define MEMCTL_BASE     ESDCTL_BASE_ADDR
  70 #else
  71 #define MEMCTL_BASE     MMDC_P0_BASE_ADDR
  72 #endif
  73 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
  74 static const unsigned char bank_lookup[] = {3, 2};
  75
  76 /* these MMDC registers are common to the IMX53 and IMX6 */
  77 struct esd_mmdc_regs {
  78         uint32_t        ctl;
  79         uint32_t        pdc;
  80         uint32_t        otc;
  81         uint32_t        cfg0;
  82         uint32_t        cfg1;
  83         uint32_t        cfg2;
  84         uint32_t        misc;
  85 };
  86
  87 #define ESD_MMDC_CTL_GET_ROW(mdctl)     ((ctl >> 24) & 7)
  88 #define ESD_MMDC_CTL_GET_COLUMN(mdctl)  ((ctl >> 20) & 7)
  89 #define ESD_MMDC_CTL_GET_WIDTH(mdctl)   ((ctl >> 16) & 3)
  90 #define ESD_MMDC_CTL_GET_CS1(mdctl)     ((ctl >> 30) & 1)
  91 #define ESD_MMDC_MISC_GET_BANK(mdmisc)  ((misc >> 5) & 1)
  92
  93 /*
  94  * imx_ddr_size - return size in bytes of DRAM according MMDC config
  95  * The MMDC MDCTL register holds the number of bits for row, col, and data
  96  * width and the MMDC MDMISC register holds the number of banks. Combine
  97  * all these bits to determine the meme size the MMDC has been configured for
  98  */
  99 unsigned imx_ddr_size(void)
 100 {
 101         struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
 102         unsigned ctl = readl(&mem->ctl);
 103         unsigned misc = readl(&mem->misc);
 104         int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
 105
 106         bits += ESD_MMDC_CTL_GET_ROW(ctl);
 107         bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
 108         bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
 109         bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
 110         bits += ESD_MMDC_CTL_GET_CS1(ctl);
 111
 112         /* The MX6 can do only 3840 MiB of DRAM */
 113         if (bits == 32)
 114                 return 0xf0000000;
 115
 116         return 1 << bits;
 117 }
 118 #endif
 119
 120 #if defined(CONFIG_DISPLAY_CPUINFO)
 121
 122 const char *get_imx_type(u32 imxtype)
 123 {
 124         switch (imxtype) {
 125         case MXC_CPU_MX6Q:
 126                 return "6Q";    /* Quad-core version of the mx6 */
 127         case MXC_CPU_MX6D:
 128                 return "6D";    /* Dual-core version of the mx6 */
 129         case MXC_CPU_MX6DL:
 130                 return "6DL";   /* Dual Lite version of the mx6 */
 131         case MXC_CPU_MX6SOLO:
 132                 return "6SOLO"; /* Solo version of the mx6 */
 133         case MXC_CPU_MX6SL:
 134                 return "6SL";   /* Solo-Lite version of the mx6 */
 135         case MXC_CPU_MX6SX:
 136                 return "6SX";   /* SoloX version of the mx6 */
 137         case MXC_CPU_MX51:
 138                 return "51";
 139         case MXC_CPU_MX53:
 140                 return "53";
 141         default:
 142                 return "??";
 143         }
 144 }
 145
 146 int print_cpuinfo(void)
 147 {
 148         u32 cpurev, max_freq;
 149
 150 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
 151         struct udevice *thermal_dev;
 152         int cpu_tmp, minc, maxc, ret;
 153 #endif
 154
 155         cpurev = get_cpu_rev();
 156
 157 #if defined(CONFIG_MX6)
 158         printf("CPU:   Freescale i.MX%s rev%d.%d",
 159                get_imx_type((cpurev & 0xFF000) >> 12),
 160                (cpurev & 0x000F0) >> 4,
 161                (cpurev & 0x0000F) >> 0);
 162         max_freq = get_cpu_speed_grade_hz();
 163         if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
 164                 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
 165         } else {
 166                 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
 167                        mxc_get_clock(MXC_ARM_CLK) / 1000000);
 168         }
 169 #else
 170         printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
 171                 get_imx_type((cpurev & 0xFF000) >> 12),
 172                 (cpurev & 0x000F0) >> 4,
 173                 (cpurev & 0x0000F) >> 0,
 174                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 175 #endif
 176
 177 #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
 178         puts("CPU:   ");
 179         switch (get_cpu_temp_grade(&minc, &maxc)) {
 180         case TEMP_AUTOMOTIVE:
 181                 puts("Automotive temperature grade ");
 182                 break;
 183         case TEMP_INDUSTRIAL:
 184                 puts("Industrial temperature grade ");
 185                 break;
 186         case TEMP_EXTCOMMERCIAL:
 187                 puts("Extended Commercial temperature grade ");
 188                 break;
 189         default:
 190                 puts("Commercial temperature grade ");
 191                 break;
 192         }
 193         printf("(%dC to %dC)", minc, maxc);
 194         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 195         if (!ret) {
 196                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 197
 198                 if (!ret)
 199                         printf(" at %dC\n", cpu_tmp);
 200                 else
 201                         puts(" - invalid sensor data\n");
 202         } else {
 203                 puts(" - invalid sensor device\n");
 204         }
 205 #endif
 206
 207         printf("Reset cause: %s\n", get_reset_cause());
 208         return 0;
 209 }
 210 #endif
 211
 212 int cpu_eth_init(bd_t *bis)
 213 {
 214         int rc = -ENODEV;
 215
 216 #if defined(CONFIG_FEC_MXC)
 217         rc = fecmxc_initialize(bis);
 218 #endif
 219
 220         return rc;
 221 }
 222
 223 #ifdef CONFIG_FSL_ESDHC
 224 /*
 225  * Initializes on-chip MMC controllers.
 226  * to override, implement board_mmc_init()
 227  */
 228 int cpu_mmc_init(bd_t *bis)
 229 {
 230         return fsl_esdhc_mmc_init(bis);
 231 }
 232 #endif
 233
 234 u32 get_ahb_clk(void)
 235 {
 236         struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 237         u32 reg, ahb_podf;
 238
 239         reg = __raw_readl(&imx_ccm->cbcdr);
 240         reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
 241         ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 242
 243         return get_periph_clk() / (ahb_podf + 1);
 244 }
 245
 246 void arch_preboot_os(void)
 247 {
 248 #if defined(CONFIG_CMD_SATA)
 249         sata_stop();
 250 #if defined(CONFIG_MX6)
 251         disable_sata_clock();
 252 #endif
 253 #endif
 254 #if defined(CONFIG_VIDEO_IPUV3)
 255         /* disable video before launching O/S */
 256         ipuv3_fb_shutdown();
 257 #endif
 258 }
 259
 260 void set_chipselect_size(int const cs_size)
 261 {
 262         unsigned int reg;
 263         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 264         reg = readl(&iomuxc_regs->gpr[1]);
 265
 266         switch (cs_size) {
 267         case CS0_128:
 268                 reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
 269                 reg |= 0x5;
 270                 break;
 271         case CS0_64M_CS1_64M:
 272                 reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
 273                 reg |= 0x1B;
 274                 break;
 275         case CS0_64M_CS1_32M_CS2_32M:
 276                 reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
 277                 reg |= 0x4B;
 278                 break;
 279         case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
 280                 reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
 281                 reg |= 0x249;
 282                 break;
 283         default:
 284                 printf("Unknown chip select size: %d\n", cs_size);
 285                 break;
 286         }
 287
 288         writel(reg, &iomuxc_regs->gpr[1]);
 289 }