arch/arm/imx-common/cpu.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/errno.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/arch/crm_regs.h>
  33 #include <ipu_pixfmt.h>
  34
  35 #ifdef CONFIG_FSL_ESDHC
  36 #include <fsl_esdhc.h>
  37 #endif
  38
  39 char *get_reset_cause(void)
  40 {
  41         u32 cause;
  42         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  43
  44         cause = readl(&src_regs->srsr);
  45         writel(cause, &src_regs->srsr);
  46
  47         switch (cause) {
  48         case 0x00001:
  49         case 0x00011:
  50                 return "POR";
  51         case 0x00004:
  52                 return "CSU";
  53         case 0x00008:
  54                 return "IPP USER";
  55         case 0x00010:
  56                 return "WDOG";
  57         case 0x00020:
  58                 return "JTAG HIGH-Z";
  59         case 0x00040:
  60                 return "JTAG SW";
  61         case 0x10000:
  62                 return "WARM BOOT";
  63         default:
  64                 return "unknown reset";
  65         }
  66 }
  67
  68 #if defined(CONFIG_DISPLAY_CPUINFO)
  69
  70 static const char *get_imx_type(u32 imxtype)
  71 {
  72         switch (imxtype) {
  73         case 0x63:
  74                 return "6Q";    /* Quad-core version of the mx6 */
  75         case 0x61:
  76                 return "6DS";   /* Dual/Solo version of the mx6 */
  77         case 0x60:
  78                 return "6SL";   /* Solo-Lite version of the mx6 */
  79         case 0x51:
  80                 return "51";
  81         case 0x53:
  82                 return "53";
  83         default:
  84                 return "??";
  85         }
  86 }
  87
  88 int print_cpuinfo(void)
  89 {
  90         u32 cpurev;
  91
  92         cpurev = get_cpu_rev();
  93
  94         printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
  95                 get_imx_type((cpurev & 0xFF000) >> 12),
  96                 (cpurev & 0x000F0) >> 4,
  97                 (cpurev & 0x0000F) >> 0,
  98                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
  99         printf("Reset cause: %s\n", get_reset_cause());
 100         return 0;
 101 }
 102 #endif
 103
 104 int cpu_eth_init(bd_t *bis)
 105 {
 106         int rc = -ENODEV;
 107
 108 #if defined(CONFIG_FEC_MXC)
 109         rc = fecmxc_initialize(bis);
 110 #endif
 111
 112         return rc;
 113 }
 114
 115 #ifdef CONFIG_FSL_ESDHC
 116 /*
 117  * Initializes on-chip MMC controllers.
 118  * to override, implement board_mmc_init()
 119  */
 120 int cpu_mmc_init(bd_t *bis)
 121 {
 122         return fsl_esdhc_mmc_init(bis);
 123 }
 124 #endif
 125
 126 void reset_cpu(ulong addr)
 127 {
 128         __raw_writew(4, WDOG1_BASE_ADDR);
 129 }
 130
 131 u32 get_ahb_clk(void)
 132 {
 133         struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 134         u32 reg, ahb_podf;
 135
 136         reg = __raw_readl(&imx_ccm->cbcdr);
 137         reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
 138         ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 139
 140         return get_periph_clk() / (ahb_podf + 1);
 141 }
 142
 143 #if defined(CONFIG_VIDEO_IPUV3)
 144 void arch_preboot_os(void)
 145 {
 146         /* disable video before launching O/S */
 147         ipuv3_fb_shutdown();
 148 }
 149 #endif