3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
28 #if defined(CONFIG_DISPLAY_CPUINFO)
29 static u32 reset_cause
= -1;
31 static char *get_reset_cause(void)
34 struct src
*src_regs
= (struct src
*)SRC_BASE_ADDR
;
36 cause
= readl(&src_regs
->srsr
);
37 writel(cause
, &src_regs
->srsr
);
72 return "unknown reset";
76 u32
get_imx_reset_cause(void)
82 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
83 #if defined(CONFIG_MX53)
84 #define MEMCTL_BASE ESDCTL_BASE_ADDR
86 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
88 static const unsigned char col_lookup
[] = {9, 10, 11, 8, 12, 9, 9, 9};
89 static const unsigned char bank_lookup
[] = {3, 2};
91 /* these MMDC registers are common to the IMX53 and IMX6 */
92 struct esd_mmdc_regs
{
102 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
103 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
104 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
105 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
106 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
109 * imx_ddr_size - return size in bytes of DRAM according MMDC config
110 * The MMDC MDCTL register holds the number of bits for row, col, and data
111 * width and the MMDC MDMISC register holds the number of banks. Combine
112 * all these bits to determine the meme size the MMDC has been configured for
114 unsigned imx_ddr_size(void)
116 struct esd_mmdc_regs
*mem
= (struct esd_mmdc_regs
*)MEMCTL_BASE
;
117 unsigned ctl
= readl(&mem
->ctl
);
118 unsigned misc
= readl(&mem
->misc
);
119 int bits
= 11 + 0 + 0 + 1; /* row + col + bank + width */
121 bits
+= ESD_MMDC_CTL_GET_ROW(ctl
);
122 bits
+= col_lookup
[ESD_MMDC_CTL_GET_COLUMN(ctl
)];
123 bits
+= bank_lookup
[ESD_MMDC_MISC_GET_BANK(misc
)];
124 bits
+= ESD_MMDC_CTL_GET_WIDTH(ctl
);
125 bits
+= ESD_MMDC_CTL_GET_CS1(ctl
);
127 /* The MX6 can do only 3840 MiB of DRAM */
135 #if defined(CONFIG_DISPLAY_CPUINFO)
137 const char *get_imx_type(u32 imxtype
)
141 return "7S"; /* Single-core version of the mx7 */
143 return "7D"; /* Dual-core version of the mx7 */
145 return "6QP"; /* Quad-Plus version of the mx6 */
147 return "6DP"; /* Dual-Plus version of the mx6 */
149 return "6Q"; /* Quad-core version of the mx6 */
151 return "6D"; /* Dual-core version of the mx6 */
153 return "6DL"; /* Dual Lite version of the mx6 */
154 case MXC_CPU_MX6SOLO
:
155 return "6SOLO"; /* Solo version of the mx6 */
157 return "6SL"; /* Solo-Lite version of the mx6 */
159 return "6SX"; /* SoloX version of the mx6 */
161 return "6UL"; /* Ultra-Lite version of the mx6 */
171 int print_cpuinfo(void)
174 __maybe_unused u32 max_freq
;
176 cpurev
= get_cpu_rev();
178 #if defined(CONFIG_IMX_THERMAL)
179 struct udevice
*thermal_dev
;
180 int cpu_tmp
, minc
, maxc
, ret
;
182 printf("CPU: Freescale i.MX%s rev%d.%d",
183 get_imx_type((cpurev
& 0xFF000) >> 12),
184 (cpurev
& 0x000F0) >> 4,
185 (cpurev
& 0x0000F) >> 0);
186 max_freq
= get_cpu_speed_grade_hz();
187 if (!max_freq
|| max_freq
== mxc_get_clock(MXC_ARM_CLK
)) {
188 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK
) / 1000000);
190 printf(" %d MHz (running at %d MHz)\n", max_freq
/ 1000000,
191 mxc_get_clock(MXC_ARM_CLK
) / 1000000);
194 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
195 get_imx_type((cpurev
& 0xFF000) >> 12),
196 (cpurev
& 0x000F0) >> 4,
197 (cpurev
& 0x0000F) >> 0,
198 mxc_get_clock(MXC_ARM_CLK
) / 1000000);
201 #if defined(CONFIG_IMX_THERMAL)
203 switch (get_cpu_temp_grade(&minc
, &maxc
)) {
204 case TEMP_AUTOMOTIVE
:
205 puts("Automotive temperature grade ");
207 case TEMP_INDUSTRIAL
:
208 puts("Industrial temperature grade ");
210 case TEMP_EXTCOMMERCIAL
:
211 puts("Extended Commercial temperature grade ");
214 puts("Commercial temperature grade ");
217 printf("(%dC to %dC)", minc
, maxc
);
218 ret
= uclass_get_device(UCLASS_THERMAL
, 0, &thermal_dev
);
220 ret
= thermal_get_temp(thermal_dev
, &cpu_tmp
);
223 printf(" at %dC\n", cpu_tmp
);
225 debug(" - invalid sensor data\n");
227 debug(" - invalid sensor device\n");
231 printf("Reset cause: %s\n", get_reset_cause());
236 int cpu_eth_init(bd_t
*bis
)
240 #if defined(CONFIG_FEC_MXC)
241 rc
= fecmxc_initialize(bis
);
247 #ifdef CONFIG_FSL_ESDHC
249 * Initializes on-chip MMC controllers.
250 * to override, implement board_mmc_init()
252 int cpu_mmc_init(bd_t
*bis
)
254 return fsl_esdhc_mmc_init(bis
);
259 u32
get_ahb_clk(void)
261 struct mxc_ccm_reg
*imx_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
264 reg
= __raw_readl(&imx_ccm
->cbcdr
);
265 reg
&= MXC_CCM_CBCDR_AHB_PODF_MASK
;
266 ahb_podf
= reg
>> MXC_CCM_CBCDR_AHB_PODF_OFFSET
;
268 return get_periph_clk() / (ahb_podf
+ 1);
272 void arch_preboot_os(void)
274 #if defined(CONFIG_CMD_SATA)
276 #if defined(CONFIG_MX6)
277 disable_sata_clock();
280 #if defined(CONFIG_VIDEO_IPUV3)
281 /* disable video before launching O/S */
284 #if defined(CONFIG_VIDEO_MXS)
289 void set_chipselect_size(int const cs_size
)
292 struct iomuxc
*iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
293 reg
= readl(&iomuxc_regs
->gpr
[1]);
297 reg
&= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
300 case CS0_64M_CS1_64M
:
301 reg
&= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
304 case CS0_64M_CS1_32M_CS2_32M
:
305 reg
&= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
308 case CS0_32M_CS1_32M_CS2_32M_CS3_32M
:
309 reg
&= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
313 printf("Unknown chip select size: %d\n", cs_size
);
317 writel(reg
, &iomuxc_regs
->gpr
[1]);