arch/arm/include/asm/arch-am33xx/clock.h

   1 /*
   2  * clock.h
   3  *
   4  * clock header
   5  *
   6  * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _CLOCKS_H_
  12 #define _CLOCKS_H_
  13
  14 #include <asm/arch/clocks_am33xx.h>
  15 #include <asm/arch/hardware.h>
  16
  17 #if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
  18 #include <asm/arch/clock_ti81xx.h>
  19 #endif
  20
  21 #define LDELAY 1000000
  22
  23 /*CM_<clock_domain>__CLKCTRL */
  24 #define CD_CLKCTRL_CLKTRCTRL_SHIFT              0
  25 #define CD_CLKCTRL_CLKTRCTRL_MASK               3
  26
  27 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP           0
  28 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP           1
  29 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP            2
  30
  31 /* CM_<clock_domain>_<module>_CLKCTRL */
  32 #define MODULE_CLKCTRL_MODULEMODE_SHIFT         0
  33 #define MODULE_CLKCTRL_MODULEMODE_MASK          3
  34 #define MODULE_CLKCTRL_IDLEST_SHIFT             16
  35 #define MODULE_CLKCTRL_IDLEST_MASK              (3 << 16)
  36
  37 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE            0
  38 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN        2
  39
  40 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL  0
  41 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING     1
  42 #define MODULE_CLKCTRL_IDLEST_IDLE              2
  43 #define MODULE_CLKCTRL_IDLEST_DISABLED          3
  44
  45 /* CM_CLKMODE_DPLL */
  46 #define CM_CLKMODE_DPLL_SSC_EN_SHIFT            12
  47 #define CM_CLKMODE_DPLL_SSC_EN_MASK             (1 << 12)
  48 #define CM_CLKMODE_DPLL_SSC_ACK_MASK            (1 << 13)
  49 #define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK     (1 << 14)
  50 #define CM_CLKMODE_DPLL_SSC_TYPE_MASK           (1 << 15)
  51 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT          11
  52 #define CM_CLKMODE_DPLL_REGM4XEN_MASK           (1 << 11)
  53 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT         10
  54 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK          (1 << 10)
  55 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT    9
  56 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK     (1 << 9)
  57 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT     8
  58 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK      (1 << 8)
  59 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT         5
  60 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK          (0x7 << 5)
  61 #define CM_CLKMODE_DPLL_EN_SHIFT                0
  62 #define CM_CLKMODE_DPLL_EN_MASK                 (0x7 << 0)
  63
  64 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT           0
  65 #define CM_CLKMODE_DPLL_DPLL_EN_MASK            7
  66
  67 #define DPLL_EN_STOP                    1
  68 #define DPLL_EN_MN_BYPASS               4
  69 #define DPLL_EN_LOW_POWER_BYPASS        5
  70 #define DPLL_EN_LOCK                    7
  71
  72 /* CM_IDLEST_DPLL fields */
  73 #define ST_DPLL_CLK_MASK                1
  74
  75 /* CM_CLKSEL_DPLL */
  76 #define CM_CLKSEL_DPLL_M_SHIFT                  8
  77 #define CM_CLKSEL_DPLL_M_MASK                   (0x7FF << 8)
  78 #define CM_CLKSEL_DPLL_N_SHIFT                  0
  79 #define CM_CLKSEL_DPLL_N_MASK                   0x7F
  80
  81 struct dpll_params {
  82         u32 m;
  83         u32 n;
  84         s8 m2;
  85         s8 m3;
  86         s8 m4;
  87         s8 m5;
  88         s8 m6;
  89 };
  90
  91 struct dpll_regs {
  92         u32 cm_clkmode_dpll;
  93         u32 cm_idlest_dpll;
  94         u32 cm_autoidle_dpll;
  95         u32 cm_clksel_dpll;
  96         u32 cm_div_m2_dpll;
  97         u32 cm_div_m3_dpll;
  98         u32 cm_div_m4_dpll;
  99         u32 cm_div_m5_dpll;
 100         u32 cm_div_m6_dpll;
 101 };
 102
 103 extern const struct dpll_regs dpll_mpu_regs;
 104 extern const struct dpll_regs dpll_core_regs;
 105 extern const struct dpll_regs dpll_per_regs;
 106 extern const struct dpll_regs dpll_ddr_regs;
 107 extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
 108 extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
 109 extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
 110 extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
 111 extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
 112 extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
 113
 114 extern struct cm_wkuppll *const cmwkup;
 115
 116 const struct dpll_params *get_dpll_mpu_params(void);
 117 const struct dpll_params *get_dpll_core_params(void);
 118 const struct dpll_params *get_dpll_per_params(void);
 119 const struct dpll_params *get_dpll_ddr_params(void);
 120 void scale_vcores(void);
 121 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 122 void prcm_init(void);
 123 void enable_basic_clocks(void);
 124 void do_enable_clocks(u32 *const *, u32 *const *, u8);
 125 void do_disable_clocks(u32 *const *, u32 *const *, u8);
 126
 127 void set_mpu_spreadspectrum(int permille);
 128 #endif