arch/arm/include/asm/arch-am33xx/ddr_defs.h

   1 /*
   2  * ddr_defs.h
   3  *
   4  * ddr specific header
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #ifndef _DDR_DEFS_H
  20 #define _DDR_DEFS_H
  21
  22 #include <asm/arch/hardware.h>
  23 #include <asm/emif.h>
  24
  25 /* AM335X EMIF Register values */
  26 #define VTP_CTRL_READY          (0x1 << 5)
  27 #define VTP_CTRL_ENABLE         (0x1 << 6)
  28 #define VTP_CTRL_START_EN       (0x1)
  29 #define PHY_DLL_LOCK_DIFF       0x0
  30 #define DDR_CKE_CTRL_NORMAL     0x1
  31 #define PHY_EN_DYN_PWRDN        (0x1 << 20)
  32
  33 /* Micron MT47H128M16RT-25E */
  34 #define MT47H128M16RT25E_EMIF_READ_LATENCY      0x100005
  35 #define MT47H128M16RT25E_EMIF_TIM1              0x0666B3C9
  36 #define MT47H128M16RT25E_EMIF_TIM2              0x243631CA
  37 #define MT47H128M16RT25E_EMIF_TIM3              0x0000033F
  38 #define MT47H128M16RT25E_EMIF_SDCFG             0x41805332
  39 #define MT47H128M16RT25E_EMIF_SDREF             0x0000081a
  40 #define MT47H128M16RT25E_DLL_LOCK_DIFF          0x0
  41 #define MT47H128M16RT25E_RATIO                  0x80
  42 #define MT47H128M16RT25E_INVERT_CLKOUT          0x00
  43 #define MT47H128M16RT25E_RD_DQS                 0x12
  44 #define MT47H128M16RT25E_WR_DQS                 0x00
  45 #define MT47H128M16RT25E_PHY_WRLVL              0x00
  46 #define MT47H128M16RT25E_PHY_GATELVL            0x00
  47 #define MT47H128M16RT25E_PHY_WR_DATA            0x40
  48 #define MT47H128M16RT25E_PHY_FIFO_WE            0x80
  49 #define MT47H128M16RT25E_PHY_RANK0_DELAY                0x1
  50 #define MT47H128M16RT25E_IOCTRL_VALUE           0x18B
  51
  52 /* Micron MT41J128M16JT-125 */
  53 #define MT41J128MJT125_EMIF_READ_LATENCY        0x06
  54 #define MT41J128MJT125_EMIF_TIM1                0x0888A39B
  55 #define MT41J128MJT125_EMIF_TIM2                0x26337FDA
  56 #define MT41J128MJT125_EMIF_TIM3                0x501F830F
  57 #define MT41J128MJT125_EMIF_SDCFG               0x61C04AB2
  58 #define MT41J128MJT125_EMIF_SDREF               0x0000093B
  59 #define MT41J128MJT125_ZQ_CFG                   0x50074BE4
  60 #define MT41J128MJT125_DLL_LOCK_DIFF            0x1
  61 #define MT41J128MJT125_RATIO                    0x40
  62 #define MT41J128MJT125_INVERT_CLKOUT            0x1
  63 #define MT41J128MJT125_RD_DQS                   0x3B
  64 #define MT41J128MJT125_WR_DQS                   0x85
  65 #define MT41J128MJT125_PHY_WR_DATA              0xC1
  66 #define MT41J128MJT125_PHY_FIFO_WE              0x100
  67 #define MT41J128MJT125_IOCTRL_VALUE             0x18B
  68
  69 /* Micron MT41J256M8HX-15E */
  70 #define MT41J256M8HX15E_EMIF_READ_LATENCY       0x06
  71 #define MT41J256M8HX15E_EMIF_TIM1               0x0888A39B
  72 #define MT41J256M8HX15E_EMIF_TIM2               0x26337FDA
  73 #define MT41J256M8HX15E_EMIF_TIM3               0x501F830F
  74 #define MT41J256M8HX15E_EMIF_SDCFG              0x61C04B32
  75 #define MT41J256M8HX15E_EMIF_SDREF              0x0000093B
  76 #define MT41J256M8HX15E_ZQ_CFG                  0x50074BE4
  77 #define MT41J256M8HX15E_DLL_LOCK_DIFF           0x1
  78 #define MT41J256M8HX15E_RATIO                   0x40
  79 #define MT41J256M8HX15E_INVERT_CLKOUT           0x1
  80 #define MT41J256M8HX15E_RD_DQS                  0x3B
  81 #define MT41J256M8HX15E_WR_DQS                  0x85
  82 #define MT41J256M8HX15E_PHY_WR_DATA             0xC1
  83 #define MT41J256M8HX15E_PHY_FIFO_WE             0x100
  84 #define MT41J256M8HX15E_IOCTRL_VALUE            0x18B
  85
  86 /* Micron MT41J512M8RH-125 on EVM v1.5 */
  87 #define MT41J512M8RH125_EMIF_READ_LATENCY       0x06
  88 #define MT41J512M8RH125_EMIF_TIM1               0x0888A39B
  89 #define MT41J512M8RH125_EMIF_TIM2               0x26517FDA
  90 #define MT41J512M8RH125_EMIF_TIM3               0x501F84EF
  91 #define MT41J512M8RH125_EMIF_SDCFG              0x61C04BB2
  92 #define MT41J512M8RH125_EMIF_SDREF              0x0000093B
  93 #define MT41J512M8RH125_ZQ_CFG                  0x50074BE4
  94 #define MT41J512M8RH125_DLL_LOCK_DIFF           0x1
  95 #define MT41J512M8RH125_RATIO                   0x80
  96 #define MT41J512M8RH125_INVERT_CLKOUT           0x0
  97 #define MT41J512M8RH125_RD_DQS                  0x3B
  98 #define MT41J512M8RH125_WR_DQS                  0x3C
  99 #define MT41J512M8RH125_PHY_FIFO_WE             0xA5
 100 #define MT41J512M8RH125_PHY_WR_DATA             0x74
 101 #define MT41J512M8RH125_IOCTRL_VALUE            0x18B
 102
 103 /**
 104  * Configure DMM
 105  */
 106 void config_dmm(const struct dmm_lisa_map_regs *regs);
 107
 108 /**
 109  * Configure SDRAM
 110  */
 111 void config_sdram(const struct emif_regs *regs, int nr);
 112
 113 /**
 114  * Set SDRAM timings
 115  */
 116 void set_sdram_timings(const struct emif_regs *regs, int nr);
 117
 118 /**
 119  * Configure DDR PHY
 120  */
 121 void config_ddr_phy(const struct emif_regs *regs, int nr);
 122
 123 struct ddr_cmd_regs {
 124         unsigned int resv0[7];
 125         unsigned int cm0csratio;        /* offset 0x01C */
 126         unsigned int resv1[2];
 127         unsigned int cm0dldiff;         /* offset 0x028 */
 128         unsigned int cm0iclkout;        /* offset 0x02C */
 129         unsigned int resv2[8];
 130         unsigned int cm1csratio;        /* offset 0x050 */
 131         unsigned int resv3[2];
 132         unsigned int cm1dldiff;         /* offset 0x05C */
 133         unsigned int cm1iclkout;        /* offset 0x060 */
 134         unsigned int resv4[8];
 135         unsigned int cm2csratio;        /* offset 0x084 */
 136         unsigned int resv5[2];
 137         unsigned int cm2dldiff;         /* offset 0x090 */
 138         unsigned int cm2iclkout;        /* offset 0x094 */
 139         unsigned int resv6[3];
 140 };
 141
 142 struct ddr_data_regs {
 143         unsigned int dt0rdsratio0;      /* offset 0x0C8 */
 144         unsigned int resv1[4];
 145         unsigned int dt0wdsratio0;      /* offset 0x0DC */
 146         unsigned int resv2[4];
 147         unsigned int dt0wiratio0;       /* offset 0x0F0 */
 148         unsigned int resv3;
 149         unsigned int dt0wimode0;        /* offset 0x0F8 */
 150         unsigned int dt0giratio0;       /* offset 0x0FC */
 151         unsigned int resv4;
 152         unsigned int dt0gimode0;        /* offset 0x104 */
 153         unsigned int dt0fwsratio0;      /* offset 0x108 */
 154         unsigned int resv5[4];
 155         unsigned int dt0dqoffset;       /* offset 0x11C */
 156         unsigned int dt0wrsratio0;      /* offset 0x120 */
 157         unsigned int resv6[4];
 158         unsigned int dt0rdelays0;       /* offset 0x134 */
 159         unsigned int dt0dldiff0;        /* offset 0x138 */
 160         unsigned int resv7[12];
 161 };
 162
 163 /**
 164  * This structure represents the DDR registers on AM33XX devices.
 165  * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
 166  * correspond to DATA1 registers defined here.
 167  */
 168 struct ddr_regs {
 169         unsigned int resv0[7];
 170         unsigned int cm0csratio;        /* offset 0x01C */
 171         unsigned int resv1[2];
 172         unsigned int cm0dldiff;         /* offset 0x028 */
 173         unsigned int cm0iclkout;        /* offset 0x02C */
 174         unsigned int resv2[8];
 175         unsigned int cm1csratio;        /* offset 0x050 */
 176         unsigned int resv3[2];
 177         unsigned int cm1dldiff;         /* offset 0x05C */
 178         unsigned int cm1iclkout;        /* offset 0x060 */
 179         unsigned int resv4[8];
 180         unsigned int cm2csratio;        /* offset 0x084 */
 181         unsigned int resv5[2];
 182         unsigned int cm2dldiff;         /* offset 0x090 */
 183         unsigned int cm2iclkout;        /* offset 0x094 */
 184         unsigned int resv6[12];
 185         unsigned int dt0rdsratio0;      /* offset 0x0C8 */
 186         unsigned int resv7[4];
 187         unsigned int dt0wdsratio0;      /* offset 0x0DC */
 188         unsigned int resv8[4];
 189         unsigned int dt0wiratio0;       /* offset 0x0F0 */
 190         unsigned int resv9;
 191         unsigned int dt0wimode0;        /* offset 0x0F8 */
 192         unsigned int dt0giratio0;       /* offset 0x0FC */
 193         unsigned int resv10;
 194         unsigned int dt0gimode0;        /* offset 0x104 */
 195         unsigned int dt0fwsratio0;      /* offset 0x108 */
 196         unsigned int resv11[4];
 197         unsigned int dt0dqoffset;       /* offset 0x11C */
 198         unsigned int dt0wrsratio0;      /* offset 0x120 */
 199         unsigned int resv12[4];
 200         unsigned int dt0rdelays0;       /* offset 0x134 */
 201         unsigned int dt0dldiff0;        /* offset 0x138 */
 202 };
 203
 204 /**
 205  * Encapsulates DDR CMD control registers.
 206  */
 207 struct cmd_control {
 208         unsigned long cmd0csratio;
 209         unsigned long cmd0csforce;
 210         unsigned long cmd0csdelay;
 211         unsigned long cmd0dldiff;
 212         unsigned long cmd0iclkout;
 213         unsigned long cmd1csratio;
 214         unsigned long cmd1csforce;
 215         unsigned long cmd1csdelay;
 216         unsigned long cmd1dldiff;
 217         unsigned long cmd1iclkout;
 218         unsigned long cmd2csratio;
 219         unsigned long cmd2csforce;
 220         unsigned long cmd2csdelay;
 221         unsigned long cmd2dldiff;
 222         unsigned long cmd2iclkout;
 223 };
 224
 225 /**
 226  * Encapsulates DDR DATA registers.
 227  */
 228 struct ddr_data {
 229         unsigned long datardsratio0;
 230         unsigned long datawdsratio0;
 231         unsigned long datawiratio0;
 232         unsigned long datagiratio0;
 233         unsigned long datafwsratio0;
 234         unsigned long datawrsratio0;
 235         unsigned long datauserank0delay;
 236         unsigned long datadldiff0;
 237 };
 238
 239 /**
 240  * Configure DDR CMD control registers
 241  */
 242 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
 243
 244 /**
 245  * Configure DDR DATA registers
 246  */
 247 void config_ddr_data(const struct ddr_data *data, int nr);
 248
 249 /**
 250  * This structure represents the DDR io control on AM33XX devices.
 251  */
 252 struct ddr_cmdtctrl {
 253         unsigned int resv1[1];
 254         unsigned int cm0ioctl;
 255         unsigned int cm1ioctl;
 256         unsigned int cm2ioctl;
 257         unsigned int resv2[12];
 258         unsigned int dt0ioctl;
 259         unsigned int dt1ioctl;
 260 };
 261
 262 /**
 263  * Configure DDR io control registers
 264  */
 265 void config_io_ctrl(unsigned long val);
 266
 267 struct ddr_ctrl {
 268         unsigned int ddrioctrl;
 269         unsigned int resv1[325];
 270         unsigned int ddrckectrl;
 271 };
 272
 273 void config_ddr(unsigned int pll, unsigned int ioctrl,
 274                 const struct ddr_data *data, const struct cmd_control *ctrl,
 275                 const struct emif_regs *regs, int nr);
 276
 277 #endif  /* _DDR_DEFS_H */