arch/arm/include/asm/arch-exynos/clock.h

   1 /*
   2  * (C) Copyright 2010 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __ASM_ARM_ARCH_CLOCK_H_
   9 #define __ASM_ARM_ARCH_CLOCK_H_
  10
  11 #ifndef __ASSEMBLY__
  12 struct exynos4_clock {
  13         unsigned char   res1[0x4200];
  14         unsigned int    src_leftbus;
  15         unsigned char   res2[0x1fc];
  16         unsigned int    mux_stat_leftbus;
  17         unsigned char   res4[0xfc];
  18         unsigned int    div_leftbus;
  19         unsigned char   res5[0xfc];
  20         unsigned int    div_stat_leftbus;
  21         unsigned char   res6[0x1fc];
  22         unsigned int    gate_ip_leftbus;
  23         unsigned char   res7[0x1fc];
  24         unsigned int    clkout_leftbus;
  25         unsigned int    clkout_leftbus_div_stat;
  26         unsigned char   res8[0x37f8];
  27         unsigned int    src_rightbus;
  28         unsigned char   res9[0x1fc];
  29         unsigned int    mux_stat_rightbus;
  30         unsigned char   res10[0xfc];
  31         unsigned int    div_rightbus;
  32         unsigned char   res11[0xfc];
  33         unsigned int    div_stat_rightbus;
  34         unsigned char   res12[0x1fc];
  35         unsigned int    gate_ip_rightbus;
  36         unsigned char   res13[0x1fc];
  37         unsigned int    clkout_rightbus;
  38         unsigned int    clkout_rightbus_div_stat;
  39         unsigned char   res14[0x3608];
  40         unsigned int    epll_lock;
  41         unsigned char   res15[0xc];
  42         unsigned int    vpll_lock;
  43         unsigned char   res16[0xec];
  44         unsigned int    epll_con0;
  45         unsigned int    epll_con1;
  46         unsigned char   res17[0x8];
  47         unsigned int    vpll_con0;
  48         unsigned int    vpll_con1;
  49         unsigned char   res18[0xe8];
  50         unsigned int    src_top0;
  51         unsigned int    src_top1;
  52         unsigned char   res19[0x8];
  53         unsigned int    src_cam;
  54         unsigned int    src_tv;
  55         unsigned int    src_mfc;
  56         unsigned int    src_g3d;
  57         unsigned int    src_image;
  58         unsigned int    src_lcd0;
  59         unsigned int    src_lcd1;
  60         unsigned int    src_maudio;
  61         unsigned int    src_fsys;
  62         unsigned char   res20[0xc];
  63         unsigned int    src_peril0;
  64         unsigned int    src_peril1;
  65         unsigned char   res21[0xb8];
  66         unsigned int    src_mask_top;
  67         unsigned char   res22[0xc];
  68         unsigned int    src_mask_cam;
  69         unsigned int    src_mask_tv;
  70         unsigned char   res23[0xc];
  71         unsigned int    src_mask_lcd0;
  72         unsigned int    src_mask_lcd1;
  73         unsigned int    src_mask_maudio;
  74         unsigned int    src_mask_fsys;
  75         unsigned char   res24[0xc];
  76         unsigned int    src_mask_peril0;
  77         unsigned int    src_mask_peril1;
  78         unsigned char   res25[0xb8];
  79         unsigned int    mux_stat_top;
  80         unsigned char   res26[0x14];
  81         unsigned int    mux_stat_mfc;
  82         unsigned int    mux_stat_g3d;
  83         unsigned int    mux_stat_image;
  84         unsigned char   res27[0xdc];
  85         unsigned int    div_top;
  86         unsigned char   res28[0xc];
  87         unsigned int    div_cam;
  88         unsigned int    div_tv;
  89         unsigned int    div_mfc;
  90         unsigned int    div_g3d;
  91         unsigned int    div_image;
  92         unsigned int    div_lcd0;
  93         unsigned int    div_lcd1;
  94         unsigned int    div_maudio;
  95         unsigned int    div_fsys0;
  96         unsigned int    div_fsys1;
  97         unsigned int    div_fsys2;
  98         unsigned int    div_fsys3;
  99         unsigned int    div_peril0;
 100         unsigned int    div_peril1;
 101         unsigned int    div_peril2;
 102         unsigned int    div_peril3;
 103         unsigned int    div_peril4;
 104         unsigned int    div_peril5;
 105         unsigned char   res29[0x18];
 106         unsigned int    div2_ratio;
 107         unsigned char   res30[0x8c];
 108         unsigned int    div_stat_top;
 109         unsigned char   res31[0xc];
 110         unsigned int    div_stat_cam;
 111         unsigned int    div_stat_tv;
 112         unsigned int    div_stat_mfc;
 113         unsigned int    div_stat_g3d;
 114         unsigned int    div_stat_image;
 115         unsigned int    div_stat_lcd0;
 116         unsigned int    div_stat_lcd1;
 117         unsigned int    div_stat_maudio;
 118         unsigned int    div_stat_fsys0;
 119         unsigned int    div_stat_fsys1;
 120         unsigned int    div_stat_fsys2;
 121         unsigned int    div_stat_fsys3;
 122         unsigned int    div_stat_peril0;
 123         unsigned int    div_stat_peril1;
 124         unsigned int    div_stat_peril2;
 125         unsigned int    div_stat_peril3;
 126         unsigned int    div_stat_peril4;
 127         unsigned int    div_stat_peril5;
 128         unsigned char   res32[0x18];
 129         unsigned int    div2_stat;
 130         unsigned char   res33[0x29c];
 131         unsigned int    gate_ip_cam;
 132         unsigned int    gate_ip_tv;
 133         unsigned int    gate_ip_mfc;
 134         unsigned int    gate_ip_g3d;
 135         unsigned int    gate_ip_image;
 136         unsigned int    gate_ip_lcd0;
 137         unsigned int    gate_ip_lcd1;
 138         unsigned char   res34[0x4];
 139         unsigned int    gate_ip_fsys;
 140         unsigned char   res35[0x8];
 141         unsigned int    gate_ip_gps;
 142         unsigned int    gate_ip_peril;
 143         unsigned char   res36[0xc];
 144         unsigned int    gate_ip_perir;
 145         unsigned char   res37[0xc];
 146         unsigned int    gate_block;
 147         unsigned char   res38[0x8c];
 148         unsigned int    clkout_cmu_top;
 149         unsigned int    clkout_cmu_top_div_stat;
 150         unsigned char   res39[0x37f8];
 151         unsigned int    src_dmc;
 152         unsigned char   res40[0xfc];
 153         unsigned int    src_mask_dmc;
 154         unsigned char   res41[0xfc];
 155         unsigned int    mux_stat_dmc;
 156         unsigned char   res42[0xfc];
 157         unsigned int    div_dmc0;
 158         unsigned int    div_dmc1;
 159         unsigned char   res43[0xf8];
 160         unsigned int    div_stat_dmc0;
 161         unsigned int    div_stat_dmc1;
 162         unsigned char   res44[0x2f8];
 163         unsigned int    gate_ip_dmc;
 164         unsigned char   res45[0xfc];
 165         unsigned int    clkout_cmu_dmc;
 166         unsigned int    clkout_cmu_dmc_div_stat;
 167         unsigned char   res46[0x5f8];
 168         unsigned int    dcgidx_map0;
 169         unsigned int    dcgidx_map1;
 170         unsigned int    dcgidx_map2;
 171         unsigned char   res47[0x14];
 172         unsigned int    dcgperf_map0;
 173         unsigned int    dcgperf_map1;
 174         unsigned char   res48[0x18];
 175         unsigned int    dvcidx_map;
 176         unsigned char   res49[0x1c];
 177         unsigned int    freq_cpu;
 178         unsigned int    freq_dpm;
 179         unsigned char   res50[0x18];
 180         unsigned int    dvsemclk_en;
 181         unsigned int    maxperf;
 182         unsigned char   res51[0x2f78];
 183         unsigned int    apll_lock;
 184         unsigned char   res52[0x4];
 185         unsigned int    mpll_lock;
 186         unsigned char   res53[0xf4];
 187         unsigned int    apll_con0;
 188         unsigned int    apll_con1;
 189         unsigned int    mpll_con0;
 190         unsigned int    mpll_con1;
 191         unsigned char   res54[0xf0];
 192         unsigned int    src_cpu;
 193         unsigned char   res55[0x1fc];
 194         unsigned int    mux_stat_cpu;
 195         unsigned char   res56[0xfc];
 196         unsigned int    div_cpu0;
 197         unsigned int    div_cpu1;
 198         unsigned char   res57[0xf8];
 199         unsigned int    div_stat_cpu0;
 200         unsigned int    div_stat_cpu1;
 201         unsigned char   res58[0x3f8];
 202         unsigned int    clkout_cmu_cpu;
 203         unsigned int    clkout_cmu_cpu_div_stat;
 204         unsigned char   res59[0x5f8];
 205         unsigned int    armclk_stopctrl;
 206         unsigned int    atclk_stopctrl;
 207         unsigned char   res60[0x8];
 208         unsigned int    parityfail_status;
 209         unsigned int    parityfail_clear;
 210         unsigned char   res61[0xe8];
 211         unsigned int    apll_con0_l8;
 212         unsigned int    apll_con0_l7;
 213         unsigned int    apll_con0_l6;
 214         unsigned int    apll_con0_l5;
 215         unsigned int    apll_con0_l4;
 216         unsigned int    apll_con0_l3;
 217         unsigned int    apll_con0_l2;
 218         unsigned int    apll_con0_l1;
 219         unsigned int    iem_control;
 220         unsigned char   res62[0xdc];
 221         unsigned int    apll_con1_l8;
 222         unsigned int    apll_con1_l7;
 223         unsigned int    apll_con1_l6;
 224         unsigned int    apll_con1_l5;
 225         unsigned int    apll_con1_l4;
 226         unsigned int    apll_con1_l3;
 227         unsigned int    apll_con1_l2;
 228         unsigned int    apll_con1_l1;
 229         unsigned char   res63[0xe0];
 230         unsigned int    div_iem_l8;
 231         unsigned int    div_iem_l7;
 232         unsigned int    div_iem_l6;
 233         unsigned int    div_iem_l5;
 234         unsigned int    div_iem_l4;
 235         unsigned int    div_iem_l3;
 236         unsigned int    div_iem_l2;
 237         unsigned int    div_iem_l1;
 238 };
 239
 240 struct exynos4x12_clock {
 241         unsigned char   res1[0x4200];
 242         unsigned int    src_leftbus;
 243         unsigned char   res2[0x1fc];
 244         unsigned int    mux_stat_leftbus;
 245         unsigned char   res3[0xfc];
 246         unsigned int    div_leftbus;
 247         unsigned char   res4[0xfc];
 248         unsigned int    div_stat_leftbus;
 249         unsigned char   res5[0x1fc];
 250         unsigned int    gate_ip_leftbus;
 251         unsigned char   res6[0x12c];
 252         unsigned int    gate_ip_image;
 253         unsigned char   res7[0xcc];
 254         unsigned int    clkout_leftbus;
 255         unsigned int    clkout_leftbus_div_stat;
 256         unsigned char   res8[0x37f8];
 257         unsigned int    src_rightbus;
 258         unsigned char   res9[0x1fc];
 259         unsigned int    mux_stat_rightbus;
 260         unsigned char   res10[0xfc];
 261         unsigned int    div_rightbus;
 262         unsigned char   res11[0xfc];
 263         unsigned int    div_stat_rightbus;
 264         unsigned char   res12[0x1fc];
 265         unsigned int    gate_ip_rightbus;
 266         unsigned char   res13[0x15c];
 267         unsigned int    gate_ip_perir;
 268         unsigned char   res14[0x9c];
 269         unsigned int    clkout_rightbus;
 270         unsigned int    clkout_rightbus_div_stat;
 271         unsigned char   res15[0x3608];
 272         unsigned int    epll_lock;
 273         unsigned char   res16[0xc];
 274         unsigned int    vpll_lock;
 275         unsigned char   res17[0xec];
 276         unsigned int    epll_con0;
 277         unsigned int    epll_con1;
 278         unsigned int    epll_con2;
 279         unsigned char   res18[0x4];
 280         unsigned int    vpll_con0;
 281         unsigned int    vpll_con1;
 282         unsigned int    vpll_con2;
 283         unsigned char   res19[0xe4];
 284         unsigned int    src_top0;
 285         unsigned int    src_top1;
 286         unsigned char   res20[0x8];
 287         unsigned int    src_cam;
 288         unsigned int    src_tv;
 289         unsigned int    src_mfc;
 290         unsigned int    src_g3d;
 291         unsigned char   res21[0x4];
 292         unsigned int    src_lcd;
 293         unsigned int    src_isp;
 294         unsigned int    src_maudio;
 295         unsigned int    src_fsys;
 296         unsigned char   res22[0xc];
 297         unsigned int    src_peril0;
 298         unsigned int    src_peril1;
 299         unsigned int    src_cam1;
 300         unsigned char   res23[0xb4];
 301         unsigned int    src_mask_top;
 302         unsigned char   res24[0xc];
 303         unsigned int    src_mask_cam;
 304         unsigned int    src_mask_tv;
 305         unsigned char   res25[0xc];
 306         unsigned int    src_mask_lcd;
 307         unsigned int    src_mask_isp;
 308         unsigned int    src_mask_maudio;
 309         unsigned int    src_mask_fsys;
 310         unsigned char   res26[0xc];
 311         unsigned int    src_mask_peril0;
 312         unsigned int    src_mask_peril1;
 313         unsigned char   res27[0xb8];
 314         unsigned int    mux_stat_top0;
 315         unsigned int    mux_stat_top1;
 316         unsigned char   res28[0x10];
 317         unsigned int    mux_stat_mfc;
 318         unsigned int    mux_stat_g3d;
 319         unsigned char   res29[0x28];
 320         unsigned int    mux_stat_cam1;
 321         unsigned char   res30[0xb4];
 322         unsigned int    div_top;
 323         unsigned char   res31[0xc];
 324         unsigned int    div_cam;
 325         unsigned int    div_tv;
 326         unsigned int    div_mfc;
 327         unsigned int    div_g3d;
 328         unsigned char   res32[0x4];
 329         unsigned int    div_lcd;
 330         unsigned int    div_isp;
 331         unsigned int    div_maudio;
 332         unsigned int    div_fsys0;
 333         unsigned int    div_fsys1;
 334         unsigned int    div_fsys2;
 335         unsigned int    div_fsys3;
 336         unsigned int    div_peril0;
 337         unsigned int    div_peril1;
 338         unsigned int    div_peril2;
 339         unsigned int    div_peril3;
 340         unsigned int    div_peril4;
 341         unsigned int    div_peril5;
 342         unsigned int    div_cam1;
 343         unsigned char   res33[0x14];
 344         unsigned int    div2_ratio;
 345         unsigned char   res34[0x8c];
 346         unsigned int    div_stat_top;
 347         unsigned char   res35[0xc];
 348         unsigned int    div_stat_cam;
 349         unsigned int    div_stat_tv;
 350         unsigned int    div_stat_mfc;
 351         unsigned int    div_stat_g3d;
 352         unsigned char   res36[0x4];
 353         unsigned int    div_stat_lcd;
 354         unsigned int    div_stat_isp;
 355         unsigned int    div_stat_maudio;
 356         unsigned int    div_stat_fsys0;
 357         unsigned int    div_stat_fsys1;
 358         unsigned int    div_stat_fsys2;
 359         unsigned int    div_stat_fsys3;
 360         unsigned int    div_stat_peril0;
 361         unsigned int    div_stat_peril1;
 362         unsigned int    div_stat_peril2;
 363         unsigned int    div_stat_peril3;
 364         unsigned int    div_stat_peril4;
 365         unsigned int    div_stat_peril5;
 366         unsigned int    div_stat_cam1;
 367         unsigned char   res37[0x14];
 368         unsigned int    div2_stat;
 369         unsigned char   res38[0x29c];
 370         unsigned int    gate_ip_cam;
 371         unsigned int    gate_ip_tv;
 372         unsigned int    gate_ip_mfc;
 373         unsigned int    gate_ip_g3d;
 374         unsigned char   res39[0x4];
 375         unsigned int    gate_ip_lcd;
 376         unsigned int    gate_ip_isp;
 377         unsigned char   res40[0x4];
 378         unsigned int    gate_ip_fsys;
 379         unsigned char   res41[0x8];
 380         unsigned int    gate_ip_gps;
 381         unsigned int    gate_ip_peril;
 382         unsigned char   res42[0xc];
 383         unsigned char   res43[0x4];
 384         unsigned char   res44[0xc];
 385         unsigned int    gate_block;
 386         unsigned char   res45[0x8c];
 387         unsigned int    clkout_cmu_top;
 388         unsigned int    clkout_cmu_top_div_stat;
 389         unsigned char   res46[0x3600];
 390         unsigned int    mpll_lock;
 391         unsigned char   res47[0xfc];
 392         unsigned int    mpll_con0;
 393         unsigned int    mpll_con1;
 394         unsigned char   res48[0xf0];
 395         unsigned int    src_dmc;
 396         unsigned char   res49[0xfc];
 397         unsigned int    src_mask_dmc;
 398         unsigned char   res50[0xfc];
 399         unsigned int    mux_stat_dmc;
 400         unsigned char   res51[0xfc];
 401         unsigned int    div_dmc0;
 402         unsigned int    div_dmc1;
 403         unsigned char   res52[0xf8];
 404         unsigned int    div_stat_dmc0;
 405         unsigned int    div_stat_dmc1;
 406         unsigned char   res53[0xf8];
 407         unsigned int    gate_bus_dmc0;
 408         unsigned int    gate_bus_dmc1;
 409         unsigned char   res54[0x1f8];
 410         unsigned int    gate_ip_dmc0;
 411         unsigned int    gate_ip_dmc1;
 412         unsigned char   res55[0xf8];
 413         unsigned int    clkout_cmu_dmc;
 414         unsigned int    clkout_cmu_dmc_div_stat;
 415         unsigned char   res56[0x5f8];
 416         unsigned int    dcgidx_map0;
 417         unsigned int    dcgidx_map1;
 418         unsigned int    dcgidx_map2;
 419         unsigned char   res57[0x14];
 420         unsigned int    dcgperf_map0;
 421         unsigned int    dcgperf_map1;
 422         unsigned char   res58[0x18];
 423         unsigned int    dvcidx_map;
 424         unsigned char   res59[0x1c];
 425         unsigned int    freq_cpu;
 426         unsigned int    freq_dpm;
 427         unsigned char   res60[0x18];
 428         unsigned int    dvsemclk_en;
 429         unsigned int    maxperf;
 430         unsigned char   res61[0x8];
 431         unsigned int    dmc_freq_ctrl;
 432         unsigned int    dmc_pause_ctrl;
 433         unsigned int    dddrphy_lock_ctrl;
 434         unsigned int    c2c_state;
 435         unsigned char   res62[0x2f60];
 436         unsigned int    apll_lock;
 437         unsigned char   res63[0x8];
 438         unsigned char   res64[0xf4];
 439         unsigned int    apll_con0;
 440         unsigned int    apll_con1;
 441         unsigned char   res65[0xf8];
 442         unsigned int    src_cpu;
 443         unsigned char   res66[0x1fc];
 444         unsigned int    mux_stat_cpu;
 445         unsigned char   res67[0xfc];
 446         unsigned int    div_cpu0;
 447         unsigned int    div_cpu1;
 448         unsigned char   res68[0xf8];
 449         unsigned int    div_stat_cpu0;
 450         unsigned int    div_stat_cpu1;
 451         unsigned char   res69[0x2f8];
 452         unsigned int    clk_gate_ip_cpu;
 453         unsigned char   res70[0xfc];
 454         unsigned int    clkout_cmu_cpu;
 455         unsigned int    clkout_cmu_cpu_div_stat;
 456         unsigned char   res71[0x5f8];
 457         unsigned int    armclk_stopctrl;
 458         unsigned int    atclk_stopctrl;
 459         unsigned char   res72[0x10];
 460         unsigned char   res73[0x8];
 461         unsigned int    pwr_ctrl;
 462         unsigned int    pwr_ctrl2;
 463         unsigned char   res74[0xd8];
 464         unsigned int    apll_con0_l8;
 465         unsigned int    apll_con0_l7;
 466         unsigned int    apll_con0_l6;
 467         unsigned int    apll_con0_l5;
 468         unsigned int    apll_con0_l4;
 469         unsigned int    apll_con0_l3;
 470         unsigned int    apll_con0_l2;
 471         unsigned int    apll_con0_l1;
 472         unsigned int    iem_control;
 473         unsigned char   res75[0xdc];
 474         unsigned int    apll_con1_l8;
 475         unsigned int    apll_con1_l7;
 476         unsigned int    apll_con1_l6;
 477         unsigned int    apll_con1_l5;
 478         unsigned int    apll_con1_l4;
 479         unsigned int    apll_con1_l3;
 480         unsigned int    apll_con1_l2;
 481         unsigned int    apll_con1_l1;
 482         unsigned char   res76[0xe0];
 483         unsigned int    div_iem_l8;
 484         unsigned int    div_iem_l7;
 485         unsigned int    div_iem_l6;
 486         unsigned int    div_iem_l5;
 487         unsigned int    div_iem_l4;
 488         unsigned int    div_iem_l3;
 489         unsigned int    div_iem_l2;
 490         unsigned int    div_iem_l1;
 491         unsigned char   res77[0xe0];
 492         unsigned int    l2_status;
 493         unsigned char   res78[0xc];
 494         unsigned int    cpu_status;
 495         unsigned char   res79[0xc];
 496         unsigned int    ptm_status;
 497         unsigned char   res80[0x2edc];
 498         unsigned int    div_isp0;
 499         unsigned int    div_isp1;
 500         unsigned char   res81[0xf8];
 501         unsigned int    div_stat_isp0;
 502         unsigned int    div_stat_isp1;
 503         unsigned char   res82[0x3f8];
 504         unsigned int    gate_ip_isp0;
 505         unsigned int    gate_ip_isp1;
 506         unsigned char   res83[0x1f8];
 507         unsigned int    clkout_cmu_isp;
 508         unsigned int    clkout_cmu_ispd_div_stat;
 509         unsigned char   res84[0xf8];
 510         unsigned int    cmu_isp_spar0;
 511         unsigned int    cmu_isp_spar1;
 512         unsigned int    cmu_isp_spar2;
 513         unsigned int    cmu_isp_spar3;
 514 };
 515
 516 struct exynos5_clock {
 517         unsigned int    apll_lock;
 518         unsigned char   res1[0xfc];
 519         unsigned int    apll_con0;
 520         unsigned int    apll_con1;
 521         unsigned char   res2[0xf8];
 522         unsigned int    src_cpu;
 523         unsigned char   res3[0x1fc];
 524         unsigned int    mux_stat_cpu;
 525         unsigned char   res4[0xfc];
 526         unsigned int    div_cpu0;
 527         unsigned int    div_cpu1;
 528         unsigned char   res5[0xf8];
 529         unsigned int    div_stat_cpu0;
 530         unsigned int    div_stat_cpu1;
 531         unsigned char   res6[0x1f8];
 532         unsigned int    gate_sclk_cpu;
 533         unsigned char   res7[0x1fc];
 534         unsigned int    clkout_cmu_cpu;
 535         unsigned int    clkout_cmu_cpu_div_stat;
 536         unsigned char   res8[0x5f8];
 537         unsigned int    armclk_stopctrl;
 538         unsigned char   res9[0x0c];
 539         unsigned int    parityfail_status;
 540         unsigned int    parityfail_clear;
 541         unsigned char   res10[0x8];
 542         unsigned int    pwr_ctrl;
 543         unsigned int    pwr_ctr2;
 544         unsigned char   res11[0xd8];
 545         unsigned int    apll_con0_l8;
 546         unsigned int    apll_con0_l7;
 547         unsigned int    apll_con0_l6;
 548         unsigned int    apll_con0_l5;
 549         unsigned int    apll_con0_l4;
 550         unsigned int    apll_con0_l3;
 551         unsigned int    apll_con0_l2;
 552         unsigned int    apll_con0_l1;
 553         unsigned int    iem_control;
 554         unsigned char   res12[0xdc];
 555         unsigned int    apll_con1_l8;
 556         unsigned int    apll_con1_l7;
 557         unsigned int    apll_con1_l6;
 558         unsigned int    apll_con1_l5;
 559         unsigned int    apll_con1_l4;
 560         unsigned int    apll_con1_l3;
 561         unsigned int    apll_con1_l2;
 562         unsigned int    apll_con1_l1;
 563         unsigned char   res13[0xe0];
 564         unsigned int    div_iem_l8;
 565         unsigned int    div_iem_l7;
 566         unsigned int    div_iem_l6;
 567         unsigned int    div_iem_l5;
 568         unsigned int    div_iem_l4;
 569         unsigned int    div_iem_l3;
 570         unsigned int    div_iem_l2;
 571         unsigned int    div_iem_l1;
 572         unsigned char   res14[0x2ce0];
 573         unsigned int    mpll_lock;
 574         unsigned char   res15[0xfc];
 575         unsigned int    mpll_con0;
 576         unsigned int    mpll_con1;
 577         unsigned char   res16[0xf8];
 578         unsigned int    src_core0;
 579         unsigned int    src_core1;
 580         unsigned char   res17[0xf8];
 581         unsigned int    src_mask_core;
 582         unsigned char   res18[0x100];
 583         unsigned int    mux_stat_core1;
 584         unsigned char   res19[0xf8];
 585         unsigned int    div_core0;
 586         unsigned int    div_core1;
 587         unsigned int    div_sysrgt;
 588         unsigned char   res20[0xf4];
 589         unsigned int    div_stat_core0;
 590         unsigned int    div_stat_core1;
 591         unsigned int    div_stat_sysrgt;
 592         unsigned char   res21[0x2f4];
 593         unsigned int    gate_ip_core;
 594         unsigned int    gate_ip_sysrgt;
 595         unsigned char   res22[0x8];
 596         unsigned int    c2c_monitor;
 597         unsigned char   res23[0xec];
 598         unsigned int    clkout_cmu_core;
 599         unsigned int    clkout_cmu_core_div_stat;
 600         unsigned char   res24[0x5f8];
 601         unsigned int    dcgidx_map0;
 602         unsigned int    dcgidx_map1;
 603         unsigned int    dcgidx_map2;
 604         unsigned char   res25[0x14];
 605         unsigned int    dcgperf_map0;
 606         unsigned int    dcgperf_map1;
 607         unsigned char   res26[0x18];
 608         unsigned int    dvcidx_map;
 609         unsigned char   res27[0x1c];
 610         unsigned int    freq_cpu;
 611         unsigned int    freq_dpm;
 612         unsigned char   res28[0x18];
 613         unsigned int    dvsemclk_en;
 614         unsigned int    maxperf;
 615         unsigned char   res29[0xf78];
 616         unsigned int    c2c_config;
 617         unsigned char   res30[0x24fc];
 618         unsigned int    div_acp;
 619         unsigned char   res31[0xfc];
 620         unsigned int    div_stat_acp;
 621         unsigned char   res32[0x1fc];
 622         unsigned int    gate_ip_acp;
 623         unsigned char   res33[0xfc];
 624         unsigned int    div_syslft;
 625         unsigned char   res34[0xc];
 626         unsigned int    div_stat_syslft;
 627         unsigned char   res35[0x1c];
 628         unsigned int    gate_ip_syslft;
 629         unsigned char   res36[0xcc];
 630         unsigned int    clkout_cmu_acp;
 631         unsigned int    clkout_cmu_acp_div_stat;
 632         unsigned char   res37[0x8];
 633         unsigned int    ufmc_config;
 634         unsigned char   res38[0x38ec];
 635         unsigned int    div_isp0;
 636         unsigned int    div_isp1;
 637         unsigned int    div_isp2;
 638         unsigned char   res39[0xf4];
 639         unsigned int    div_stat_isp0;
 640         unsigned int    div_stat_isp1;
 641         unsigned int    div_stat_isp2;
 642         unsigned char   res40[0x3f4];
 643         unsigned int    gate_ip_isp0;
 644         unsigned int    gate_ip_isp1;
 645         unsigned char   res41[0xf8];
 646         unsigned int    gate_sclk_isp;
 647         unsigned char   res42[0xc];
 648         unsigned int    mcuisp_pwr_ctrl;
 649         unsigned char   res43[0xec];
 650         unsigned int    clkout_cmu_isp;
 651         unsigned int    clkout_cmu_isp_div_stat;
 652         unsigned char   res44[0x3618];
 653         unsigned int    cpll_lock;
 654         unsigned char   res45[0xc];
 655         unsigned int    epll_lock;
 656         unsigned char   res46[0xc];
 657         unsigned int    vpll_lock;
 658         unsigned char   res47[0xc];
 659         unsigned int    gpll_lock;
 660         unsigned char   res48[0xcc];
 661         unsigned int    cpll_con0;
 662         unsigned int    cpll_con1;
 663         unsigned char   res49[0x8];
 664         unsigned int    epll_con0;
 665         unsigned int    epll_con1;
 666         unsigned int    epll_con2;
 667         unsigned char   res50[0x4];
 668         unsigned int    vpll_con0;
 669         unsigned int    vpll_con1;
 670         unsigned int    vpll_con2;
 671         unsigned char   res51[0x4];
 672         unsigned int    gpll_con0;
 673         unsigned int    gpll_con1;
 674         unsigned char   res52[0xb8];
 675         unsigned int    src_top0;
 676         unsigned int    src_top1;
 677         unsigned int    src_top2;
 678         unsigned int    src_top3;
 679         unsigned int    src_gscl;
 680         unsigned char   res53[0x8];
 681         unsigned int    src_disp1_0;
 682         unsigned char   res54[0x10];
 683         unsigned int    src_mau;
 684         unsigned int    src_fsys;
 685         unsigned int    src_gen;
 686         unsigned char   res55[0x4];
 687         unsigned int    src_peric0;
 688         unsigned int    src_peric1;
 689         unsigned char   res56[0x18];
 690         unsigned int    sclk_src_isp;
 691         unsigned char   res57[0x9c];
 692         unsigned int    src_mask_top;
 693         unsigned char   res58[0xc];
 694         unsigned int    src_mask_gscl;
 695         unsigned char   res59[0x8];
 696         unsigned int    src_mask_disp1_0;
 697         unsigned char   res60[0x4];
 698         unsigned int    src_mask_mau;
 699         unsigned char   res61[0x8];
 700         unsigned int    src_mask_fsys;
 701         unsigned int    src_mask_gen;
 702         unsigned char   res62[0x8];
 703         unsigned int    src_mask_peric0;
 704         unsigned int    src_mask_peric1;
 705         unsigned char   res63[0x18];
 706         unsigned int    src_mask_isp;
 707         unsigned char   res67[0x9c];
 708         unsigned int    mux_stat_top0;
 709         unsigned int    mux_stat_top1;
 710         unsigned int    mux_stat_top2;
 711         unsigned int    mux_stat_top3;
 712         unsigned char   res68[0xf0];
 713         unsigned int    div_top0;
 714         unsigned int    div_top1;
 715         unsigned char   res69[0x8];
 716         unsigned int    div_gscl;
 717         unsigned char   res70[0x8];
 718         unsigned int    div_disp1_0;
 719         unsigned char   res71[0xc];
 720         unsigned int    div_gen;
 721         unsigned char   res72[0x4];
 722         unsigned int    div_mau;
 723         unsigned int    div_fsys0;
 724         unsigned int    div_fsys1;
 725         unsigned int    div_fsys2;
 726         unsigned char   res73[0x4];
 727         unsigned int    div_peric0;
 728         unsigned int    div_peric1;
 729         unsigned int    div_peric2;
 730         unsigned int    div_peric3;
 731         unsigned int    div_peric4;
 732         unsigned int    div_peric5;
 733         unsigned char   res74[0x10];
 734         unsigned int    sclk_div_isp;
 735         unsigned char   res75[0xc];
 736         unsigned int    div2_ratio0;
 737         unsigned int    div2_ratio1;
 738         unsigned char   res76[0x8];
 739         unsigned int    div4_ratio;
 740         unsigned char   res77[0x6c];
 741         unsigned int    div_stat_top0;
 742         unsigned int    div_stat_top1;
 743         unsigned char   res78[0x8];
 744         unsigned int    div_stat_gscl;
 745         unsigned char   res79[0x8];
 746         unsigned int    div_stat_disp1_0;
 747         unsigned char   res80[0xc];
 748         unsigned int    div_stat_gen;
 749         unsigned char   res81[0x4];
 750         unsigned int    div_stat_mau;
 751         unsigned int    div_stat_fsys0;
 752         unsigned int    div_stat_fsys1;
 753         unsigned int    div_stat_fsys2;
 754         unsigned char   res82[0x4];
 755         unsigned int    div_stat_peric0;
 756         unsigned int    div_stat_peric1;
 757         unsigned int    div_stat_peric2;
 758         unsigned int    div_stat_peric3;
 759         unsigned int    div_stat_peric4;
 760         unsigned int    div_stat_peric5;
 761         unsigned char   res83[0x10];
 762         unsigned int    sclk_div_stat_isp;
 763         unsigned char   res84[0xc];
 764         unsigned int    div2_stat0;
 765         unsigned int    div2_stat1;
 766         unsigned char   res85[0x8];
 767         unsigned int    div4_stat;
 768         unsigned char   res86[0x184];
 769         unsigned int    gate_top_sclk_disp1;
 770         unsigned int    gate_top_sclk_gen;
 771         unsigned char   res87[0xc];
 772         unsigned int    gate_top_sclk_mau;
 773         unsigned int    gate_top_sclk_fsys;
 774         unsigned char   res88[0xc];
 775         unsigned int    gate_top_sclk_peric;
 776         unsigned char   res89[0x1c];
 777         unsigned int    gate_top_sclk_isp;
 778         unsigned char   res90[0xac];
 779         unsigned int    gate_ip_gscl;
 780         unsigned char   res91[0x4];
 781         unsigned int    gate_ip_disp1;
 782         unsigned int    gate_ip_mfc;
 783         unsigned int    gate_ip_g3d;
 784         unsigned int    gate_ip_gen;
 785         unsigned char   res92[0xc];
 786         unsigned int    gate_ip_fsys;
 787         unsigned char   res93[0x8];
 788         unsigned int    gate_ip_peric;
 789         unsigned char   res94[0xc];
 790         unsigned int    gate_ip_peris;
 791         unsigned char   res95[0x1c];
 792         unsigned int    gate_block;
 793         unsigned char   res96[0x1c];
 794         unsigned int    mcuiop_pwr_ctrl;
 795         unsigned char   res97[0x5c];
 796         unsigned int    clkout_cmu_top;
 797         unsigned int    clkout_cmu_top_div_stat;
 798         unsigned char   res98[0x37f8];
 799         unsigned int    src_lex;
 800         unsigned char   res99[0x1fc];
 801         unsigned int    mux_stat_lex;
 802         unsigned char   res100[0xfc];
 803         unsigned int    div_lex;
 804         unsigned char   res101[0xfc];
 805         unsigned int    div_stat_lex;
 806         unsigned char   res102[0x1fc];
 807         unsigned int    gate_ip_lex;
 808         unsigned char   res103[0x1fc];
 809         unsigned int    clkout_cmu_lex;
 810         unsigned int    clkout_cmu_lex_div_stat;
 811         unsigned char   res104[0x3af8];
 812         unsigned int    div_r0x;
 813         unsigned char   res105[0xfc];
 814         unsigned int    div_stat_r0x;
 815         unsigned char   res106[0x1fc];
 816         unsigned int    gate_ip_r0x;
 817         unsigned char   res107[0x1fc];
 818         unsigned int    clkout_cmu_r0x;
 819         unsigned int    clkout_cmu_r0x_div_stat;
 820         unsigned char   res108[0x3af8];
 821         unsigned int    div_r1x;
 822         unsigned char   res109[0xfc];
 823         unsigned int    div_stat_r1x;
 824         unsigned char   res110[0x1fc];
 825         unsigned int    gate_ip_r1x;
 826         unsigned char   res111[0x1fc];
 827         unsigned int    clkout_cmu_r1x;
 828         unsigned int    clkout_cmu_r1x_div_stat;
 829         unsigned char   res112[0x3608];
 830         unsigned int    bpll_lock;
 831         unsigned char   res113[0xfc];
 832         unsigned int    bpll_con0;
 833         unsigned int    bpll_con1;
 834         unsigned char   res114[0xe8];
 835         unsigned int    src_cdrex;
 836         unsigned char   res115[0x1fc];
 837         unsigned int    mux_stat_cdrex;
 838         unsigned char   res116[0xfc];
 839         unsigned int    div_cdrex;
 840         unsigned char   res117[0xfc];
 841         unsigned int    div_stat_cdrex;
 842         unsigned char   res118[0x2fc];
 843         unsigned int    gate_ip_cdrex;
 844         unsigned char   res119[0x10];
 845         unsigned int    dmc_freq_ctrl;
 846         unsigned char   res120[0x4];
 847         unsigned int    drex2_pause;
 848         unsigned char   res121[0xe0];
 849         unsigned int    clkout_cmu_cdrex;
 850         unsigned int    clkout_cmu_cdrex_div_stat;
 851         unsigned char   res122[0x8];
 852         unsigned int    lpddr3phy_ctrl;
 853         unsigned int    lpddr3phy_con0;
 854         unsigned int    lpddr3phy_con1;
 855         unsigned int    lpddr3phy_con2;
 856         unsigned int    lpddr3phy_con3;
 857         unsigned int    pll_div2_sel;
 858         unsigned char   res123[0xf5d8];
 859 };
 860
 861 /* structure for epll configuration used in audio clock configuration */
 862 struct set_epll_con_val {
 863         unsigned int freq_out;          /* frequency out */
 864         unsigned int en_lock_det;       /* enable lock detect */
 865         unsigned int m_div;             /* m divider value */
 866         unsigned int p_div;             /* p divider value */
 867         unsigned int s_div;             /* s divider value */
 868         unsigned int k_dsm;             /* k value of delta signal modulator */
 869 };
 870 #endif
 871
 872 #define MPLL_FOUT_SEL_SHIFT     4
 873 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT   29  /* EPLL Locked bit position*/
 874 #define TIMEOUT_EPLL_LOCK               1000
 875
 876 #define AUDIO_0_RATIO_MASK              0x0f
 877 #define AUDIO_1_RATIO_MASK              0x0f
 878
 879 #define AUDIO1_SEL_MASK                 0xf
 880 #define CLK_SRC_SCLK_EPLL               0x7
 881
 882 /* CON0 bit-fields */
 883 #define EPLL_CON0_MDIV_MASK             0x1ff
 884 #define EPLL_CON0_PDIV_MASK             0x3f
 885 #define EPLL_CON0_SDIV_MASK             0x7
 886 #define EPLL_CON0_MDIV_SHIFT            16
 887 #define EPLL_CON0_PDIV_SHIFT            8
 888 #define EPLL_CON0_SDIV_SHIFT            0
 889 #define EPLL_CON0_LOCK_DET_EN_SHIFT     28
 890 #define EPLL_CON0_LOCK_DET_EN_MASK      1
 891
 892 #define MPLL_FOUT_SEL_MASK      0x1
 893 #define BPLL_FOUT_SEL_SHIFT     0
 894 #define BPLL_FOUT_SEL_MASK      0x1
 895 #endif