arch/arm/include/asm/arch-exynos/sromc.h

   1 /*
   2  * (C) Copyright 2010 Samsung Electronics
   3  * Naveen Krishna Ch <ch.naveen@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  * Note: This file contains the register description for SROMC
  21  *
  22  */
  23
  24 #ifndef __ASM_ARCH_SROMC_H_
  25 #define __ASM_ARCH_SROMC_H_
  26
  27 #define SROMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
  28 #define SROMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
  29                                                 /* 1-> Byte base address*/
  30 #define SROMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
  31 #define SROMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
  32
  33 #define SROMC_BC_TACS(x) (x << 28) /* address set-up */
  34 #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
  35 #define SROMC_BC_TACC(x) (x << 16) /* access cycle */
  36 #define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
  37 #define SROMC_BC_TAH(x)  (x << 8)  /* address holding time */
  38 #define SROMC_BC_TACP(x) (x << 4)  /* page mode access cycle */
  39 #define SROMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
  40
  41 #ifndef __ASSEMBLY__
  42 struct s5p_sromc {
  43         unsigned int    bw;
  44         unsigned int    bc[4];
  45 };
  46 #endif  /* __ASSEMBLY__ */
  47
  48 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
  49 void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
  50
  51 enum {
  52         FDT_SROM_PMC,
  53         FDT_SROM_TACP,
  54         FDT_SROM_TAH,
  55         FDT_SROM_TCOH,
  56         FDT_SROM_TACC,
  57         FDT_SROM_TCOS,
  58         FDT_SROM_TACS,
  59
  60         FDT_SROM_TIMING_COUNT,
  61 };
  62
  63 struct fdt_sromc {
  64         u8 bank;        /* srom bank number */
  65         u8 width;       /* bus width in bytes */
  66         unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
  67 };
  68
  69 #endif /* __ASM_ARCH_SROMC_H_ */