2 * Copyright 2014-2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
10 static struct cpu_type cpu_type_list
[] = {
11 CPU_TYPE_ENTRY(LS2080
, LS2080
, 8),
12 CPU_TYPE_ENTRY(LS2085
, LS2085
, 8),
13 CPU_TYPE_ENTRY(LS2045
, LS2045
, 4),
14 CPU_TYPE_ENTRY(LS1043
, LS1043
, 4),
17 #ifndef CONFIG_SYS_DCACHE_OFF
19 #define SECTION_SHIFT_L0 39UL
20 #define SECTION_SHIFT_L1 30UL
21 #define SECTION_SHIFT_L2 21UL
22 #define BLOCK_SIZE_L0 0x8000000000
23 #define BLOCK_SIZE_L1 0x40000000
24 #define BLOCK_SIZE_L2 0x200000
25 #define NUM_OF_ENTRY 512
26 #define TCR_EL2_PS_40BIT (2 << 16)
28 #define LAYERSCAPE_VA_BITS (40)
29 #define LAYERSCAPE_TCR (TCR_TG0_4K | \
34 TCR_T0SZ(LAYERSCAPE_VA_BITS))
35 #define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
40 TCR_T0SZ(LAYERSCAPE_VA_BITS))
42 #ifdef CONFIG_FSL_LSCH3
43 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
44 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
45 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
46 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
47 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
48 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
49 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
50 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
51 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
52 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
53 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
54 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
55 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
56 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
57 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
58 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000
59 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000
60 #define CONFIG_SYS_FSL_NI_BASE 0x810000000
61 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000
62 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
63 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
64 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
65 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
66 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
67 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
68 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
69 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
70 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
71 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
72 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
73 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
74 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
75 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
76 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
77 #elif defined(CONFIG_FSL_LSCH2)
78 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
79 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
80 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
81 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
82 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
83 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
84 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
85 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
86 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000
87 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
88 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
89 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
90 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
91 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
92 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
93 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
94 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
95 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
96 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
97 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
98 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
101 struct sys_mmu_table
{
115 static const struct sys_mmu_table early_mmu_table
[] = {
116 #ifdef CONFIG_FSL_LSCH3
117 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
118 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
119 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
120 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
121 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
122 /* For IFC Region #1, only the first 4MB is cache-enabled */
123 { CONFIG_SYS_FSL_IFC_BASE1
, CONFIG_SYS_FSL_IFC_BASE1
,
124 CONFIG_SYS_FSL_IFC_SIZE1_1
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
125 { CONFIG_SYS_FSL_IFC_BASE1
+ CONFIG_SYS_FSL_IFC_SIZE1_1
,
126 CONFIG_SYS_FSL_IFC_BASE1
+ CONFIG_SYS_FSL_IFC_SIZE1_1
,
127 CONFIG_SYS_FSL_IFC_SIZE1
- CONFIG_SYS_FSL_IFC_SIZE1_1
,
128 MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
129 { CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FSL_IFC_BASE1
,
130 CONFIG_SYS_FSL_IFC_SIZE1
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
131 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
132 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
133 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
134 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
135 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
136 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
137 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
138 #elif defined(CONFIG_FSL_LSCH2)
139 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
140 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
141 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
142 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
143 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
144 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
145 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
146 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
147 { CONFIG_SYS_FSL_IFC_BASE
, CONFIG_SYS_FSL_IFC_BASE
,
148 CONFIG_SYS_FSL_IFC_SIZE
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
149 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
150 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
151 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
152 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
156 static const struct sys_mmu_table final_mmu_table
[] = {
157 #ifdef CONFIG_FSL_LSCH3
158 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
159 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
160 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
161 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
162 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
163 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
164 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
165 { CONFIG_SYS_FSL_QSPI_BASE2
, CONFIG_SYS_FSL_QSPI_BASE2
,
166 CONFIG_SYS_FSL_QSPI_SIZE2
, MT_DEVICE_NGNRNE
,
167 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
168 { CONFIG_SYS_FSL_IFC_BASE2
, CONFIG_SYS_FSL_IFC_BASE2
,
169 CONFIG_SYS_FSL_IFC_SIZE2
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
170 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
171 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
172 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
173 { CONFIG_SYS_FSL_MC_BASE
, CONFIG_SYS_FSL_MC_BASE
,
174 CONFIG_SYS_FSL_MC_SIZE
, MT_DEVICE_NGNRNE
,
175 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
176 { CONFIG_SYS_FSL_NI_BASE
, CONFIG_SYS_FSL_NI_BASE
,
177 CONFIG_SYS_FSL_NI_SIZE
, MT_DEVICE_NGNRNE
,
178 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
179 /* For QBMAN portal, only the first 64MB is cache-enabled */
180 { CONFIG_SYS_FSL_QBMAN_BASE
, CONFIG_SYS_FSL_QBMAN_BASE
,
181 CONFIG_SYS_FSL_QBMAN_SIZE_1
, MT_NORMAL
,
182 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
183 { CONFIG_SYS_FSL_QBMAN_BASE
+ CONFIG_SYS_FSL_QBMAN_SIZE_1
,
184 CONFIG_SYS_FSL_QBMAN_BASE
+ CONFIG_SYS_FSL_QBMAN_SIZE_1
,
185 CONFIG_SYS_FSL_QBMAN_SIZE
- CONFIG_SYS_FSL_QBMAN_SIZE_1
,
186 MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
187 { CONFIG_SYS_PCIE1_PHYS_ADDR
, CONFIG_SYS_PCIE1_PHYS_ADDR
,
188 CONFIG_SYS_PCIE1_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
189 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
190 { CONFIG_SYS_PCIE2_PHYS_ADDR
, CONFIG_SYS_PCIE2_PHYS_ADDR
,
191 CONFIG_SYS_PCIE2_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
192 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
193 { CONFIG_SYS_PCIE3_PHYS_ADDR
, CONFIG_SYS_PCIE3_PHYS_ADDR
,
194 CONFIG_SYS_PCIE3_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
195 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
196 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
197 { CONFIG_SYS_PCIE4_PHYS_ADDR
, CONFIG_SYS_PCIE4_PHYS_ADDR
,
198 CONFIG_SYS_PCIE4_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
199 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
201 { CONFIG_SYS_FSL_WRIOP1_BASE
, CONFIG_SYS_FSL_WRIOP1_BASE
,
202 CONFIG_SYS_FSL_WRIOP1_SIZE
, MT_DEVICE_NGNRNE
,
203 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
204 { CONFIG_SYS_FSL_AIOP1_BASE
, CONFIG_SYS_FSL_AIOP1_BASE
,
205 CONFIG_SYS_FSL_AIOP1_SIZE
, MT_DEVICE_NGNRNE
,
206 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
207 { CONFIG_SYS_FSL_PEBUF_BASE
, CONFIG_SYS_FSL_PEBUF_BASE
,
208 CONFIG_SYS_FSL_PEBUF_SIZE
, MT_DEVICE_NGNRNE
,
209 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
210 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
211 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
212 #elif defined(CONFIG_FSL_LSCH2)
213 { CONFIG_SYS_FSL_BOOTROM_BASE
, CONFIG_SYS_FSL_BOOTROM_BASE
,
214 CONFIG_SYS_FSL_BOOTROM_SIZE
, MT_DEVICE_NGNRNE
,
215 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
216 { CONFIG_SYS_FSL_CCSR_BASE
, CONFIG_SYS_FSL_CCSR_BASE
,
217 CONFIG_SYS_FSL_CCSR_SIZE
, MT_DEVICE_NGNRNE
,
218 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
219 { CONFIG_SYS_FSL_OCRAM_BASE
, CONFIG_SYS_FSL_OCRAM_BASE
,
220 CONFIG_SYS_FSL_OCRAM_SIZE
, MT_NORMAL
, PMD_SECT_NON_SHARE
},
221 { CONFIG_SYS_FSL_DCSR_BASE
, CONFIG_SYS_FSL_DCSR_BASE
,
222 CONFIG_SYS_FSL_DCSR_SIZE
, MT_DEVICE_NGNRNE
,
223 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
224 { CONFIG_SYS_FSL_QSPI_BASE
, CONFIG_SYS_FSL_QSPI_BASE
,
225 CONFIG_SYS_FSL_QSPI_SIZE
, MT_DEVICE_NGNRNE
,
226 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
227 { CONFIG_SYS_FSL_IFC_BASE
, CONFIG_SYS_FSL_IFC_BASE
,
228 CONFIG_SYS_FSL_IFC_SIZE
, MT_DEVICE_NGNRNE
, PMD_SECT_NON_SHARE
},
229 { CONFIG_SYS_FSL_DRAM_BASE1
, CONFIG_SYS_FSL_DRAM_BASE1
,
230 CONFIG_SYS_FSL_DRAM_SIZE1
, MT_NORMAL
,
231 PMD_SECT_OUTER_SHARE
| PMD_SECT_NS
},
232 { CONFIG_SYS_FSL_QBMAN_BASE
, CONFIG_SYS_FSL_QBMAN_BASE
,
233 CONFIG_SYS_FSL_QBMAN_SIZE
, MT_DEVICE_NGNRNE
,
234 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
235 { CONFIG_SYS_FSL_DRAM_BASE2
, CONFIG_SYS_FSL_DRAM_BASE2
,
236 CONFIG_SYS_FSL_DRAM_SIZE2
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
237 { CONFIG_SYS_PCIE1_PHYS_ADDR
, CONFIG_SYS_PCIE1_PHYS_ADDR
,
238 CONFIG_SYS_PCIE1_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
239 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
240 { CONFIG_SYS_PCIE2_PHYS_ADDR
, CONFIG_SYS_PCIE2_PHYS_ADDR
,
241 CONFIG_SYS_PCIE2_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
242 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
243 { CONFIG_SYS_PCIE3_PHYS_ADDR
, CONFIG_SYS_PCIE3_PHYS_ADDR
,
244 CONFIG_SYS_PCIE3_PHYS_SIZE
, MT_DEVICE_NGNRNE
,
245 PMD_SECT_NON_SHARE
| PMD_SECT_PXN
| PMD_SECT_UXN
},
246 { CONFIG_SYS_FSL_DRAM_BASE3
, CONFIG_SYS_FSL_DRAM_BASE3
,
247 CONFIG_SYS_FSL_DRAM_SIZE3
, MT_NORMAL
, PMD_SECT_OUTER_SHARE
},
252 int fsl_qoriq_core_to_cluster(unsigned int core
);
254 #endif /* _FSL_LAYERSCAPE_CPU_H */