2 * Copyright 2013-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
8 #define __ARCH_FSL_LSCH2_IMMAP_H__
10 #include <fsl_immap.h>
12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_DCSRBAR 0x20000000
14 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
18 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
19 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
20 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
21 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
22 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
23 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
24 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
25 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
26 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
27 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
28 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
29 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
30 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
33 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
34 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
35 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
36 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
37 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
38 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
39 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
40 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
41 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
42 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
44 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
46 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
47 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
48 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
49 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
51 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
53 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
54 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
56 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
58 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
60 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
61 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
62 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
64 #ifdef CONFIG_ARCH_LS1012A
65 #define PCIE_LUT_BASE 0xC0000
67 #define PCIE_LUT_BASE 0x10000
69 #define PCIE_LUT_LCTRL0 0x7F8
70 #define PCIE_LUT_DBG 0x7FC
72 /* TZ Address Space Controller Definitions */
73 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
74 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
75 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
76 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
77 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
78 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
79 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
80 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
81 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
82 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
83 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
84 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
85 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
87 #define TP_ITYP_AV 0x00000001 /* Initiator available */
88 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
89 #define TP_ITYP_TYPE_ARM 0x0
90 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
91 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
92 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
93 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
94 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
95 #define TY_ITYP_VER_A7 0x1
96 #define TY_ITYP_VER_A53 0x2
97 #define TY_ITYP_VER_A57 0x3
98 #define TY_ITYP_VER_A72 0x4
100 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
101 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
102 #define TP_INIT_PER_CLUSTER 4
105 * Define default values for some CCSR macros to make header files cleaner*
107 * To completely disable CCSR relocation in a board header file, define
108 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
109 * to a value that is the same as CONFIG_SYS_CCSRBAR.
112 #ifdef CONFIG_SYS_CCSRBAR_PHYS
113 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
114 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
117 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
118 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
119 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
120 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
123 #ifndef CONFIG_SYS_CCSRBAR
124 #define CONFIG_SYS_CCSRBAR 0x01000000
127 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
128 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
131 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
132 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
135 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
136 CONFIG_SYS_CCSRBAR_PHYS_LOW)
139 unsigned long freq_processor
[CONFIG_MAX_CPUS
];
140 unsigned long freq_systembus
;
141 unsigned long freq_ddrbus
;
142 unsigned long freq_localbus
;
143 unsigned long freq_sdhc
;
144 #ifdef CONFIG_SYS_DPAA_FMAN
145 unsigned long freq_fman
[CONFIG_SYS_NUM_FMAN
];
147 unsigned long freq_qman
;
150 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
151 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
152 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
153 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
154 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
155 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
156 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
158 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
159 #define CONFIG_SYS_FSL_FM1_ADDR \
160 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
161 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
162 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
164 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
165 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
166 #define CONFIG_SYS_FSL_SEC_ADDR \
167 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
168 #define CONFIG_SYS_FSL_JR0_ADDR \
169 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
171 /* Device Configuration and Pin Control */
172 #define DCFG_DCSR_PORCR1 0x0
175 u32 porsr1
; /* POR status 1 */
176 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
177 u32 porsr2
; /* POR status 2 */
178 u8 res_008
[0x20-0x8];
179 u32 gpporcr1
; /* General-purpose POR configuration */
181 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
182 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
183 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
184 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
185 u32 dcfg_fusesr
; /* Fuse status register */
186 u8 res_02c
[0x70-0x2c];
187 u32 devdisr
; /* Device disable control */
188 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
189 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
190 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
191 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
192 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
193 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
194 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
195 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
196 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
197 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
198 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
199 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
200 u32 devdisr2
; /* Device disable control 2 */
201 u32 devdisr3
; /* Device disable control 3 */
202 u32 devdisr4
; /* Device disable control 4 */
203 u32 devdisr5
; /* Device disable control 5 */
204 u32 devdisr6
; /* Device disable control 6 */
205 u32 devdisr7
; /* Device disable control 7 */
206 u8 res_08c
[0x94-0x8c];
207 u32 coredisru
; /* uppper portion for support of 64 cores */
208 u32 coredisrl
; /* lower portion for support of 64 cores */
209 u8 res_09c
[0xa0-0x9c];
210 u32 pvr
; /* Processor version */
211 u32 svr
; /* System version */
212 u32 mvr
; /* Manufacturing version */
213 u8 res_0ac
[0xb0-0xac];
214 u32 rstcr
; /* Reset control */
215 u32 rstrqpblsr
; /* Reset request preboot loader status */
216 u8 res_0b8
[0xc0-0xb8];
217 u32 rstrqmr1
; /* Reset request mask */
218 u8 res_0c4
[0xc8-0xc4];
219 u32 rstrqsr1
; /* Reset request status */
220 u8 res_0cc
[0xd4-0xcc];
221 u32 rstrqwdtmrl
; /* Reset request WDT mask */
222 u8 res_0d8
[0xdc-0xd8];
223 u32 rstrqwdtsrl
; /* Reset request WDT status */
224 u8 res_0e0
[0xe4-0xe0];
225 u32 brrl
; /* Boot release */
226 u8 res_0e8
[0x100-0xe8];
227 u32 rcwsr
[16]; /* Reset control word status */
228 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
229 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
230 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
231 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
232 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
233 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
234 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
235 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
236 #define RCW_SB_EN_REG_INDEX 7
237 #define RCW_SB_EN_MASK 0x00200000
239 u8 res_140
[0x200-0x140];
240 u32 scratchrw
[4]; /* Scratch Read/Write */
241 u8 res_210
[0x300-0x210];
242 u32 scratchw1r
[4]; /* Scratch Read (Write once) */
243 u8 res_310
[0x400-0x310];
245 u8 res_430
[0x500-0x430];
247 /* PCI Express n Logical I/O Device Number register */
248 u32 dcfg_ccsr_pex1liodnr
;
249 u32 dcfg_ccsr_pex2liodnr
;
250 u32 dcfg_ccsr_pex3liodnr
;
251 u32 dcfg_ccsr_pex4liodnr
;
252 /* RIO n Logical I/O Device Number register */
253 u32 dcfg_ccsr_rio1liodnr
;
254 u32 dcfg_ccsr_rio2liodnr
;
255 u32 dcfg_ccsr_rio3liodnr
;
256 u32 dcfg_ccsr_rio4liodnr
;
257 /* USB Logical I/O Device Number register */
258 u32 dcfg_ccsr_usb1liodnr
;
259 u32 dcfg_ccsr_usb2liodnr
;
260 u32 dcfg_ccsr_usb3liodnr
;
261 u32 dcfg_ccsr_usb4liodnr
;
262 /* SD/MMC Logical I/O Device Number register */
263 u32 dcfg_ccsr_sdmmc1liodnr
;
264 u32 dcfg_ccsr_sdmmc2liodnr
;
265 u32 dcfg_ccsr_sdmmc3liodnr
;
266 u32 dcfg_ccsr_sdmmc4liodnr
;
267 /* RIO Message Unit Logical I/O Device Number register */
268 u32 dcfg_ccsr_riomaintliodnr
;
270 u8 res_544
[0x550-0x544];
272 u8 res_560
[0x570-0x560];
274 u32 dcfg_ccsr_misc1liodnr
;
275 u32 dcfg_ccsr_misc2liodnr
;
276 u32 dcfg_ccsr_misc3liodnr
;
277 u32 dcfg_ccsr_misc4liodnr
;
278 u32 dcfg_ccsr_dma1liodnr
;
279 u32 dcfg_ccsr_dma2liodnr
;
280 u32 dcfg_ccsr_dma3liodnr
;
281 u32 dcfg_ccsr_dma4liodnr
;
282 u32 dcfg_ccsr_spare1liodnr
;
283 u32 dcfg_ccsr_spare2liodnr
;
284 u32 dcfg_ccsr_spare3liodnr
;
285 u32 dcfg_ccsr_spare4liodnr
;
286 u8 res_5a0
[0x600-0x5a0];
292 u8 res_60c
[0x610-0x60c];
293 u32 dcfg_ccsr_gensr1
;
294 u32 dcfg_ccsr_gensr2
;
295 u32 dcfg_ccsr_gensr3
;
296 u32 dcfg_ccsr_gensr4
;
297 u32 dcfg_ccsr_gencr1
;
298 u32 dcfg_ccsr_gencr2
;
299 u32 dcfg_ccsr_gencr3
;
300 u32 dcfg_ccsr_gencr4
;
301 u32 dcfg_ccsr_gencr5
;
302 u32 dcfg_ccsr_gencr6
;
303 u32 dcfg_ccsr_gencr7
;
304 u8 res_63c
[0x658-0x63c];
305 u32 dcfg_ccsr_cgensr1
;
306 u32 dcfg_ccsr_cgensr0
;
307 u8 res_660
[0x678-0x660];
308 u32 dcfg_ccsr_cgencr1
;
310 u32 dcfg_ccsr_cgencr0
;
311 u8 res_680
[0x700-0x680];
312 u32 dcfg_ccsr_sriopstecr
;
313 u32 dcfg_ccsr_dcsrcr
;
315 u8 res_708
[0x740-0x708]; /* add more registers when needed */
316 u32 tp_ityp
[64]; /* Topology Initiator Type Register */
321 u8 res_8c0
[0xa00-0x8c0]; /* add more registers when needed */
322 u32 dcfg_ccsr_qmbm_warmrst
;
323 u8 res_a04
[0xa20-0xa04]; /* add more registers when needed */
324 u32 dcfg_ccsr_reserved0
;
325 u32 dcfg_ccsr_reserved1
;
328 #define SCFG_QSPI_CLKSEL 0x40100000
329 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
330 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
331 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
332 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000
333 #define SCFG_USBPWRFAULT_SHARED 0x00000001
334 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002
335 #define SCFG_USBPWRFAULT_USB3_SHIFT 4
336 #define SCFG_USBPWRFAULT_USB2_SHIFT 2
337 #define SCFG_USBPWRFAULT_USB1_SHIFT 0
339 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
340 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
341 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
342 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
344 /* Supplemental Configuration Unit */
346 u8 res_000
[0x100-0x000];
349 u8 res_108
[0x114-0x108];
358 u8 res_140
[0x158-0x140];
361 u8 res_160
[0x180-0x160];
363 u8 res_184
[0x18c-0x184];
365 u8 res_190
[0x1a4-0x190];
367 u8 res_1a8
[0x1ac-0x1a8];
369 u8 res_1b0
[0x204-0x1b0];
371 u8 res_208
[0x220-0x208];
381 u8 res_244
[0x400-0x244];
386 u32 usbdrvvbus_selcr
;
387 u32 usbpwrfault_selcr
;
388 u32 usb_refclk_selcr1
;
389 u32 usb_refclk_selcr2
;
390 u32 usb_refclk_selcr3
;
391 u8 res_424
[0x600-0x424];
393 u8 res_610
[0x680-0x610];
395 u8 res_684
[0x1000-0x684];
398 u8 res_1008
[0x2000-0x1008];
401 u8 res_2008
[0x3000-0x2008];
409 u32 clkcncsr
; /* core cluster n clock control status */
411 u32 clkcghwacsr
; /* Clock generator n hardware accelerator */
414 u8 res_040
[0x780]; /* 0x100 */
420 u32 clkpcsr
; /* 0xa00 Platform clock domain control/status */
422 u32 pllpgsr
; /* 0xc00 Platform PLL General Status */
424 u32 plldgsr
; /* 0xc20 DDR PLL General Status */
441 #define SRDS_MAX_LANES 4
444 u32 rstctl
; /* Reset Control Register */
445 #define SRDS_RSTCTL_RST 0x80000000
446 #define SRDS_RSTCTL_RSTDONE 0x40000000
447 #define SRDS_RSTCTL_RSTERR 0x20000000
448 #define SRDS_RSTCTL_SWRST 0x10000000
449 #define SRDS_RSTCTL_SDEN 0x00000020
450 #define SRDS_RSTCTL_SDRST_B 0x00000040
451 #define SRDS_RSTCTL_PLLRST_B 0x00000080
452 u32 pllcr0
; /* PLL Control Register 0 */
453 #define SRDS_PLLCR0_POFF 0x80000000
454 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
455 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
456 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
457 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
458 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
459 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
460 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
461 #define SRDS_PLLCR0_PLL_LCK 0x00800000
462 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
463 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
464 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
465 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
466 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
467 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
468 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
469 u32 pllcr1
; /* PLL Control Register 1 */
470 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
471 u32 res_0c
; /* 0x00c */
474 u32 pllcr5
; /* 0x018 SerDes PLL1 Control 5 */
475 u8 res_1c
[0x20-0x1c];
477 u8 res_40
[0x90-0x40];
478 u32 srdstcalcr
; /* 0x90 TX Calibration Control */
479 u8 res_94
[0xa0-0x94];
480 u32 srdsrcalcr
; /* 0xa0 RX Calibration Control */
481 u8 res_a4
[0xb0-0xa4];
482 u32 srdsgr0
; /* 0xb0 General Register 0 */
483 u8 res_b4
[0x100-0xb4];
485 u32 lnpssr0
; /* 0x100, 0x120, 0x140, 0x160 */
486 u8 res_104
[0x120-0x104];
487 } lnpssr
[4]; /* Lane A, B, C, D */
488 u8 res_180
[0x200-0x180];
489 u32 srdspccr0
; /* 0x200 Protocol Configuration 0 */
490 u32 srdspccr1
; /* 0x204 Protocol Configuration 1 */
491 u32 srdspccr2
; /* 0x208 Protocol Configuration 2 */
492 u32 srdspccr3
; /* 0x20c Protocol Configuration 3 */
493 u32 srdspccr4
; /* 0x210 Protocol Configuration 4 */
494 u32 srdspccr5
; /* 0x214 Protocol Configuration 5 */
495 u32 srdspccr6
; /* 0x218 Protocol Configuration 6 */
496 u32 srdspccr7
; /* 0x21c Protocol Configuration 7 */
497 u32 srdspccr8
; /* 0x220 Protocol Configuration 8 */
498 u32 srdspccr9
; /* 0x224 Protocol Configuration 9 */
499 u32 srdspccra
; /* 0x228 Protocol Configuration A */
500 u32 srdspccrb
; /* 0x22c Protocol Configuration B */
501 u8 res_230
[0x800-0x230];
503 u32 gcr0
; /* 0x800 General Control Register 0 */
504 u32 gcr1
; /* 0x804 General Control Register 1 */
505 u32 gcr2
; /* 0x808 General Control Register 2 */
507 u32 recr0
; /* 0x810 Receive Equalization Control */
509 u32 tecr0
; /* 0x818 Transmit Equalization Control */
511 u32 ttlcr0
; /* 0x820 Transition Tracking Loop Ctrl 0 */
512 u8 res_824
[0x83c-0x824];
514 } lane
[4]; /* Lane A, B, C, D */
515 u8 res_900
[0x1000-0x900]; /* from 0x900 to 0xfff */
517 u32 srdspexcr0
; /* 0x1000, 0x1040, 0x1080 */
518 u8 res_1004
[0x1040-0x1004];
520 u8 res_10c0
[0x1800-0x10c0];
522 u8 res_1800
[0x1804-0x1800];
523 u32 srdssgmiicr1
; /* 0x1804 SGMII Protocol Control 1 */
524 u8 res_1808
[0x180c-0x1808];
525 u32 srdssgmiicr3
; /* 0x180c SGMII Protocol Control 3 */
526 } sgmii
[4]; /* Lane A, B, C, D */
527 u8 res_1840
[0x1880-0x1840];
529 u8 res_1880
[0x1884-0x1880];
530 u32 srdsqsgmiicr1
; /* 0x1884 QSGMII Protocol Control 1 */
531 u8 res_1888
[0x188c-0x1888];
532 u32 srdsqsgmiicr3
; /* 0x188c QSGMII Protocol Control 3 */
533 } qsgmii
[2]; /* Lane A, B */
534 u8 res_18a0
[0x1980-0x18a0];
536 u8 res_1980
[0x1984-0x1980];
537 u32 srdsxficr1
; /* 0x1984 XFI Protocol Control 1 */
538 u8 res_1988
[0x198c-0x1988];
539 u32 srdsxficr3
; /* 0x198c XFI Protocol Control 3 */
540 } xfi
[2]; /* Lane A, B */
541 u8 res_19a0
[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
544 #define CCI400_CTRLORD_TERM_BARRIER 0x00000008
545 #define CCI400_CTRLORD_EN_BARRIER 0
546 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002
547 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
548 #define CCI400_SNOOP_REQ_EN 0x00000001
550 /* CCI-400 registers */
552 u32 ctrl_ord
; /* Control Override */
553 u32 spec_ctrl
; /* Speculation Control */
554 u32 secure_access
; /* Secure Access */
555 u32 status
; /* Status */
556 u32 impr_err
; /* Imprecise Error */
557 u8 res_14
[0x100 - 0x14];
558 u32 pmcr
; /* Performance Monitor Control */
559 u8 res_104
[0xfd0 - 0x104];
560 u32 pid
[8]; /* Peripheral ID */
561 u32 cid
[4]; /* Component ID */
563 u32 snoop_ctrl
; /* Snoop Control */
564 u32 sha_ord
; /* Shareable Override */
565 u8 res_1008
[0x1100 - 0x1008];
566 u32 rc_qos_ord
; /* read channel QoS Value Override */
567 u32 wc_qos_ord
; /* read channel QoS Value Override */
568 u8 res_1108
[0x110c - 0x1108];
569 u32 qos_ctrl
; /* QoS Control */
570 u32 max_ot
; /* Max OT */
571 u8 res_1114
[0x1130 - 0x1114];
572 u32 target_lat
; /* Target Latency */
573 u32 latency_regu
; /* Latency Regulation */
574 u32 qos_range
; /* QoS Range */
575 u8 res_113c
[0x2000 - 0x113c];
576 } slave
[5]; /* Slave Interface */
577 u8 res_6000
[0x9004 - 0x6000];
578 u32 cycle_counter
; /* Cycle counter */
579 u32 count_ctrl
; /* Count Control */
580 u32 overflow_status
; /* Overflow Flag Status */
581 u8 res_9010
[0xa000 - 0x9010];
583 u32 event_select
; /* Event Select */
584 u32 event_count
; /* Event Count */
585 u32 counter_ctrl
; /* Counter Control */
586 u32 overflow_status
; /* Overflow Flag Status */
587 u8 res_a010
[0xb000 - 0xa010];
588 } pcounter
[4]; /* Performance Counter */
589 u8 res_e004
[0x10000 - 0xe004];
593 #define SMMU_SCR0 (SMMU_BASE + 0x0)
594 #define SMMU_SCR1 (SMMU_BASE + 0x4)
595 #define SMMU_SCR2 (SMMU_BASE + 0x8)
596 #define SMMU_SACR (SMMU_BASE + 0x10)
597 #define SMMU_IDR0 (SMMU_BASE + 0x20)
598 #define SMMU_IDR1 (SMMU_BASE + 0x24)
600 #define SMMU_NSCR0 (SMMU_BASE + 0x400)
601 #define SMMU_NSCR2 (SMMU_BASE + 0x408)
602 #define SMMU_NSACR (SMMU_BASE + 0x410)
604 #define SCR0_CLIENTPD_MASK 0x00000001
605 #define SCR0_USFCFG_MASK 0x00000400
609 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/