arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * LayerScape Internal Memory Map
   4  *
   5  * Copyright 2017-2020 NXP
   6  * Copyright 2014 Freescale Semiconductor, Inc.
   7  */
   8
   9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
  10 #define __ARCH_FSL_LSCH3_IMMAP_H_
  11
  12 #define CFG_SYS_FSL_DDR_ADDR                    (CONFIG_SYS_IMMR + 0x00080000)
  13 #define CFG_SYS_FSL_DDR2_ADDR           (CONFIG_SYS_IMMR + 0x00090000)
  14 #define CFG_SYS_FSL_DDR3_ADDR           0x08210000
  15 #define CFG_SYS_FSL_GUTS_ADDR           (CONFIG_SYS_IMMR + 0x00E00000)
  16 #define CFG_SYS_FSL_PMU_ADDR                    (CONFIG_SYS_IMMR + 0x00E30000)
  17 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
  18 #define CFG_SYS_FSL_RST_ADDR                    (CONFIG_SYS_IMMR + 0x00e88180)
  19 #else
  20 #define CFG_SYS_FSL_RST_ADDR                    (CONFIG_SYS_IMMR + 0x00E60000)
  21 #endif
  22 #define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR   (CONFIG_SYS_IMMR + 0x00300000)
  23 #define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR   (CONFIG_SYS_IMMR + 0x00310000)
  24 #define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR   (CONFIG_SYS_IMMR + 0x00370000)
  25 #ifndef CONFIG_NXP_LSCH3_2
  26 #define SYS_FSL_QSPI_ADDR                       (CONFIG_SYS_IMMR + 0x010c0000)
  27 #else
  28 #define SYS_NXP_FSPI_ADDR                       (CONFIG_SYS_IMMR + 0x010c0000)
  29 #define SYS_NXP_FSPI_LUTKEY_BASE_ADDR           0x18
  30 #define SYS_NXP_FSPI_LUT_BASE_ADDR              0x200
  31 #endif
  32 #define CFG_SYS_FSL_ESDHC_ADDR          (CONFIG_SYS_IMMR + 0x01140000)
  33 #define FSL_ESDHC1_BASE_ADDR                    CFG_SYS_FSL_ESDHC_ADDR
  34 #define FSL_ESDHC2_BASE_ADDR                    (CONFIG_SYS_IMMR + 0x01150000)
  35 #ifndef CONFIG_NXP_LSCH3_2
  36 #define CFG_SYS_IFC_ADDR                        (CONFIG_SYS_IMMR + 0x01240000)
  37 #endif
  38 #define CFG_SYS_NS16550_COM1                    (CONFIG_SYS_IMMR + 0x011C0500)
  39 #define CFG_SYS_NS16550_COM2                    (CONFIG_SYS_IMMR + 0x011C0600)
  40 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR      0x023d0000
  41 #define CFG_SYS_FSL_TIMER_ADDR          0x023e0000
  42 #define CFG_SYS_FSL_PMU_CLTBENR         (CFG_SYS_FSL_PMU_ADDR + \
  43                                                  0x18A0)
  44 #define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
  45 #define FSL_LSCH3_SVR           (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
  46
  47 #define CFG_SYS_FSL_WRIOP1_ADDR         (CONFIG_SYS_IMMR + 0x7B80000)
  48 #define CFG_SYS_FSL_WRIOP1_MDIO1        (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
  49 #define CFG_SYS_FSL_WRIOP1_MDIO2        (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
  50 #define CFG_SYS_FSL_LSCH3_SERDES_ADDR   (CONFIG_SYS_IMMR + 0xEA0000)
  51
  52 #define CFG_SYS_FSL_DCSR_DDR_ADDR               0x70012c000ULL
  53 #define CFG_SYS_FSL_DCSR_DDR2_ADDR              0x70012d000ULL
  54 #define CFG_SYS_FSL_DCSR_DDR3_ADDR              0x700132000ULL
  55
  56 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01000000)
  57 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01010000)
  58 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01020000)
  59 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01030000)
  60 #ifdef CONFIG_NXP_LSCH3_2
  61 #define I2C5_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01040000)
  62 #define I2C6_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01050000)
  63 #define I2C7_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01060000)
  64 #define I2C8_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01070000)
  65 #endif
  66 #define GPIO4_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01330000)
  67 #define GPIO4_GPDIR_ADDR                        (GPIO4_BASE_ADDR + 0x0)
  68 #define GPIO4_GPDAT_ADDR                        (GPIO4_BASE_ADDR + 0x8)
  69
  70 #define CFG_SYS_XHCI_USB1_ADDR          (CONFIG_SYS_IMMR + 0x02100000)
  71 #define CFG_SYS_XHCI_USB2_ADDR          (CONFIG_SYS_IMMR + 0x02110000)
  72
  73 /* TZ Address Space Controller Definitions */
  74 #define TZASC1_BASE                     0x01100000      /* as per CCSR map. */
  75 #define TZASC2_BASE                     0x01110000      /* as per CCSR map. */
  76 #define TZASC3_BASE                     0x01120000      /* as per CCSR map. */
  77 #define TZASC4_BASE                     0x01130000      /* as per CCSR map. */
  78 #define TZASC_BUILD_CONFIG_REG(x)       ((TZASC1_BASE + (x * 0x10000)))
  79 #define TZASC_ACTION_REG(x)             ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  80 #define TZASC_GATE_KEEPER(x)            ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  81 #define TZASC_REGION_BASE_LOW_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  82 #define TZASC_REGION_BASE_HIGH_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  83 #define TZASC_REGION_TOP_LOW_0(x)       ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  84 #define TZASC_REGION_TOP_HIGH_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  85 #define TZASC_REGION_ATTRIBUTES_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  86 #define TZASC_REGION_ID_ACCESS_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  87
  88 /* EDMA */
  89 #define EDMA_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x012c0000)
  90
  91 /* SATA */
  92 #define AHCI_BASE_ADDR1                         (CONFIG_SYS_IMMR + 0x02200000)
  93 #define AHCI_BASE_ADDR2                         (CONFIG_SYS_IMMR + 0x02210000)
  94 #define AHCI_BASE_ADDR3                         (CONFIG_SYS_IMMR + 0x02220000)
  95 #define AHCI_BASE_ADDR4                         (CONFIG_SYS_IMMR + 0x02230000)
  96
  97 /* QDMA */
  98 #define QDMA_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x07380000)
  99 #define QMAN_CQSIDR_REG                         0x20a80
 100
 101 /* DISPLAY */
 102 #define DISPLAY_BASE_ADDR                       (CONFIG_SYS_IMMR + 0x0e080000)
 103
 104 /* GPU */
 105 #define GPU_BASE_ADDR                           (CONFIG_SYS_IMMR + 0x0e0c0000)
 106
 107 /* SFP */
 108 #define CFG_SYS_SFP_ADDR                (CONFIG_SYS_IMMR + 0x00e80200)
 109
 110 /* SEC */
 111 #define CFG_SYS_FSL_SEC_OFFSET          0x07000000ull
 112 #define CFG_SYS_FSL_JR0_OFFSET          0x07010000ull
 113 #define FSL_SEC_JR0_OFFSET                      CFG_SYS_FSL_JR0_OFFSET
 114 #define FSL_SEC_JR1_OFFSET                      0x07020000ull
 115 #define FSL_SEC_JR2_OFFSET                      0x07030000ull
 116 #define FSL_SEC_JR3_OFFSET                      0x07040000ull
 117 #define CFG_SYS_FSL_SEC_ADDR \
 118         (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
 119 #define CFG_SYS_FSL_JR0_ADDR \
 120         (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
 121 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
 122 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
 123 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
 124 #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
 125
 126 #ifdef CONFIG_TFABOOT
 127 #ifdef CONFIG_NXP_LSCH3_2
 128 /* RCW_SRC field in Power-On Reset Control Register 1 */
 129 #define RCW_SRC_MASK                    0x07800000
 130 #define RCW_SRC_BIT                     23
 131
 132 /* CFG_RCW_SRC[3:0] */
 133 #define RCW_SRC_TYPE_MASK               0x8
 134 #define RCW_SRC_ADDR_OFFSET_8MB         0x800000
 135
 136 /* RCW SRC HARDCODED */
 137 #define RCW_SRC_HARDCODED_VAL           0x0     /* 0x00 - 0x07 */
 138
 139 #define RCW_SRC_SDHC1_VAL               0x8     /* 0x8 */
 140 #define RCW_SRC_SDHC2_VAL               0x9     /* 0x9 */
 141 #define RCW_SRC_I2C1_VAL                0xa     /* 0xa */
 142 #define RCW_SRC_RESERVED_UART_VAL       0xb     /* 0xb */
 143 #define RCW_SRC_FLEXSPI_NAND2K_VAL      0xc     /* 0xc */
 144 #define RCW_SRC_FLEXSPI_NAND4K_VAL      0xd     /* 0xd */
 145 #define RCW_SRC_RESERVED_1_VAL          0xe     /* 0xe */
 146 #define RCW_SRC_FLEXSPI_NOR_24B         0xf     /* 0xf */
 147 #else
 148 #define RCW_SRC_MASK                    (0xFF800000)
 149 #define RCW_SRC_BIT                     23
 150 /* CFG_RCW_SRC[6:0] */
 151 #define RCW_SRC_TYPE_MASK               (0x70)
 152
 153 /* RCW SRC HARDCODED */
 154 #define RCW_SRC_HARDCODED_VAL           (0x10)     /* 0x10 - 0x1f */
 155 /* Hardcoded will also have CFG_RCW_SRC[7] as 1.   0x90 - 0x9f */
 156
 157 /* RCW SRC NOR */
 158 #define RCW_SRC_NOR_VAL                 (0x20)
 159 #define NOR_TYPE_MASK                   (0x10)
 160 #define NOR_16B_VAL                     (0x0)       /* 0x20 - 0x2f */
 161 #define NOR_32B_VAL                     (0x10)       /* 0x30 - 0x3f */
 162
 163 /* RCW SRC Serial Flash
 164  * 1. SERIAL NOR (QSPI)
 165  * 2. OTHERS (SD/MMC, SPI, I2C1
 166  */
 167 #define RCW_SRC_SERIAL_MASK             (0x7F)
 168 #define RCW_SRC_QSPI_VAL                (0x62)     /* 0x62 */
 169 #define RCW_SRC_SD_CARD_VAL             (0x40)     /* 0x40 */
 170 #define RCW_SRC_EMMC_VAL                (0x41)     /* 0x41 */
 171 #define RCW_SRC_I2C1_VAL                (0x49)     /* 0x49 */
 172 #endif
 173 #endif
 174
 175 /* Security Monitor */
 176 #define CFG_SYS_SEC_MON_ADDR            (CONFIG_SYS_IMMR + 0x00e90000)
 177
 178 /* MMU 500 */
 179 #define SMMU_SCR0                       (SMMU_BASE + 0x0)
 180 #define SMMU_SCR1                       (SMMU_BASE + 0x4)
 181 #define SMMU_SCR2                       (SMMU_BASE + 0x8)
 182 #define SMMU_SACR                       (SMMU_BASE + 0x10)
 183 #define SMMU_IDR0                       (SMMU_BASE + 0x20)
 184 #define SMMU_IDR1                       (SMMU_BASE + 0x24)
 185
 186 #define SMMU_NSCR0                      (SMMU_BASE + 0x400)
 187 #define SMMU_NSCR2                      (SMMU_BASE + 0x408)
 188 #define SMMU_NSACR                      (SMMU_BASE + 0x410)
 189
 190 #define SCR0_CLIENTPD_MASK              0x00000001
 191 #define SCR0_USFCFG_MASK                0x00000400
 192
 193
 194 /* PCIe */
 195 #define CFG_SYS_PCIE1_ADDR                      (CONFIG_SYS_IMMR + 0x2400000)
 196 #define CFG_SYS_PCIE2_ADDR                      (CONFIG_SYS_IMMR + 0x2500000)
 197 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 198 #define SYS_PCIE5_ADDR                          (CONFIG_SYS_IMMR + 0x2800000)
 199 #define SYS_PCIE6_ADDR                          (CONFIG_SYS_IMMR + 0x2900000)
 200 #endif
 201
 202 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 203 #define CFG_SYS_PCIE1_PHYS_ADDR         0x8000000000ULL
 204 #define CFG_SYS_PCIE2_PHYS_ADDR         0x8800000000ULL
 205 #define CFG_SYS_PCIE3_PHYS_ADDR         0x9000000000ULL
 206 #define CFG_SYS_PCIE4_PHYS_ADDR         0x9800000000ULL
 207 #define SYS_PCIE5_PHYS_ADDR                     0xa000000000ULL
 208 #define SYS_PCIE6_PHYS_ADDR                     0xa800000000ULL
 209 #elif CONFIG_ARCH_LS1088A
 210 #define CFG_SYS_PCIE1_PHYS_ADDR         0x2000000000ULL
 211 #define CFG_SYS_PCIE2_PHYS_ADDR         0x2800000000ULL
 212 #define CFG_SYS_PCIE3_PHYS_ADDR         0x3000000000ULL
 213 #elif CONFIG_ARCH_LS1028A
 214 #define CFG_SYS_PCIE1_PHYS_ADDR         0x8000000000ULL
 215 #define CFG_SYS_PCIE2_PHYS_ADDR         0x8800000000ULL
 216 #define CFG_SYS_PCIE3_PHYS_ADDR         0x01f0000000ULL
 217 /* this is used by integrated PCI on LS1028, includes ECAM and register space */
 218 #define CFG_SYS_PCIE3_PHYS_SIZE         0x0010000000ULL
 219 #else
 220 #define CFG_SYS_PCIE1_PHYS_ADDR         0x1000000000ULL
 221 #define CFG_SYS_PCIE2_PHYS_ADDR         0x1200000000ULL
 222 #define CFG_SYS_PCIE3_PHYS_ADDR         0x1400000000ULL
 223 #define CFG_SYS_PCIE4_PHYS_ADDR         0x1600000000ULL
 224 #endif
 225
 226 /* Device Configuration */
 227 #define DCFG_BASE               0x01e00000
 228 #define DCFG_PORSR1                     0x000
 229 #define DCFG_PORSR1_RCW_SRC             0xff800000
 230 #define DCFG_PORSR1_RCW_SRC_SDHC1       0x04000000
 231 #define DCFG_PORSR1_RCW_SRC_SDHC2       0x04800000
 232 #define DCFG_PORSR1_RCW_SRC_I2C         0x05000000
 233 #define DCFG_PORSR1_RCW_SRC_FSPI_NOR    0x07800000
 234 #define DCFG_PORSR1_RCW_SRC_NOR         0x12f00000
 235 #define DCFG_RCWSR12                    0x12c
 236 #define DCFG_RCWSR12_SDHC_SHIFT         24
 237 #define DCFG_RCWSR12_SDHC_MASK          0x7
 238 #define DCFG_RCWSR13                    0x130
 239 #define DCFG_RCWSR13_SDHC_SHIFT         3
 240 #define DCFG_RCWSR13_SDHC_MASK          0x7
 241 #define DCFG_RCWSR13_DSPI               (0 << 8)
 242 #define DCFG_RCWSR15                    0x138
 243 #define DCFG_RCWSR15_IFCGRPABASE_QSPI   0x3
 244
 245 #define DCFG_DCSR_BASE          0X700100000ULL
 246 #define DCFG_DCSR_PORCR1                0x000
 247
 248 /* Interrupt Sampling Control */
 249 #define ISC_BASE                0x01F70000
 250 #define IRQCR_OFFSET            0x14
 251
 252 /* Supplemental Configuration */
 253 #define SCFG_BASE               0x01fc0000
 254 #define SCFG_USB3PRM1CR                 0x000
 255 #define SCFG_USB3PRM1CR_INIT            0x27672b2a
 256 #define SCFG_USB_TXVREFTUNE             0x9
 257 #define SCFG_USB_SQRXTUNE_MASK  0x7
 258 #define SCFG_QSPICLKCTLR        0x10
 259
 260 #define DCSR_BASE               0x700000000ULL
 261 #define DCSR_USB_PHY1                   0x4600000
 262 #define DCSR_USB_PHY2                   0x4610000
 263 #define DCSR_USB_PHY_RX_OVRD_IN_HI      0x200C
 264 #define USB_PHY_RX_EQ_VAL_1             0x0000
 265 #define USB_PHY_RX_EQ_VAL_2             0x0080
 266 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
 267         defined(CONFIG_ARCH_LS1028A)
 268 #define USB_PHY_RX_EQ_VAL_3             0x0380
 269 #define USB_PHY_RX_EQ_VAL_4             0x0b80
 270 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 271 #define USB_PHY_RX_EQ_VAL_3             0x0080
 272 #define USB_PHY_RX_EQ_VAL_4             0x0880
 273 #endif
 274 #define DCSR_USB_IOCR1                  0x108004
 275 #define DCSR_USB_PCSTXSWINGFULL 0x71
 276
 277 #define TP_ITYP_AV              0x00000001      /* Initiator available */
 278 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
 279 #define TP_ITYP_TYPE_ARM        0x0
 280 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
 281 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
 282 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
 283 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
 284 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
 285 #define TY_ITYP_VER_A7          0x1
 286 #define TY_ITYP_VER_A53         0x2
 287 #define TY_ITYP_VER_A57         0x3
 288 #define TY_ITYP_VER_A72         0x4
 289
 290 #define TP_CLUSTER_EOC          0x80000000      /* end of clusters */
 291 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 292 #define TP_INIT_PER_CLUSTER     4
 293 /* This is chassis generation 3 */
 294 #ifndef __ASSEMBLY__
 295 struct sys_info {
 296         unsigned long freq_processor[CONFIG_MAX_CPUS];
 297         /* frequency of platform PLL */
 298         unsigned long freq_systembus;
 299         unsigned long freq_ddrbus;
 300         unsigned long freq_cga_m2;
 301 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 302         unsigned long freq_ddrbus2;
 303 #endif
 304         unsigned long freq_localbus;
 305         unsigned long freq_qe;
 306 #ifdef CONFIG_SYS_DPAA_FMAN
 307         unsigned long freq_fman[CFG_SYS_NUM_FMAN];
 308 #endif
 309 #ifdef CONFIG_SYS_DPAA_QBMAN
 310         unsigned long freq_qman;
 311 #endif
 312 #ifdef CONFIG_SYS_DPAA_PME
 313         unsigned long freq_pme;
 314 #endif
 315 };
 316
 317 /* Global Utilities Block */
 318 struct ccsr_gur {
 319         u32     porsr1;         /* POR status 1 */
 320         u32     porsr2;         /* POR status 2 */
 321         u8      res_008[0x20-0x8];
 322         u32     gpporcr1;       /* General-purpose POR configuration */
 323         u32     gpporcr2;       /* General-purpose POR configuration 2 */
 324         u32     gpporcr3;
 325         u32     gpporcr4;
 326         u8      res_030[0x60-0x30];
 327 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK       0x1F
 328 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK    0x1F
 329 #if defined(CONFIG_ARCH_LS1088A)
 330 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT      25
 331 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT   20
 332 #else
 333 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT      2
 334 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT   7
 335 #endif
 336         u32     dcfg_fusesr;    /* Fuse status register */
 337         u8      res_064[0x70-0x64];
 338         u32     devdisr;        /* Device disable control 1 */
 339         u32     devdisr2;       /* Device disable control 2 */
 340         u32     devdisr3;       /* Device disable control 3 */
 341         u32     devdisr4;       /* Device disable control 4 */
 342         u32     devdisr5;       /* Device disable control 5 */
 343         u32     devdisr6;       /* Device disable control 6 */
 344         u8      res_088[0x94-0x88];
 345         u32     coredisr;       /* Device disable control 7 */
 346 #define FSL_CHASSIS3_DEVDISR2_DPMAC1    0x00000001
 347 #define FSL_CHASSIS3_DEVDISR2_DPMAC2    0x00000002
 348 #define FSL_CHASSIS3_DEVDISR2_DPMAC3    0x00000004
 349 #define FSL_CHASSIS3_DEVDISR2_DPMAC4    0x00000008
 350 #define FSL_CHASSIS3_DEVDISR2_DPMAC5    0x00000010
 351 #define FSL_CHASSIS3_DEVDISR2_DPMAC6    0x00000020
 352 #define FSL_CHASSIS3_DEVDISR2_DPMAC7    0x00000040
 353 #define FSL_CHASSIS3_DEVDISR2_DPMAC8    0x00000080
 354 #define FSL_CHASSIS3_DEVDISR2_DPMAC9    0x00000100
 355 #define FSL_CHASSIS3_DEVDISR2_DPMAC10   0x00000200
 356 #define FSL_CHASSIS3_DEVDISR2_DPMAC11   0x00000400
 357 #define FSL_CHASSIS3_DEVDISR2_DPMAC12   0x00000800
 358 #define FSL_CHASSIS3_DEVDISR2_DPMAC13   0x00001000
 359 #define FSL_CHASSIS3_DEVDISR2_DPMAC14   0x00002000
 360 #define FSL_CHASSIS3_DEVDISR2_DPMAC15   0x00004000
 361 #define FSL_CHASSIS3_DEVDISR2_DPMAC16   0x00008000
 362 #define FSL_CHASSIS3_DEVDISR2_DPMAC17   0x00010000
 363 #define FSL_CHASSIS3_DEVDISR2_DPMAC18   0x00020000
 364 #define FSL_CHASSIS3_DEVDISR2_DPMAC19   0x00040000
 365 #define FSL_CHASSIS3_DEVDISR2_DPMAC20   0x00080000
 366 #define FSL_CHASSIS3_DEVDISR2_DPMAC21   0x00100000
 367 #define FSL_CHASSIS3_DEVDISR2_DPMAC22   0x00200000
 368 #define FSL_CHASSIS3_DEVDISR2_DPMAC23   0x00400000
 369 #define FSL_CHASSIS3_DEVDISR2_DPMAC24   0x00800000
 370         u8      res_098[0xa0-0x98];
 371         u32     pvr;            /* Processor version */
 372         u32     svr;            /* System version */
 373         u8      res_0a8[0x100-0xa8];
 374         u32     rcwsr[30];      /* Reset control word status */
 375
 376 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT   2
 377 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK    0x1f
 378 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT   10
 379 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK    0x3f
 380 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT  18
 381 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK   0x3f
 382
 383 #if defined(CONFIG_ARCH_LS2080A)
 384 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF0000
 385 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 386 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
 387 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
 388 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK   FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
 389 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
 390 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK   FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
 391 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 392 #define FSL_CHASSIS3_SRDS1_REGSR        29
 393 #define FSL_CHASSIS3_SRDS2_REGSR        29
 394 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 395 #define FSL_CHASSIS3_EC1_REGSR  27
 396 #define FSL_CHASSIS3_EC2_REGSR  27
 397 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK       0x00000003
 398 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT      0
 399 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK       0x0000000C
 400 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT      2
 401 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x001F0000
 402 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 403 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0x03E00000
 404 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  21
 405 #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK   0x7C000000
 406 #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT  26
 407 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK   FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
 408 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
 409 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK   FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
 410 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 411 #define FSL_CHASSIS3_SRDS3_PRTCL_MASK   FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
 412 #define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
 413 #define FSL_CHASSIS3_SRDS1_REGSR        29
 414 #define FSL_CHASSIS3_SRDS2_REGSR        29
 415 #define FSL_CHASSIS3_SRDS3_REGSR        29
 416 #define FSL_CHASSIS3_RCWSR12_REGSR         12
 417 #define FSL_CHASSIS3_RCWSR13_REGSR         13
 418 #define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK  0x07000000
 419 #define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
 420 #define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK  0x00000038
 421 #define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
 422 #define FSL_CHASSIS3_IIC5_PMUX_MASK        0x00000E00
 423 #define FSL_CHASSIS3_IIC5_PMUX_SHIFT       9
 424 #elif defined(CONFIG_ARCH_LS1088A)
 425 #define FSL_CHASSIS3_EC1_REGSR  26
 426 #define FSL_CHASSIS3_EC2_REGSR  26
 427 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK     0x00000007
 428 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT    0
 429 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK     0x00000038
 430 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT    3
 431 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK   0xFFFF0000
 432 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT  16
 433 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK   0x0000FFFF
 434 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT  0
 435 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK   FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
 436 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
 437 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK   FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
 438 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
 439 #define FSL_CHASSIS3_SRDS1_REGSR        29
 440 #define FSL_CHASSIS3_SRDS2_REGSR        30
 441 #elif defined(CONFIG_ARCH_LS1028A)
 442 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK   0xFFFF0000
 443 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT  16
 444 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK   FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
 445 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
 446 #define FSL_CHASSIS3_SRDS1_REGSR        29
 447 #endif
 448 #define RCW_SB_EN_REG_INDEX     9
 449 #define RCW_SB_EN_MASK          0x00000400
 450
 451         u8      res_178[0x200-0x178];
 452         u32     scratchrw[16];  /* Scratch Read/Write */
 453         u8      res_240[0x300-0x240];
 454         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 455         u8      res_310[0x400-0x310];
 456         u32     bootlocptrl;    /* Boot location pointer low-order addr */
 457         u32     bootlocptrh;    /* Boot location pointer high-order addr */
 458         u8      res_408[0x520-0x408];
 459         u32     usb1_amqr;
 460         u32     usb2_amqr;
 461         u8      res_528[0x530-0x528];   /* add more registers when needed */
 462         u32     sdmm1_amqr;
 463         u32     sdmm2_amqr;
 464         u8      res_538[0x550 - 0x538]; /* add more registers when needed */
 465         u32     sata1_amqr;
 466         u32     sata2_amqr;
 467         u32     sata3_amqr;
 468         u32     sata4_amqr;
 469         u8      res_560[0x570 - 0x560]; /* add more registers when needed */
 470         u32     misc1_amqr;
 471         u8      res_574[0x590-0x574];   /* add more registers when needed */
 472         u32     spare1_amqr;
 473         u32     spare2_amqr;
 474         u32     spare3_amqr;
 475         u8      res_59c[0x620 - 0x59c]; /* add more registers when needed */
 476         u32     gencr[7];       /* General Control Registers */
 477         u8      res_63c[0x640-0x63c];   /* add more registers when needed */
 478         u32     cgensr1;        /* Core General Status Register */
 479         u8      res_644[0x660-0x644];   /* add more registers when needed */
 480         u32     cgencr1;        /* Core General Control Register */
 481         u8      res_664[0x740-0x664];   /* add more registers when needed */
 482         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 483         struct {
 484                 u32     upper;
 485                 u32     lower;
 486         } tp_cluster[4];        /* Core cluster n Topology Register */
 487         u8      res_864[0x920-0x864];   /* add more registers when needed */
 488         u32 ioqoscr[8]; /*I/O Quality of Services Register */
 489         u32 uccr;
 490         u8      res_944[0x960-0x944];   /* add more registers when needed */
 491         u32 ftmcr;
 492         u8      res_964[0x990-0x964];   /* add more registers when needed */
 493         u32 coredisablesr;
 494         u8      res_994[0xa00-0x994];   /* add more registers when needed */
 495         u32 sdbgcr; /*Secure Debug Confifuration Register */
 496         u8      res_a04[0xbf8-0xa04];   /* add more registers when needed */
 497         u32 ipbrr1;
 498         u32 ipbrr2;
 499         u8      res_858[0x1000-0xc00];
 500 };
 501
 502 struct ccsr_clk_cluster_group {
 503         struct {
 504                 u8      res_00[0x10];
 505                 u32     csr;
 506                 u8      res_14[0x20-0x14];
 507         } hwncsr[3];
 508         u8      res_60[0x80-0x60];
 509         struct {
 510                 u32     gsr;
 511                 u8      res_84[0xa0-0x84];
 512         } pllngsr[3];
 513         u8      res_e0[0x100-0xe0];
 514 };
 515
 516 struct ccsr_clk_ctrl {
 517         struct {
 518                 u32 csr;        /* core cluster n clock control status */
 519                 u8  res_04[0x20-0x04];
 520         } clkcncsr[8];
 521 };
 522
 523 struct ccsr_reset {
 524         u32 rstcr;                      /* 0x000 */
 525         u32 rstcrsp;                    /* 0x004 */
 526         u8 res_008[0x10-0x08];          /* 0x008 */
 527         u32 rstrqmr1;                   /* 0x010 */
 528         u32 rstrqmr2;                   /* 0x014 */
 529         u32 rstrqsr1;                   /* 0x018 */
 530         u32 rstrqsr2;                   /* 0x01c */
 531         u32 rstrqwdtmrl;                /* 0x020 */
 532         u32 rstrqwdtmru;                /* 0x024 */
 533         u8 res_028[0x30-0x28];          /* 0x028 */
 534         u32 rstrqwdtsrl;                /* 0x030 */
 535         u32 rstrqwdtsru;                /* 0x034 */
 536         u8 res_038[0x60-0x38];          /* 0x038 */
 537         u32 brrl;                       /* 0x060 */
 538         u32 brru;                       /* 0x064 */
 539         u8 res_068[0x80-0x68];          /* 0x068 */
 540         u32 pirset;                     /* 0x080 */
 541         u32 pirclr;                     /* 0x084 */
 542         u8 res_088[0x90-0x88];          /* 0x088 */
 543         u32 brcorenbr;                  /* 0x090 */
 544         u8 res_094[0x100-0x94];         /* 0x094 */
 545         u32 rcw_reqr;                   /* 0x100 */
 546         u32 rcw_completion;             /* 0x104 */
 547         u8 res_108[0x110-0x108];        /* 0x108 */
 548         u32 pbi_reqr;                   /* 0x110 */
 549         u32 pbi_completion;             /* 0x114 */
 550         u8 res_118[0xa00-0x118];        /* 0x118 */
 551         u32 qmbm_warmrst;               /* 0xa00 */
 552         u32 soc_warmrst;                /* 0xa04 */
 553         u8 res_a08[0xbf8-0xa08];        /* 0xa08 */
 554         u32 ip_rev1;                    /* 0xbf8 */
 555         u32 ip_rev2;                    /* 0xbfc */
 556 };
 557
 558 struct ccsr_serdes {
 559         struct {
 560                 u32     rstctl; /* Reset Control Register */
 561                 u32     pllcr0; /* PLL Control Register 0 */
 562                 u32     pllcr1; /* PLL Control Register 1 */
 563                 u32     pllcr2; /* PLL Control Register 2 */
 564                 u32     pllcr3; /* PLL Control Register 3 */
 565                 u32     pllcr4; /* PLL Control Register 4 */
 566                 u32     pllcr5; /* PLL Control Register 5 */
 567                 u8      res[0x20 - 0x1c];
 568         } bank[2];
 569         u8      res1[0x90 - 0x40];
 570         u32     srdstcalcr;     /* TX Calibration Control */
 571         u32     srdstcalcr1;    /* TX Calibration Control1 */
 572         u8      res2[0xa0 - 0x98];
 573         u32     srdsrcalcr;     /* RX Calibration Control */
 574         u32     srdsrcalcr1;    /* RX Calibration Control1 */
 575         u8      res3[0xb0 - 0xa8];
 576         u32     srdsgr0;        /* General Register 0 */
 577         u8      res4[0x800 - 0xb4];
 578         struct serdes_lane {
 579                 u32     gcr0;   /* General Control Register 0 */
 580                 u32     gcr1;   /* General Control Register 1 */
 581                 u32     gcr2;   /* General Control Register 2 */
 582                 u32     ssc0;   /* Speed Switch Control 0 */
 583                 u32     rec0;   /* Receive Equalization Control 0 */
 584                 u32     rec1;   /* Receive Equalization Control 1 */
 585                 u32     tec0;   /* Transmit Equalization Control 0 */
 586                 u32     ssc1;   /* Speed Switch Control 1 */
 587                 u8      res1[0x840 - 0x820];
 588         } lane[8];
 589         u8 res5[0x19fc - 0xa00];
 590 };
 591
 592 struct ccsr_gpio {
 593         u32     gpdir;
 594         u32     gpodr;
 595         u32     gpdat;
 596         u32     gpier;
 597         u32     gpimr;
 598         u32     gpicr;
 599         u32     gpibe;
 600 };
 601
 602 #endif /*__ASSEMBLY__ */
 603 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */