arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #ifndef __FSL_STREAM_ID_H
   8 #define __FSL_STREAM_ID_H
   9
  10 /* Stream IDs on ls2080a devices are not hardwired and are
  11  * programmed by sw.  There are a limited number of stream IDs
  12  * available, and the partitioning of them is scenario dependent.
  13  * This header defines the partitioning between legacy, PCI,
  14  * and DPAA2 devices.
  15  *
  16  * This partitiong can be customized in this file depending
  17  * on the specific hardware config-- e.g. perhaps not all
  18  * PEX controllers are in use.
  19  *
  20  * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
  21  * each of the different bus masters.  The relationship between
  22  * the AMQ registers and stream IDs is defined in the table below:
  23  *          AMQ bit    streamID bit
  24  *      ---------------------------
  25  *           PL[18]         9
  26  *          BMT[17]         8
  27  *           VA[16]         7
  28  *             [15]         -
  29  *         ICID[14:7]       -
  30  *         ICID[6:0]        6-0
  31  *     ----------------------------
  32  */
  33
  34 #define AMQ_PL_MASK                     (0x1 << 18)   /* priviledge bit */
  35 #define AMQ_BMT_MASK                    (0x1 << 17)   /* bypass bit */
  36
  37 #define FSL_INVALID_STREAM_ID           0
  38
  39 #define FSL_BYPASS_AMQ                  (AMQ_PL_MASK | AMQ_BMT_MASK)
  40
  41 /* legacy devices */
  42 #define FSL_USB1_STREAM_ID              1
  43 #define FSL_USB2_STREAM_ID              2
  44 #define FSL_SDMMC_STREAM_ID             3
  45 #define FSL_SATA1_STREAM_ID             4
  46 #define FSL_SATA2_STREAM_ID             5
  47 #define FSL_DMA_STREAM_ID               6
  48
  49 /* PCI - programmed in PEXn_LUT by OS */
  50 /*   4 IDs per controller */
  51 #define FSL_PEX1_STREAM_ID_START        7
  52 #define FSL_PEX1_STREAM_ID_END          10
  53 #define FSL_PEX2_STREAM_ID_START        11
  54 #define FSL_PEX2_STREAM_ID_END          14
  55 #define FSL_PEX3_STREAM_ID_START        15
  56 #define FSL_PEX3_STREAM_ID_END          18
  57 #define FSL_PEX4_STREAM_ID_START        19
  58 #define FSL_PEX4_STREAM_ID_END          22
  59
  60 /* DPAA2 - set in MC DPC and alloced by MC */
  61 #define FSL_DPAA2_STREAM_ID_START       23
  62 #define FSL_DPAA2_STREAM_ID_END         63
  63
  64 #endif