arch/arm/include/asm/arch-fsl-layerscape/mp.h

   1 /*
   2  * Copyright 2014-2015, Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _FSL_LAYERSCAPE_MP_H
   8 #define _FSL_LAYERSCAPE_MP_H
   9
  10 /*
  11 * Each spin table element is defined as
  12 * struct {
  13 *      uint64_t entry_addr;
  14 *      uint64_t status;
  15 *      uint64_t lpid;
  16 * };
  17 * we pad this struct to 64 bytes so each entry is in its own cacheline
  18 * the actual spin table is an array of these structures
  19 */
  20 #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX  0
  21 #define SPIN_TABLE_ELEM_STATUS_IDX      1
  22 #define SPIN_TABLE_ELEM_LPID_IDX        2
  23 #define WORDS_PER_SPIN_TABLE_ENTRY      8       /* pad to 64 bytes */
  24 #define SPIN_TABLE_ELEM_SIZE            64
  25
  26 #define id_to_core(x)   ((x & 3) | (x >> 6))
  27 #ifndef __ASSEMBLY__
  28 extern u64 __spin_table[];
  29 extern u64 __real_cntfrq;
  30 extern u64 *secondary_boot_code;
  31 extern size_t __secondary_boot_code_size;
  32 int fsl_layerscape_wake_seconday_cores(void);
  33 void *get_spin_tbl_addr(void);
  34 phys_addr_t determine_mp_bootpg(void);
  35 void secondary_boot_func(void);
  36 int is_core_online(u64 cpu_id);
  37 u32 cpu_pos_mask(void);
  38 #endif
  39
  40 #define IH_ARCH_ARM             2       /* ARM */
  41 #define IH_ARCH_ARM64           22      /* ARM64 */
  42
  43 #endif /* _FSL_LAYERSCAPE_MP_H */