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git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/arm/include/asm/arch-lpc32xx/emc.h
2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/types.h>
14 u32 ctrl
; /* Controls operation of the EMC */
15 u32 status
; /* Provides EMC status information */
16 u32 config
; /* Configures operation of the EMC */
18 u32 control
; /* Controls dyn memory operation */
19 u32 refresh
; /* Configures dyn memory refresh operation */
20 u32 read_config
; /* Configures the dyn memory read strategy */
22 u32 t_rp
; /* Precharge command period */
23 u32 t_ras
; /* Active to precharge command period */
24 u32 t_srex
; /* Self-refresh exit time */
26 u32 t_wr
; /* Write recovery time */
27 u32 t_rc
; /* Active to active command period */
28 u32 t_rfc
; /* Auto-refresh period */
29 u32 t_xsr
; /* Exit self-refresh to active command time */
30 u32 t_rrd
; /* Active bank A to active bank B latency */
31 u32 t_mrd
; /* Load mode register to active command time */
32 u32 t_cdlr
; /* Last data in to read command time */
34 u32 extended_wait
; /* time for static memory rd/wr transfers */
36 u32 config0
; /* Configuration information for the SDRAM */
37 u32 rascas0
; /* RAS and CAS latencies for the SDRAM */
39 u32 config1
; /* Configuration information for the SDRAM */
40 u32 rascas1
; /* RAS and CAS latencies for the SDRAM */
43 u32 config
; /* Static memory configuration */
44 u32 waitwen
; /* Delay from chip select to write enable */
45 u32 waitoen
; /* Delay to output enable */
46 u32 waitrd
; /* Delay to a read access */
47 u32 waitpage
; /* Delay for async page mode read */
48 u32 waitwr
; /* Delay to a write access */
49 u32 waitturn
; /* Number of bus turnaround cycles */
54 u32 control
; /* Control register for AHB */
55 u32 status
; /* Status register for AHB */
56 u32 timeout
; /* Timeout register for AHB */
61 /* Static Memory Configuration Register bits */
62 #define EMC_STAT_CONFIG_WP (1 << 20)
63 #define EMC_STAT_CONFIG_EW (1 << 8)
64 #define EMC_STAT_CONFIG_PB (1 << 7)
65 #define EMC_STAT_CONFIG_PC (1 << 6)
66 #define EMC_STAT_CONFIG_PM (1 << 3)
67 #define EMC_STAT_CONFIG_32BIT (2 << 0)
68 #define EMC_STAT_CONFIG_16BIT (1 << 0)
69 #define EMC_STAT_CONFIG_8BIT (0 << 0)
71 /* Static Memory Delay Registers */
72 #define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
73 #define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F)
74 #define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
75 #define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
76 #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
77 #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
79 #endif /* _LPC32XX_EMC_H */