arch/arm/include/asm/arch-ls102xa/config.h

   1 /*
   2  * Copyright 2014, Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
   8 #define _ASM_ARMV7_LS102XA_CONFIG_
   9
  10 #define CONFIG_SYS_CACHELINE_SIZE               64
  11
  12 #define OCRAM_BASE_ADDR                         0x10000000
  13 #define OCRAM_SIZE                              0x00020000
  14
  15 #define CONFIG_SYS_IMMR                         0x01000000
  16
  17 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  18 #define CONFIG_SYS_CCI400_ADDR                  (CONFIG_SYS_IMMR + 0x00180000)
  19 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x00530000)
  20 #define CONFIG_SYS_FSL_ESDHC_ADDR               (CONFIG_SYS_IMMR + 0x00560000)
  21 #define CONFIG_SYS_FSL_SCFG_ADDR                (CONFIG_SYS_IMMR + 0x00570000)
  22 #define CONFIG_SYS_FSL_SERDES_ADDR              (CONFIG_SYS_IMMR + 0x00ea0000)
  23 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
  24 #define CONFIG_SYS_FSL_LS1_CLK_ADDR             (CONFIG_SYS_IMMR + 0x00ee1000)
  25 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011c0500)
  26 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011d0500)
  27 #define CONFIG_SYS_DCU_ADDR                     (CONFIG_SYS_IMMR + 0x01ce0000)
  28
  29 #define CONFIG_SYS_TSEC1_OFFSET                 0x01d10000
  30 #define CONFIG_SYS_TSEC2_OFFSET                 0x01d50000
  31 #define CONFIG_SYS_TSEC3_OFFSET                 0x01d90000
  32 #define CONFIG_SYS_MDIO1_OFFSET                 0x01d24000
  33
  34 #define TSEC_BASE_ADDR  (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  35 #define MDIO_BASE_ADDR  (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
  36
  37 #define SCTR_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01b00000)
  38
  39 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01180000)
  40 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01190000)
  41 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011a0000)
  42
  43 #define WDOG1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01ad0000)
  44
  45 #define QSPI0_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x00550000)
  46 #define DSPI1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01100000)
  47
  48 #define LPUART_BASE                             (CONFIG_SYS_IMMR + 0x01950000)
  49
  50 #ifdef CONFIG_DDR_SPD
  51 #define CONFIG_SYS_FSL_DDR_BE
  52 #define CONFIG_VERY_BIG_RAM
  53 #ifdef CONFIG_SYS_FSL_DDR4
  54 #define CONFIG_SYS_FSL_DDRC_GEN4
  55 #else
  56 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
  57 #endif
  58 #define CONFIG_SYS_FSL_DDR
  59 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE          ((phys_size_t)2 << 30)
  60 #define CONFIG_MAX_MEM_MAPPED                   CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
  61 #endif
  62
  63 #define CONFIG_SYS_FSL_IFC_BE
  64 #define CONFIG_SYS_FSL_ESDHC_BE
  65 #define CONFIG_SYS_FSL_WDOG_BE
  66 #define CONFIG_SYS_FSL_DSPI_BE
  67 #define CONFIG_SYS_FSL_QSPI_BE
  68 #define CONFIG_SYS_FSL_DCU_BE
  69
  70 #define DCU_LAYER_MAX_NUM                       16
  71
  72 #define CONFIG_SYS_FSL_SRDS_1
  73
  74 #ifdef CONFIG_LS102XA
  75 #define CONFIG_MAX_CPUS                         2
  76 #define CONFIG_SYS_FSL_IFC_BANK_COUNT           8
  77 #define CONFIG_NUM_DDR_CONTROLLERS              1
  78 #define CONFIG_SYS_FSL_DDR_VER                  FSL_DDR_VER_5_0
  79 #else
  80 #error SoC not defined
  81 #endif
  82
  83 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */