arch/arm/include/asm/arch-mx25/imx-regs.h

   1 /*
   2  * Copyright (C) 2009, DENX Software Engineering
   3  * Author: John Rigby <jcrigby@gmail.com
   4  *
   5  *   Based on arch-mx31/imx-regs.h
   6  *      Copyright (C) 2009 Ilya Yanok,
   7  *              Emcraft Systems <yanok@emcraft.com>
   8  *   and arch-mx27/imx-regs.h
   9  *      Copyright (C) 2007 Pengutronix,
  10  *              Sascha Hauer <s.hauer@pengutronix.de>
  11  *      Copyright (C) 2009 Ilya Yanok,
  12  *              Emcraft Systems <yanok@emcraft.com>
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef _IMX_REGS_H
  18 #define _IMX_REGS_H
  19
  20 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  21 #include <asm/types.h>
  22
  23 /* Clock Control Module (CCM) registers */
  24 struct ccm_regs {
  25         u32 mpctl;      /* Core PLL Control */
  26         u32 upctl;      /* USB PLL Control */
  27         u32 cctl;       /* Clock Control */
  28         u32 cgr0;       /* Clock Gating Control 0 */
  29         u32 cgr1;       /* Clock Gating Control 1 */
  30         u32 cgr2;       /* Clock Gating Control 2 */
  31         u32 pcdr[4];    /* PER Clock Dividers */
  32         u32 rcsr;       /* CCM Status */
  33         u32 crdr;       /* CCM Reset and Debug */
  34         u32 dcvr0;      /* DPTC Comparator Value 0 */
  35         u32 dcvr1;      /* DPTC Comparator Value 1 */
  36         u32 dcvr2;      /* DPTC Comparator Value 2 */
  37         u32 dcvr3;      /* DPTC Comparator Value 3 */
  38         u32 ltr0;       /* Load Tracking 0 */
  39         u32 ltr1;       /* Load Tracking 1 */
  40         u32 ltr2;       /* Load Tracking 2 */
  41         u32 ltr3;       /* Load Tracking 3 */
  42         u32 ltbr0;      /* Load Tracking Buffer 0 */
  43         u32 ltbr1;      /* Load Tracking Buffer 1 */
  44         u32 pcmr0;      /* Power Management Control 0 */
  45         u32 pcmr1;      /* Power Management Control 1 */
  46         u32 pcmr2;      /* Power Management Control 2 */
  47         u32 mcr;        /* Miscellaneous Control */
  48         u32 lpimr0;     /* Low Power Interrupt Mask 0 */
  49         u32 lpimr1;     /* Low Power Interrupt Mask 1 */
  50 };
  51
  52 /* Enhanced SDRAM Controller (ESDRAMC) registers */
  53 struct esdramc_regs {
  54         u32 ctl0;       /* control 0 */
  55         u32 cfg0;       /* configuration 0 */
  56         u32 ctl1;       /* control 1 */
  57         u32 cfg1;       /* configuration 1 */
  58         u32 misc;       /* miscellaneous */
  59         u32 pad[3];
  60         u32 cdly1;      /* Delay Line 1 configuration debug */
  61         u32 cdly2;      /* delay line 2 configuration debug */
  62         u32 cdly3;      /* delay line 3 configuration debug */
  63         u32 cdly4;      /* delay line 4 configuration debug */
  64         u32 cdly5;      /* delay line 5 configuration debug */
  65         u32 cdlyl;      /* delay line cycle length debug */
  66 };
  67
  68 /* General Purpose Timer (GPT) registers */
  69 struct gpt_regs {
  70         u32 ctrl;       /* control */
  71         u32 pre;        /* prescaler */
  72         u32 stat;       /* status */
  73         u32 intr;       /* interrupt */
  74         u32 cmp[3];     /* output compare 1-3 */
  75         u32 capt[2];    /* input capture 1-2 */
  76         u32 counter;    /* counter */
  77 };
  78
  79 /* Watchdog Timer (WDOG) registers */
  80 struct wdog_regs {
  81         u16 wcr;        /* Control */
  82         u16 wsr;        /* Service */
  83         u16 wrsr;       /* Reset Status */
  84         u16 wicr;       /* Interrupt Control */
  85         u16 wmcr;       /* Misc Control */
  86 };
  87
  88 /* IIM control registers */
  89 struct iim_regs {
  90         u32 iim_stat;
  91         u32 iim_statm;
  92         u32 iim_err;
  93         u32 iim_emask;
  94         u32 iim_fctl;
  95         u32 iim_ua;
  96         u32 iim_la;
  97         u32 iim_sdat;
  98         u32 iim_prev;
  99         u32 iim_srev;
 100         u32 iim_prg_p;
 101         u32 iim_scs0;
 102         u32 iim_scs1;
 103         u32 iim_scs2;
 104         u32 iim_scs3;
 105         u32 res1[0x1f1];
 106         struct fuse_bank {
 107                 u32 fuse_regs[0x20];
 108                 u32 fuse_rsvd[0xe0];
 109         } bank[3];
 110 };
 111
 112 struct fuse_bank0_regs {
 113         u32 fuse0_7[8];
 114         u32 uid[8];
 115         u32 fuse16_25[0xa];
 116         u32 mac_addr[6];
 117 };
 118
 119 struct fuse_bank1_regs {
 120         u32 fuse0_21[0x16];
 121         u32 usr5;
 122         u32 fuse23_29[7];
 123         u32 usr6[2];
 124 };
 125
 126 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
 127 struct max_regs {
 128         u32 mpr0;
 129         u32 pad00[3];
 130         u32 sgpcr0;
 131         u32 pad01[59];
 132         u32 mpr1;
 133         u32 pad02[3];
 134         u32 sgpcr1;
 135         u32 pad03[59];
 136         u32 mpr2;
 137         u32 pad04[3];
 138         u32 sgpcr2;
 139         u32 pad05[59];
 140         u32 mpr3;
 141         u32 pad06[3];
 142         u32 sgpcr3;
 143         u32 pad07[59];
 144         u32 mpr4;
 145         u32 pad08[3];
 146         u32 sgpcr4;
 147         u32 pad09[251];
 148         u32 mgpcr0;
 149         u32 pad10[63];
 150         u32 mgpcr1;
 151         u32 pad11[63];
 152         u32 mgpcr2;
 153         u32 pad12[63];
 154         u32 mgpcr3;
 155         u32 pad13[63];
 156         u32 mgpcr4;
 157 };
 158
 159 /* AHB <-> IP-Bus Interface (AIPS) */
 160 struct aips_regs {
 161         u32 mpr_0_7;
 162         u32 mpr_8_15;
 163 };
 164 /* LCD controller registers */
 165 struct lcdc_regs {
 166         u32 lssar;      /* Screen Start Address */
 167         u32 lsr;        /* Size */
 168         u32 lvpwr;      /* Virtual Page Width */
 169         u32 lcpr;       /* Cursor Position */
 170         u32 lcwhb;      /* Cursor Width Height and Blink */
 171         u32 lccmr;      /* Color Cursor Mapping */
 172         u32 lpcr;       /* Panel Configuration */
 173         u32 lhcr;       /* Horizontal Configuration */
 174         u32 lvcr;       /* Vertical Configuration */
 175         u32 lpor;       /* Panning Offset */
 176         u32 lscr;       /* Sharp Configuration */
 177         u32 lpccr;      /* PWM Contrast Control */
 178         u32 ldcr;       /* DMA Control */
 179         u32 lrmcr;      /* Refresh Mode Control */
 180         u32 licr;       /* Interrupt Configuration */
 181         u32 lier;       /* Interrupt Enable */
 182         u32 lisr;       /* Interrupt Status */
 183         u32 res0[3];
 184         u32 lgwsar;     /* Graphic Window Start Address */
 185         u32 lgwsr;      /* Graphic Window Size */
 186         u32 lgwvpwr;    /* Graphic Window Virtual Page Width Regist */
 187         u32 lgwpor;     /* Graphic Window Panning Offset */
 188         u32 lgwpr;      /* Graphic Window Position */
 189         u32 lgwcr;      /* Graphic Window Control */
 190         u32 lgwdcr;     /* Graphic Window DMA Control */
 191         u32 res1[5];
 192         u32 lauscr;     /* AUS Mode Control */
 193         u32 lausccr;    /* AUS mode Cursor Control */
 194         u32 res2[31 + 64*7];
 195         u32 bglut;      /* Background Lookup Table */
 196         u32 gwlut;      /* Graphic Window Lookup Table */
 197 };
 198
 199 /* Wireless External Interface Module Registers */
 200 struct weim_regs {
 201         u32 cscr0u;     /* Chip Select 0 Upper Register */
 202         u32 cscr0l;     /* Chip Select 0 Lower Register */
 203         u32 cscr0a;     /* Chip Select 0 Addition Register */
 204         u32 pad0;
 205         u32 cscr1u;     /* Chip Select 1 Upper Register */
 206         u32 cscr1l;     /* Chip Select 1 Lower Register */
 207         u32 cscr1a;     /* Chip Select 1 Addition Register */
 208         u32 pad1;
 209         u32 cscr2u;     /* Chip Select 2 Upper Register */
 210         u32 cscr2l;     /* Chip Select 2 Lower Register */
 211         u32 cscr2a;     /* Chip Select 2 Addition Register */
 212         u32 pad2;
 213         u32 cscr3u;     /* Chip Select 3 Upper Register */
 214         u32 cscr3l;     /* Chip Select 3 Lower Register */
 215         u32 cscr3a;     /* Chip Select 3 Addition Register */
 216         u32 pad3;
 217         u32 cscr4u;     /* Chip Select 4 Upper Register */
 218         u32 cscr4l;     /* Chip Select 4 Lower Register */
 219         u32 cscr4a;     /* Chip Select 4 Addition Register */
 220         u32 pad4;
 221         u32 cscr5u;     /* Chip Select 5 Upper Register */
 222         u32 cscr5l;     /* Chip Select 5 Lower Register */
 223         u32 cscr5a;     /* Chip Select 5 Addition Register */
 224         u32 pad5;
 225         u32 wcr;        /* WEIM Configuration Register */
 226 };
 227
 228 /* Multi-Master Memory Interface */
 229 struct m3if_regs {
 230         u32 ctl;        /* Control Register */
 231         u32 wcfg0;      /* Watermark Configuration Register 0 */
 232         u32 wcfg1;      /* Watermark Configuration Register1 */
 233         u32 wcfg2;      /* Watermark Configuration Register2 */
 234         u32 wcfg3;      /* Watermark Configuration Register 3 */
 235         u32 wcfg4;      /* Watermark Configuration Register 4 */
 236         u32 wcfg5;      /* Watermark Configuration Register 5 */
 237         u32 wcfg6;      /* Watermark Configuration Register 6 */
 238         u32 wcfg7;      /* Watermark Configuration Register 7 */
 239         u32 wcsr;       /* Watermark Control and Status Register */
 240         u32 scfg0;      /* Snooping Configuration Register 0 */
 241         u32 scfg1;      /* Snooping Configuration Register 1 */
 242         u32 scfg2;      /* Snooping Configuration Register 2 */
 243         u32 ssr0;       /* Snooping Status Register 0 */
 244         u32 ssr1;       /* Snooping Status Register 1 */
 245         u32 res0;
 246         u32 mlwe0;      /* Master Lock WEIM CS0 Register */
 247         u32 mlwe1;      /* Master Lock WEIM CS1 Register */
 248         u32 mlwe2;      /* Master Lock WEIM CS2 Register */
 249         u32 mlwe3;      /* Master Lock WEIM CS3 Register */
 250         u32 mlwe4;      /* Master Lock WEIM CS4 Register */
 251         u32 mlwe5;      /* Master Lock WEIM CS5 Register */
 252 };
 253
 254 /* Pulse width modulation */
 255 struct pwm_regs {
 256         u32 cr; /* Control Register */
 257         u32 sr; /* Status Register */
 258         u32 ir; /* Interrupt Register */
 259         u32 sar;        /* Sample Register */
 260         u32 pr; /* Period Register */
 261         u32 cnr;        /* Counter Register */
 262 };
 263
 264 /* Enhanced Periodic Interrupt Timer */
 265 struct epit_regs {
 266         u32 cr; /* Control register */
 267         u32 sr; /* Status register */
 268         u32 lr; /* Load register */
 269         u32 cmpr;       /* Compare register */
 270         u32 cnr;        /* Counter register */
 271 };
 272
 273 /* CSPI registers */
 274 struct cspi_regs {
 275         u32 rxdata;
 276         u32 txdata;
 277         u32 ctrl;
 278         u32 intr;
 279         u32 dma;
 280         u32 stat;
 281         u32 period;
 282         u32 test;
 283 };
 284
 285 #endif
 286
 287 #define ARCH_MXC
 288
 289 /* AIPS 1 */
 290 #define IMX_AIPS1_BASE          (0x43F00000)
 291 #define IMX_MAX_BASE            (0x43F04000)
 292 #define IMX_CLKCTL_BASE         (0x43F08000)
 293 #define IMX_ETB_SLOT4_BASE      (0x43F0C000)
 294 #define IMX_ETB_SLOT5_BASE      (0x43F10000)
 295 #define IMX_ECT_CTIO_BASE       (0x43F18000)
 296 #define I2C1_BASE_ADDR          (0x43F80000)
 297 #define I2C3_BASE_ADDR          (0x43F84000)
 298 #define IMX_CAN1_BASE           (0x43F88000)
 299 #define IMX_CAN2_BASE           (0x43F8C000)
 300 #define UART1_BASE              (0x43F90000)
 301 #define UART2_BASE              (0x43F94000)
 302 #define I2C2_BASE_ADDR          (0x43F98000)
 303 #define IMX_OWIRE_BASE          (0x43F9C000)
 304 #define IMX_CSPI1_BASE          (0x43FA4000)
 305 #define IMX_KPP_BASE            (0x43FA8000)
 306 #define IMX_IOPADMUX_BASE       (0x43FAC000)
 307 #define IOMUXC_BASE_ADDR        IMX_IOPADMUX_BASE
 308 #define IMX_IOPADCTL_BASE       (0x43FAC22C)
 309 #define IMX_IOPADGRPCTL_BASE    (0x43FAC418)
 310 #define IMX_IOPADINPUTSEL_BASE  (0x43FAC460)
 311 #define IMX_AUDMUX_BASE         (0x43FB0000)
 312 #define IMX_ECT_IP1_BASE        (0x43FB8000)
 313 #define IMX_ECT_IP2_BASE        (0x43FBC000)
 314
 315 /* SPBA */
 316 #define IMX_SPBA_BASE           (0x50000000)
 317 #define IMX_CSPI3_BASE          (0x50004000)
 318 #define UART4_BASE              (0x50008000)
 319 #define UART3_BASE              (0x5000C000)
 320 #define IMX_CSPI2_BASE          (0x50010000)
 321 #define IMX_SSI2_BASE           (0x50014000)
 322 #define IMX_ESAI_BASE           (0x50018000)
 323 #define IMX_ATA_DMA_BASE        (0x50020000)
 324 #define IMX_SIM1_BASE           (0x50024000)
 325 #define IMX_SIM2_BASE           (0x50028000)
 326 #define UART5_BASE              (0x5002C000)
 327 #define IMX_TSC_BASE            (0x50030000)
 328 #define IMX_SSI1_BASE           (0x50034000)
 329 #define IMX_FEC_BASE            (0x50038000)
 330 #define IMX_SPBA_CTRL_BASE      (0x5003C000)
 331
 332 /* AIPS 2 */
 333 #define IMX_AIPS2_BASE          (0x53F00000)
 334 #define IMX_CCM_BASE            (0x53F80000)
 335 #define IMX_GPT4_BASE           (0x53F84000)
 336 #define IMX_GPT3_BASE           (0x53F88000)
 337 #define IMX_GPT2_BASE           (0x53F8C000)
 338 #define IMX_GPT1_BASE           (0x53F90000)
 339 #define IMX_EPIT1_BASE          (0x53F94000)
 340 #define IMX_EPIT2_BASE          (0x53F98000)
 341 #define IMX_GPIO4_BASE          (0x53F9C000)
 342 #define IMX_PWM2_BASE           (0x53FA0000)
 343 #define IMX_GPIO3_BASE          (0x53FA4000)
 344 #define IMX_PWM3_BASE           (0x53FA8000)
 345 #define IMX_SCC_BASE            (0x53FAC000)
 346 #define IMX_SCM_BASE            (0x53FAE000)
 347 #define IMX_SMN_BASE            (0x53FAF000)
 348 #define IMX_RNGD_BASE           (0x53FB0000)
 349 #define IMX_MMC_SDHC1_BASE      (0x53FB4000)
 350 #define IMX_MMC_SDHC2_BASE      (0x53FB8000)
 351 #define IMX_LCDC_BASE           (0x53FBC000)
 352 #define IMX_SLCDC_BASE          (0x53FC0000)
 353 #define IMX_PWM4_BASE           (0x53FC8000)
 354 #define IMX_GPIO1_BASE          (0x53FCC000)
 355 #define IMX_GPIO2_BASE          (0x53FD0000)
 356 #define IMX_SDMA_BASE           (0x53FD4000)
 357 #define IMX_WDT_BASE            (0x53FDC000)
 358 #define IMX_PWM1_BASE           (0x53FE0000)
 359 #define IMX_RTIC_BASE           (0x53FEC000)
 360 #define IMX_IIM_BASE            (0x53FF0000)
 361 #define IIM_BASE_ADDR           IMX_IIM_BASE
 362 #define IMX_USB_BASE            (0x53FF4000)
 363 #define IMX_USB_PORT_OFFSET     0x200
 364 #define IMX_CSI_BASE            (0x53FF8000)
 365 #define IMX_DRYICE_BASE         (0x53FFC000)
 366
 367 #define IMX_ARM926_ROMPATCH     (0x60000000)
 368 #define IMX_ARM926_ASIC         (0x68000000)
 369
 370 /* 128K Internal Static RAM */
 371 #define IMX_RAM_BASE            (0x78000000)
 372 #define IMX_RAM_SIZE            (128 * 1024)
 373
 374 /* SDRAM BANKS */
 375 #define IMX_SDRAM_BANK0_BASE    (0x80000000)
 376 #define IMX_SDRAM_BANK1_BASE    (0x90000000)
 377
 378 #define IMX_WEIM_CS0            (0xA0000000)
 379 #define IMX_WEIM_CS1            (0xA8000000)
 380 #define IMX_WEIM_CS2            (0xB0000000)
 381 #define IMX_WEIM_CS3            (0xB2000000)
 382 #define IMX_WEIM_CS4            (0xB4000000)
 383 #define IMX_ESDRAMC_BASE        (0xB8001000)
 384 #define IMX_WEIM_CTRL_BASE      (0xB8002000)
 385 #define IMX_M3IF_CTRL_BASE      (0xB8003000)
 386 #define IMX_EMI_CTRL_BASE       (0xB8004000)
 387
 388 /* NAND Flash Controller */
 389 #define IMX_NFC_BASE            (0xBB000000)
 390 #define NFC_BASE_ADDR           IMX_NFC_BASE
 391
 392 /* CCM bitfields */
 393 #define CCM_PLL_MFI_SHIFT       10
 394 #define CCM_PLL_MFI_MASK        0xf
 395 #define CCM_PLL_MFN_SHIFT       0
 396 #define CCM_PLL_MFN_MASK        0x3ff
 397 #define CCM_PLL_MFD_SHIFT       16
 398 #define CCM_PLL_MFD_MASK        0x3ff
 399 #define CCM_PLL_PD_SHIFT        26
 400 #define CCM_PLL_PD_MASK         0xf
 401 #define CCM_CCTL_ARM_DIV_SHIFT  30
 402 #define CCM_CCTL_ARM_DIV_MASK   3
 403 #define CCM_CCTL_AHB_DIV_SHIFT  28
 404 #define CCM_CCTL_AHB_DIV_MASK   3
 405 #define CCM_CCTL_ARM_SRC        (1 << 14)
 406 #define CCM_CGR1_GPT1           (1 << 19)
 407 #define CCM_PERCLK_REG(clk)     (clk / 4)
 408 #define CCM_PERCLK_SHIFT(clk)   (8 * (clk % 4))
 409 #define CCM_PERCLK_MASK         0x3f
 410 #define CCM_RCSR_NF_16BIT_SEL   (1 << 14)
 411 #define CCM_RCSR_NF_PS(v)       ((v >> 26) & 3)
 412 #define CCM_CRDR_BT_UART_SRC_SHIFT      29
 413 #define CCM_CRDR_BT_UART_SRC_MASK       7
 414
 415 /* ESDRAM Controller register bitfields */
 416 #define ESDCTL_PRCT(x)          (((x) & 0x3f) << 0)
 417 #define ESDCTL_BL               (1 << 7)
 418 #define ESDCTL_FP               (1 << 8)
 419 #define ESDCTL_PWDT(x)          (((x) & 3) << 10)
 420 #define ESDCTL_SREFR(x)         (((x) & 7) << 13)
 421 #define ESDCTL_DSIZ_16_UPPER    (0 << 16)
 422 #define ESDCTL_DSIZ_16_LOWER    (1 << 16)
 423 #define ESDCTL_DSIZ_32          (2 << 16)
 424 #define ESDCTL_COL8             (0 << 20)
 425 #define ESDCTL_COL9             (1 << 20)
 426 #define ESDCTL_COL10            (2 << 20)
 427 #define ESDCTL_ROW11            (0 << 24)
 428 #define ESDCTL_ROW12            (1 << 24)
 429 #define ESDCTL_ROW13            (2 << 24)
 430 #define ESDCTL_ROW14            (3 << 24)
 431 #define ESDCTL_ROW15            (4 << 24)
 432 #define ESDCTL_SP               (1 << 27)
 433 #define ESDCTL_SMODE_NORMAL     (0 << 28)
 434 #define ESDCTL_SMODE_PRECHARGE  (1 << 28)
 435 #define ESDCTL_SMODE_AUTO_REF   (2 << 28)
 436 #define ESDCTL_SMODE_LOAD_MODE  (3 << 28)
 437 #define ESDCTL_SMODE_MAN_REF    (4 << 28)
 438 #define ESDCTL_SDE              (1 << 31)
 439
 440 #define ESDCFG_TRC(x)           (((x) & 0xf) << 0)
 441 #define ESDCFG_TRCD(x)          (((x) & 0x7) << 4)
 442 #define ESDCFG_TCAS(x)          (((x) & 0x3) << 8)
 443 #define ESDCFG_TRRD(x)          (((x) & 0x3) << 10)
 444 #define ESDCFG_TRAS(x)          (((x) & 0x7) << 12)
 445 #define ESDCFG_TWR              (1 << 15)
 446 #define ESDCFG_TMRD(x)          (((x) & 0x3) << 16)
 447 #define ESDCFG_TRP(x)           (((x) & 0x3) << 18)
 448 #define ESDCFG_TWTR             (1 << 20)
 449 #define ESDCFG_TXP(x)           (((x) & 0x3) << 21)
 450
 451 #define ESDMISC_RST             (1 << 1)
 452 #define ESDMISC_MDDREN          (1 << 2)
 453 #define ESDMISC_MDDR_DL_RST     (1 << 3)
 454 #define ESDMISC_MDDR_MDIS       (1 << 4)
 455 #define ESDMISC_LHD             (1 << 5)
 456 #define ESDMISC_MA10_SHARE      (1 << 6)
 457 #define ESDMISC_SDRAM_RDY       (1 << 31)
 458
 459 /* GPT bits */
 460 #define GPT_CTRL_SWR            (1 << 15)       /* Software reset */
 461 #define GPT_CTRL_FRR            (1 << 9)        /* Freerun / restart */
 462 #define GPT_CTRL_CLKSOURCE_32   (4 << 6)        /* Clock source */
 463 #define GPT_CTRL_TEN            1               /* Timer enable */
 464
 465 /* WDOG enable */
 466 #define WCR_WDE                 0x04
 467 #define WSR_UNLOCK1             0x5555
 468 #define WSR_UNLOCK2             0xAAAA
 469
 470 /* MAX bits */
 471 #define MAX_MGPCR_AULB(x)       (((x) & 0x7) << 0)
 472
 473 /* M3IF bits */
 474 #define M3IF_CTL_MRRP(x)        (((x) & 0xff) << 0)
 475
 476 /* WEIM bits */
 477 /* 13 fields of the upper CS control register */
 478 #define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
 479                 cnc, wsc, ew, wws, edc) \
 480                 ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
 481                 (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
 482                 (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
 483 /* 12 fields of the lower CS control register */
 484 #define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
 485                 csa, ebc, dsz, csn, psr, cre, wrap, csen) \
 486                 ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
 487                 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
 488                 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
 489 /* 14 fields of the additional CS control register */
 490 #define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
 491                 wwu, age, cnc2, fce) \
 492                 ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
 493                 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
 494                 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
 495                 (age) << 2 | (cnc2) << 1 | (fce) << 0)
 496
 497 /* Names used in GPIO driver */
 498 #define GPIO1_BASE_ADDR         IMX_GPIO1_BASE
 499 #define GPIO2_BASE_ADDR         IMX_GPIO2_BASE
 500 #define GPIO3_BASE_ADDR         IMX_GPIO3_BASE
 501 #define GPIO4_BASE_ADDR         IMX_GPIO4_BASE
 502
 503 /*
 504  * CSPI register definitions
 505  */
 506 #define MXC_CSPI
 507 #define MXC_CSPICTRL_EN         (1 << 0)
 508 #define MXC_CSPICTRL_MODE       (1 << 1)
 509 #define MXC_CSPICTRL_XCH        (1 << 2)
 510 #define MXC_CSPICTRL_SMC        (1 << 3)
 511 #define MXC_CSPICTRL_POL        (1 << 4)
 512 #define MXC_CSPICTRL_PHA        (1 << 5)
 513 #define MXC_CSPICTRL_SSCTL      (1 << 6)
 514 #define MXC_CSPICTRL_SSPOL      (1 << 7)
 515 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
 516 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
 517 #define MXC_CSPICTRL_DATARATE(x)        (((x) & 0x7) << 16)
 518 #define MXC_CSPICTRL_TC         (1 << 7)
 519 #define MXC_CSPICTRL_RXOVF      (1 << 6)
 520 #define MXC_CSPICTRL_MAXBITS    0xfff
 521 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
 522 #define MAX_SPI_BYTES   4
 523
 524 #define MXC_SPI_BASE_ADDRESSES \
 525         IMX_CSPI1_BASE, \
 526         IMX_CSPI2_BASE, \
 527         IMX_CSPI3_BASE
 528
 529 #endif                          /* _IMX_REGS_H */