arch/arm/include/asm/arch-mx27/imx-regs.h

   1 /*
   2  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   3  * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _IMX_REGS_H
  25 #define _IMX_REGS_H
  26
  27 #ifndef __ASSEMBLY__
  28
  29 extern void imx_gpio_mode (int gpio_mode);
  30
  31 #ifdef CONFIG_MXC_UART
  32 extern void mx27_uart1_init_pins(void);
  33 #endif /* CONFIG_MXC_UART */
  34
  35 #ifdef CONFIG_FEC_MXC
  36 extern void mx27_fec_init_pins(void);
  37 #endif /* CONFIG_FEC_MXC */
  38
  39 #ifdef CONFIG_MXC_MMC
  40 extern void mx27_sd1_init_pins(void);
  41 extern void mx27_sd2_init_pins(void);
  42 #endif /* CONFIG_MXC_MMC */
  43
  44 /* AIPI */
  45 struct aipi_regs {
  46         u32 psr0;
  47         u32 psr1;
  48 };
  49
  50 /* System Control */
  51 struct system_control_regs {
  52         u32 res[5];
  53         u32 fmcr;
  54         u32 gpcr;
  55         u32 wbcr;
  56         u32 dscr1;
  57         u32 dscr2;
  58         u32 dscr3;
  59         u32 dscr4;
  60         u32 dscr5;
  61         u32 dscr6;
  62         u32 dscr7;
  63         u32 dscr8;
  64         u32 dscr9;
  65         u32 dscr10;
  66         u32 dscr11;
  67         u32 dscr12;
  68         u32 dscr13;
  69         u32 pscr;
  70         u32 pmcr;
  71         u32 res1;
  72         u32 dcvr0;
  73         u32 dcvr1;
  74         u32 dcvr2;
  75         u32 dcvr3;
  76 };
  77
  78 /* Chip Select Registers */
  79 struct weim_regs {
  80         u32 cs0u;       /* Chip Select 0 Upper Register */
  81         u32 cs0l;       /* Chip Select 0 Lower Register */
  82         u32 cs0a;       /* Chip Select 0 Addition Register */
  83         u32 pad0;
  84         u32 cs1u;       /* Chip Select 1 Upper Register */
  85         u32 cs1l;       /* Chip Select 1 Lower Register */
  86         u32 cs1a;       /* Chip Select 1 Addition Register */
  87         u32 pad1;
  88         u32 cs2u;       /* Chip Select 2 Upper Register */
  89         u32 cs2l;       /* Chip Select 2 Lower Register */
  90         u32 cs2a;       /* Chip Select 2 Addition Register */
  91         u32 pad2;
  92         u32 cs3u;       /* Chip Select 3 Upper Register */
  93         u32 cs3l;       /* Chip Select 3 Lower Register */
  94         u32 cs3a;       /* Chip Select 3 Addition Register */
  95         u32 pad3;
  96         u32 cs4u;       /* Chip Select 4 Upper Register */
  97         u32 cs4l;       /* Chip Select 4 Lower Register */
  98         u32 cs4a;       /* Chip Select 4 Addition Register */
  99         u32 pad4;
 100         u32 cs5u;       /* Chip Select 5 Upper Register */
 101         u32 cs5l;       /* Chip Select 5 Lower Register */
 102         u32 cs5a;       /* Chip Select 5 Addition Register */
 103         u32 pad5;
 104         u32 eim;        /* WEIM Configuration Register */
 105 };
 106
 107 /* SDRAM Controller registers */
 108 struct esdramc_regs {
 109 /* Enhanced SDRAM Control Register 0 */
 110         u32 esdctl0;
 111 /* Enhanced SDRAM Configuration Register 0 */
 112         u32 esdcfg0;
 113 /* Enhanced SDRAM Control Register 1 */
 114         u32 esdctl1;
 115 /* Enhanced SDRAM Configuration Register 1 */
 116         u32 esdcfg1;
 117 /* Enhanced SDRAM Miscellanious Register */
 118         u32 esdmisc;
 119 };
 120
 121 /* Watchdog Registers*/
 122 struct wdog_regs {
 123         u32 wcr;
 124         u32 wsr;
 125         u32 wstr;
 126 };
 127
 128 /* PLL registers */
 129 struct pll_regs {
 130         u32 cscr;       /* Clock Source Control Register */
 131         u32 mpctl0;     /* MCU PLL Control Register 0 */
 132         u32 mpctl1;     /* MCU PLL Control Register 1 */
 133         u32 spctl0;     /* System PLL Control Register 0 */
 134         u32 spctl1;     /* System PLL Control Register 1 */
 135         u32 osc26mctl;  /* Oscillator 26M Register */
 136         u32 pcdr0;      /* Peripheral Clock Divider Register 0 */
 137         u32 pcdr1;      /* Peripheral Clock Divider Register 1 */
 138         u32 pccr0;      /* Peripheral Clock Control Register 0 */
 139         u32 pccr1;      /* Peripheral Clock Control Register 1 */
 140         u32 ccsr;       /* Clock Control Status Register */
 141 };
 142
 143 /*
 144  * Definitions for the clocksource registers
 145  */
 146 struct gpt_regs {
 147         u32 gpt_tctl;
 148         u32 gpt_tprer;
 149         u32 gpt_tcmp;
 150         u32 gpt_tcr;
 151         u32 gpt_tcn;
 152         u32 gpt_tstat;
 153 };
 154
 155 /*
 156  *  GPIO Module and I/O Multiplexer
 157  */
 158 #define PORTA 0
 159 #define PORTB 1
 160 #define PORTC 2
 161 #define PORTD 3
 162 #define PORTE 4
 163 #define PORTF 5
 164
 165 struct gpio_regs {
 166         struct {
 167                 u32 ddir;
 168                 u32 ocr1;
 169                 u32 ocr2;
 170                 u32 iconfa1;
 171                 u32 iconfa2;
 172                 u32 iconfb1;
 173                 u32 iconfb2;
 174                 u32 dr;
 175                 u32 gius;
 176                 u32 ssr;
 177                 u32 icr1;
 178                 u32 icr2;
 179                 u32 imr;
 180                 u32 isr;
 181                 u32 gpr;
 182                 u32 swr;
 183                 u32 puen;
 184                 u32 res[0x2f];
 185         } port[6];
 186 };
 187
 188 /* IIM Control Registers */
 189 struct iim_regs {
 190         u32 iim_stat;
 191         u32 iim_statm;
 192         u32 iim_err;
 193         u32 iim_emask;
 194         u32 iim_fctl;
 195         u32 iim_ua;
 196         u32 iim_la;
 197         u32 iim_sdat;
 198         u32 iim_prev;
 199         u32 iim_srev;
 200         u32 iim_prog_p;
 201         u32 iim_scs0;
 202         u32 iim_scs1;
 203         u32 iim_scs2;
 204         u32 iim_scs3;
 205         u32 res[0x1f1];
 206         struct fuse_bank {
 207                 u32 fuse_regs[0x20];
 208                 u32 fuse_rsvd[0xe0];
 209         } bank[1];
 210 };
 211
 212 struct fuse_bank0_regs {
 213         u32 fuse0_3[5];
 214         u32 mac_addr[6];
 215         u32 fuse10_31[0x16];
 216 };
 217
 218 #endif
 219
 220 #define IMX_IO_BASE             0x10000000
 221
 222 #define IMX_AIPI1_BASE          (0x00000 + IMX_IO_BASE)
 223 #define IMX_WDT_BASE            (0x02000 + IMX_IO_BASE)
 224 #define IMX_TIM1_BASE           (0x03000 + IMX_IO_BASE)
 225 #define IMX_TIM2_BASE           (0x04000 + IMX_IO_BASE)
 226 #define IMX_TIM3_BASE           (0x05000 + IMX_IO_BASE)
 227 #define UART1_BASE              (0x0a000 + IMX_IO_BASE)
 228 #define UART2_BASE              (0x0b000 + IMX_IO_BASE)
 229 #define UART3_BASE              (0x0c000 + IMX_IO_BASE)
 230 #define UART4_BASE              (0x0d000 + IMX_IO_BASE)
 231 #define IMX_I2C1_BASE           (0x12000 + IMX_IO_BASE)
 232 #define IMX_GPIO_BASE           (0x15000 + IMX_IO_BASE)
 233 #define IMX_TIM4_BASE           (0x19000 + IMX_IO_BASE)
 234 #define IMX_TIM5_BASE           (0x1a000 + IMX_IO_BASE)
 235 #define IMX_UART5_BASE          (0x1b000 + IMX_IO_BASE)
 236 #define IMX_UART6_BASE          (0x1c000 + IMX_IO_BASE)
 237 #define IMX_I2C2_BASE           (0x1D000 + IMX_IO_BASE)
 238 #define IMX_TIM6_BASE           (0x1f000 + IMX_IO_BASE)
 239 #define IMX_AIPI2_BASE          (0x20000 + IMX_IO_BASE)
 240 #define IMX_PLL_BASE            (0x27000 + IMX_IO_BASE)
 241 #define IMX_SYSTEM_CTL_BASE     (0x27800 + IMX_IO_BASE)
 242 #define IMX_IIM_BASE            (0x28000 + IMX_IO_BASE)
 243 #define IMX_FEC_BASE            (0x2b000 + IMX_IO_BASE)
 244
 245 #define IMX_ESD_BASE            (0xD8001000)
 246 #define IMX_WEIM_BASE           (0xD8002000)
 247
 248 /* FMCR System Control bit definition*/
 249 #define UART4_RXD_CTL   (1 << 25)
 250 #define UART4_RTS_CTL   (1 << 24)
 251 #define KP_COL6_CTL     (1 << 18)
 252 #define KP_ROW7_CTL     (1 << 17)
 253 #define KP_ROW6_CTL     (1 << 16)
 254 #define PC_WAIT_B_CTL   (1 << 14)
 255 #define PC_READY_CTL    (1 << 13)
 256 #define PC_VS1_CTL      (1 << 12)
 257 #define PC_VS2_CTL      (1 << 11)
 258 #define PC_BVD1_CTL     (1 << 10)
 259 #define PC_BVD2_CTL     (1 << 9)
 260 #define IOS16_CTL       (1 << 8)
 261 #define NF_FMS          (1 << 5)
 262 #define NF_16BIT_SEL    (1 << 4)
 263 #define SLCDC_SEL       (1 << 2)
 264 #define SDCS1_SEL       (1 << 1)
 265 #define SDCS0_SEL       (1 << 0)
 266
 267
 268 /* important definition of some bits of WCR */
 269 #define WCR_WDE 0x04
 270
 271 #define CSCR_MPEN               (1 << 0)
 272 #define CSCR_SPEN               (1 << 1)
 273 #define CSCR_FPM_EN             (1 << 2)
 274 #define CSCR_OSC26M_DIS         (1 << 3)
 275 #define CSCR_OSC26M_DIV1P5      (1 << 4)
 276 #define CSCR_AHB_DIV
 277 #define CSCR_ARM_DIV
 278 #define CSCR_ARM_SRC_MPLL       (1 << 15)
 279 #define CSCR_MCU_SEL            (1 << 16)
 280 #define CSCR_SP_SEL             (1 << 17)
 281 #define CSCR_MPLL_RESTART       (1 << 18)
 282 #define CSCR_SPLL_RESTART       (1 << 19)
 283 #define CSCR_MSHC_SEL           (1 << 20)
 284 #define CSCR_H264_SEL           (1 << 21)
 285 #define CSCR_SSI1_SEL           (1 << 22)
 286 #define CSCR_SSI2_SEL           (1 << 23)
 287 #define CSCR_SD_CNT
 288 #define CSCR_USB_DIV
 289 #define CSCR_UPDATE_DIS         (1 << 31)
 290
 291 #define MPCTL1_BRMO             (1 << 6)
 292 #define MPCTL1_LF               (1 << 15)
 293
 294 #define PCCR0_SSI2_EN   (1 << 0)
 295 #define PCCR0_SSI1_EN   (1 << 1)
 296 #define PCCR0_SLCDC_EN  (1 << 2)
 297 #define PCCR0_SDHC3_EN  (1 << 3)
 298 #define PCCR0_SDHC2_EN  (1 << 4)
 299 #define PCCR0_SDHC1_EN  (1 << 5)
 300 #define PCCR0_SDC_EN    (1 << 6)
 301 #define PCCR0_SAHARA_EN (1 << 7)
 302 #define PCCR0_RTIC_EN   (1 << 8)
 303 #define PCCR0_RTC_EN    (1 << 9)
 304 #define PCCR0_PWM_EN    (1 << 11)
 305 #define PCCR0_OWIRE_EN  (1 << 12)
 306 #define PCCR0_MSHC_EN   (1 << 13)
 307 #define PCCR0_LCDC_EN   (1 << 14)
 308 #define PCCR0_KPP_EN    (1 << 15)
 309 #define PCCR0_IIM_EN    (1 << 16)
 310 #define PCCR0_I2C2_EN   (1 << 17)
 311 #define PCCR0_I2C1_EN   (1 << 18)
 312 #define PCCR0_GPT6_EN   (1 << 19)
 313 #define PCCR0_GPT5_EN   (1 << 20)
 314 #define PCCR0_GPT4_EN   (1 << 21)
 315 #define PCCR0_GPT3_EN   (1 << 22)
 316 #define PCCR0_GPT2_EN   (1 << 23)
 317 #define PCCR0_GPT1_EN   (1 << 24)
 318 #define PCCR0_GPIO_EN   (1 << 25)
 319 #define PCCR0_FEC_EN    (1 << 26)
 320 #define PCCR0_EMMA_EN   (1 << 27)
 321 #define PCCR0_DMA_EN    (1 << 28)
 322 #define PCCR0_CSPI3_EN  (1 << 29)
 323 #define PCCR0_CSPI2_EN  (1 << 30)
 324 #define PCCR0_CSPI1_EN  (1 << 31)
 325
 326 #define PCCR1_MSHC_BAUDEN       (1 << 2)
 327 #define PCCR1_NFC_BAUDEN        (1 << 3)
 328 #define PCCR1_SSI2_BAUDEN       (1 << 4)
 329 #define PCCR1_SSI1_BAUDEN       (1 << 5)
 330 #define PCCR1_H264_BAUDEN       (1 << 6)
 331 #define PCCR1_PERCLK4_EN        (1 << 7)
 332 #define PCCR1_PERCLK3_EN        (1 << 8)
 333 #define PCCR1_PERCLK2_EN        (1 << 9)
 334 #define PCCR1_PERCLK1_EN        (1 << 10)
 335 #define PCCR1_HCLK_USB          (1 << 11)
 336 #define PCCR1_HCLK_SLCDC        (1 << 12)
 337 #define PCCR1_HCLK_SAHARA       (1 << 13)
 338 #define PCCR1_HCLK_RTIC         (1 << 14)
 339 #define PCCR1_HCLK_LCDC         (1 << 15)
 340 #define PCCR1_HCLK_H264         (1 << 16)
 341 #define PCCR1_HCLK_FEC          (1 << 17)
 342 #define PCCR1_HCLK_EMMA         (1 << 18)
 343 #define PCCR1_HCLK_EMI          (1 << 19)
 344 #define PCCR1_HCLK_DMA          (1 << 20)
 345 #define PCCR1_HCLK_CSI          (1 << 21)
 346 #define PCCR1_HCLK_BROM         (1 << 22)
 347 #define PCCR1_HCLK_ATA          (1 << 23)
 348 #define PCCR1_WDT_EN            (1 << 24)
 349 #define PCCR1_USB_EN            (1 << 25)
 350 #define PCCR1_UART6_EN          (1 << 26)
 351 #define PCCR1_UART5_EN          (1 << 27)
 352 #define PCCR1_UART4_EN          (1 << 28)
 353 #define PCCR1_UART3_EN          (1 << 29)
 354 #define PCCR1_UART2_EN          (1 << 30)
 355 #define PCCR1_UART1_EN          (1 << 31)
 356
 357 /* SDRAM Controller registers bitfields */
 358 #define ESDCTL_PRCT(x)          (((x) & 0x3f) << 0)
 359 #define ESDCTL_BL               (1 << 7)
 360 #define ESDCTL_FP               (1 << 8)
 361 #define ESDCTL_PWDT(x)          (((x) & 3) << 10)
 362 #define ESDCTL_SREFR(x)         (((x) & 7) << 13)
 363 #define ESDCTL_DSIZ_16_UPPER    (0 << 16)
 364 #define ESDCTL_DSIZ_16_LOWER    (1 << 16)
 365 #define ESDCTL_DSIZ_32          (2 << 16)
 366 #define ESDCTL_COL8             (0 << 20)
 367 #define ESDCTL_COL9             (1 << 20)
 368 #define ESDCTL_COL10            (2 << 20)
 369 #define ESDCTL_ROW11            (0 << 24)
 370 #define ESDCTL_ROW12            (1 << 24)
 371 #define ESDCTL_ROW13            (2 << 24)
 372 #define ESDCTL_ROW14            (3 << 24)
 373 #define ESDCTL_ROW15            (4 << 24)
 374 #define ESDCTL_SP               (1 << 27)
 375 #define ESDCTL_SMODE_NORMAL     (0 << 28)
 376 #define ESDCTL_SMODE_PRECHARGE  (1 << 28)
 377 #define ESDCTL_SMODE_AUTO_REF   (2 << 28)
 378 #define ESDCTL_SMODE_LOAD_MODE  (3 << 28)
 379 #define ESDCTL_SMODE_MAN_REF    (4 << 28)
 380 #define ESDCTL_SDE              (1 << 31)
 381
 382 #define ESDCFG_TRC(x)           (((x) & 0xf) << 0)
 383 #define ESDCFG_TRCD(x)          (((x) & 0x7) << 4)
 384 #define ESDCFG_TCAS(x)          (((x) & 0x3) << 8)
 385 #define ESDCFG_TRRD(x)          (((x) & 0x3) << 10)
 386 #define ESDCFG_TRAS(x)          (((x) & 0x7) << 12)
 387 #define ESDCFG_TWR              (1 << 15)
 388 #define ESDCFG_TMRD(x)          (((x) & 0x3) << 16)
 389 #define ESDCFG_TRP(x)           (((x) & 0x3) << 18)
 390 #define ESDCFG_TWTR             (1 << 20)
 391 #define ESDCFG_TXP(x)           (((x) & 0x3) << 21)
 392
 393 #define ESDMISC_RST             (1 << 1)
 394 #define ESDMISC_MDDREN          (1 << 2)
 395 #define ESDMISC_MDDR_DL_RST     (1 << 3)
 396 #define ESDMISC_MDDR_MDIS       (1 << 4)
 397 #define ESDMISC_LHD             (1 << 5)
 398 #define ESDMISC_MA10_SHARE      (1 << 6)
 399 #define ESDMISC_SDRAM_RDY       (1 << 31)
 400
 401 #define PC5_PF_I2C2_DATA        (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
 402 #define PC6_PF_I2C2_CLK         (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
 403 #define PC7_PF_USBOTG_DATA5     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
 404 #define PC8_PF_USBOTG_DATA6     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
 405 #define PC9_PF_USBOTG_DATA0     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
 406 #define PC10_PF_USBOTG_DATA2    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
 407 #define PC11_PF_USBOTG_DATA1    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
 408 #define PC12_PF_USBOTG_DATA4    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
 409 #define PC13_PF_USBOTG_DATA3    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
 410
 411 #define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
 412 #define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
 413 #define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
 414 #define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
 415 #define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
 416 #define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
 417 #define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
 418 #define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
 419 #define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
 420 #define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
 421 #define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
 422 #define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
 423 #define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
 424 #define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
 425 #define PD14_AOUT_FEC_CLR       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
 426 #define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
 427 #define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
 428 #define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
 429
 430 #define PE0_PF_USBOTG_NXT       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
 431 #define PE1_PF_USBOTG_STP       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
 432 #define PE2_PF_USBOTG_DIR       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
 433 #define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
 434 #define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
 435 #define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
 436 #define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
 437 #define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
 438 #define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
 439 #define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
 440 #define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
 441 #define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
 442 #define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
 443 #define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
 444 #define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
 445 #define PE18_PF_SD1_D0          (GPIO_PORTE | GPIO_PF | 18)
 446 #define PE19_PF_SD1_D1          (GPIO_PORTE | GPIO_PF | 19)
 447 #define PE20_PF_SD1_D2          (GPIO_PORTE | GPIO_PF | 20)
 448 #define PE21_PF_SD1_D3          (GPIO_PORTE | GPIO_PF | 21)
 449 #define PE22_PF_SD1_CMD         (GPIO_PORTE | GPIO_PF | 22)
 450 #define PE23_PF_SD1_CLK         (GPIO_PORTE | GPIO_PF | 23)
 451 #define PB4_PF_SD2_D0           (GPIO_PORTB | GPIO_PF | 4)
 452 #define PB5_PF_SD2_D1           (GPIO_PORTB | GPIO_PF | 5)
 453 #define PB6_PF_SD2_D2           (GPIO_PORTB | GPIO_PF | 6)
 454 #define PB7_PF_SD2_D3           (GPIO_PORTB | GPIO_PF | 7)
 455 #define PB8_PF_SD2_CMD          (GPIO_PORTB | GPIO_PF | 8)
 456 #define PB9_PF_SD2_CLK          (GPIO_PORTB | GPIO_PF | 9)
 457 #define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
 458 #define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
 459 #define PE24_PF_USBOTG_CLK      (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
 460 #define PE25_PF_USBOTG_DATA7    (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
 461
 462 /* Clocksource Bitfields */
 463 #define TCTL_SWR        (1 << 15)       /* Software reset */
 464 #define TCTL_FRR        (1 << 8)        /* Freerun / restart */
 465 #define TCTL_CAP        (3 << 6)        /* Capture Edge */
 466 #define TCTL_OM         (1 << 5)        /* output mode */
 467 #define TCTL_IRQEN      (1 << 4)        /* interrupt enable */
 468 #define TCTL_CLKSOURCE  1               /* Clock source bit position */
 469 #define TCTL_TEN        1               /* Timer enable */
 470 #define TPRER_PRES      0xff            /* Prescale */
 471 #define TSTAT_CAPT      (1 << 1)        /* Capture event */
 472 #define TSTAT_COMP      1               /* Compare event */
 473
 474 #define GPIO_PIN_MASK   0x1f
 475
 476 #define GPIO_PORT_SHIFT 5
 477 #define GPIO_PORT_MASK  (0x7 << GPIO_PORT_SHIFT)
 478
 479 #define GPIO_PORTA      (PORTA << GPIO_PORT_SHIFT)
 480 #define GPIO_PORTB      (PORTB << GPIO_PORT_SHIFT)
 481 #define GPIO_PORTC      (PORTC << GPIO_PORT_SHIFT)
 482 #define GPIO_PORTD      (PORTD << GPIO_PORT_SHIFT)
 483 #define GPIO_PORTE      (PORTE << GPIO_PORT_SHIFT)
 484 #define GPIO_PORTF      (PORTF << GPIO_PORT_SHIFT)
 485
 486 #define GPIO_OUT        (1 << 8)
 487 #define GPIO_IN         (0 << 8)
 488 #define GPIO_PUEN       (1 << 9)
 489
 490 #define GPIO_PF         (1 << 10)
 491 #define GPIO_AF         (1 << 11)
 492
 493 #define GPIO_OCR_SHIFT  12
 494 #define GPIO_OCR_MASK   (3 << GPIO_OCR_SHIFT)
 495 #define GPIO_AIN        (0 << GPIO_OCR_SHIFT)
 496 #define GPIO_BIN        (1 << GPIO_OCR_SHIFT)
 497 #define GPIO_CIN        (2 << GPIO_OCR_SHIFT)
 498 #define GPIO_GPIO       (3 << GPIO_OCR_SHIFT)
 499
 500 #define GPIO_AOUT_SHIFT 14
 501 #define GPIO_AOUT_MASK  (3 << GPIO_AOUT_SHIFT)
 502 #define GPIO_AOUT       (0 << GPIO_AOUT_SHIFT)
 503 #define GPIO_AOUT_ISR   (1 << GPIO_AOUT_SHIFT)
 504 #define GPIO_AOUT_0     (2 << GPIO_AOUT_SHIFT)
 505 #define GPIO_AOUT_1     (3 << GPIO_AOUT_SHIFT)
 506
 507 #define GPIO_BOUT_SHIFT 16
 508 #define GPIO_BOUT_MASK  (3 << GPIO_BOUT_SHIFT)
 509 #define GPIO_BOUT       (0 << GPIO_BOUT_SHIFT)
 510 #define GPIO_BOUT_ISR   (1 << GPIO_BOUT_SHIFT)
 511 #define GPIO_BOUT_0     (2 << GPIO_BOUT_SHIFT)
 512 #define GPIO_BOUT_1     (3 << GPIO_BOUT_SHIFT)
 513
 514 #define IIM_STAT_BUSY   (1 << 7)
 515 #define IIM_STAT_PRGD   (1 << 1)
 516 #define IIM_STAT_SNSD   (1 << 0)
 517 #define IIM_ERR_PRGE    (1 << 7)
 518 #define IIM_ERR_WPE     (1 << 6)
 519 #define IIM_ERR_OPE     (1 << 5)
 520 #define IIM_ERR_RPE     (1 << 4)
 521 #define IIM_ERR_WLRE    (1 << 3)
 522 #define IIM_ERR_SNSE    (1 << 2)
 523 #define IIM_ERR_PARITYE (1 << 1)
 524
 525 #endif                          /* _IMX_REGS_H */