arch/arm/include/asm/arch-mx35/imx-regs.h

   1 /*
   2  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   3  *
   4  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __ASM_ARCH_MX35_H
  26 #define __ASM_ARCH_MX35_H
  27
  28 /*
  29  * IRAM
  30  */
  31 #define IRAM_BASE_ADDR          0x10000000      /* internal ram */
  32 #define IRAM_SIZE               0x00020000      /* 128 KB */
  33
  34 /*
  35  * AIPS 1
  36  */
  37 #define AIPS1_BASE_ADDR         0x43F00000
  38 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
  39 #define MAX_BASE_ADDR           0x43F04000
  40 #define EVTMON_BASE_ADDR        0x43F08000
  41 #define CLKCTL_BASE_ADDR        0x43F0C000
  42 #define I2C1_BASE_ADDR          0x43F80000
  43 #define I2C3_BASE_ADDR          0x43F84000
  44 #define ATA_BASE_ADDR           0x43F8C000
  45 #define UART1_BASE              0x43F90000
  46 #define UART2_BASE              0x43F94000
  47 #define I2C2_BASE_ADDR          0x43F98000
  48 #define CSPI1_BASE_ADDR         0x43FA4000
  49 #define IOMUXC_BASE_ADDR        0x43FAC000
  50
  51 /*
  52  * SPBA
  53  */
  54 #define SPBA_BASE_ADDR          0x50000000
  55 #define UART3_BASE              0x5000C000
  56 #define CSPI2_BASE_ADDR         0x50010000
  57 #define ATA_DMA_BASE_ADDR       0x50020000
  58 #define FEC_BASE_ADDR           0x50038000
  59 #define SPBA_CTRL_BASE_ADDR     0x5003C000
  60
  61 /*
  62  * AIPS 2
  63  */
  64 #define AIPS2_BASE_ADDR         0x53F00000
  65 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
  66 #define CCM_BASE_ADDR           0x53F80000
  67 #define GPT1_BASE_ADDR          0x53F90000
  68 #define EPIT1_BASE_ADDR         0x53F94000
  69 #define EPIT2_BASE_ADDR         0x53F98000
  70 #define GPIO3_BASE_ADDR         0x53FA4000
  71 #define MMC_SDHC1_BASE_ADDR     0x53FB4000
  72 #define MMC_SDHC2_BASE_ADDR     0x53FB8000
  73 #define MMC_SDHC3_BASE_ADDR     0x53FBC000
  74 #define IPU_CTRL_BASE_ADDR      0x53FC0000
  75 #define GPIO3_BASE_ADDR         0x53FA4000
  76 #define GPIO1_BASE_ADDR         0x53FCC000
  77 #define GPIO2_BASE_ADDR         0x53FD0000
  78 #define SDMA_BASE_ADDR          0x53FD4000
  79 #define RTC_BASE_ADDR           0x53FD8000
  80 #define WDOG_BASE_ADDR          0x53FDC000
  81 #define PWM_BASE_ADDR           0x53FE0000
  82 #define RTIC_BASE_ADDR          0x53FEC000
  83 #define IIM_BASE_ADDR           0x53FF0000
  84
  85 #define IMX_CCM_BASE            CCM_BASE_ADDR
  86
  87 /*
  88  * ROMPATCH and AVIC
  89  */
  90 #define ROMPATCH_BASE_ADDR      0x60000000
  91 #define AVIC_BASE_ADDR          0x68000000
  92
  93 /*
  94  * NAND, SDRAM, WEIM, M3IF, EMI controllers
  95  */
  96 #define EXT_MEM_CTRL_BASE       0xB8000000
  97 #define ESDCTL_BASE_ADDR        0xB8001000
  98 #define WEIM_BASE_ADDR          0xB8002000
  99 #define WEIM_CTRL_CS0           WEIM_BASE_ADDR
 100 #define WEIM_CTRL_CS1           (WEIM_BASE_ADDR + 0x10)
 101 #define WEIM_CTRL_CS2           (WEIM_BASE_ADDR + 0x20)
 102 #define WEIM_CTRL_CS3           (WEIM_BASE_ADDR + 0x30)
 103 #define WEIM_CTRL_CS4           (WEIM_BASE_ADDR + 0x40)
 104 #define WEIM_CTRL_CS5           (WEIM_BASE_ADDR + 0x50)
 105 #define M3IF_BASE_ADDR          0xB8003000
 106 #define EMI_BASE_ADDR           0xB8004000
 107
 108 #define NFC_BASE_ADDR           0xBB000000
 109
 110 /*
 111  * Memory regions and CS
 112  */
 113 #define IPU_MEM_BASE_ADDR       0x70000000
 114 #define CSD0_BASE_ADDR          0x80000000
 115 #define CSD1_BASE_ADDR          0x90000000
 116 #define CS0_BASE_ADDR           0xA0000000
 117 #define CS1_BASE_ADDR           0xA8000000
 118 #define CS2_BASE_ADDR           0xB0000000
 119 #define CS3_BASE_ADDR           0xB2000000
 120 #define CS4_BASE_ADDR           0xB4000000
 121 #define CS5_BASE_ADDR           0xB6000000
 122
 123 /*
 124  * IRQ Controller Register Definitions.
 125  */
 126 #define AVIC_NIMASK             0x04
 127 #define AVIC_INTTYPEH           0x18
 128 #define AVIC_INTTYPEL           0x1C
 129
 130 /* L210 */
 131 #define L2CC_BASE_ADDR          0x30000000
 132 #define L2_CACHE_LINE_SIZE              32
 133 #define L2_CACHE_CTL_REG                0x100
 134 #define L2_CACHE_AUX_CTL_REG            0x104
 135 #define L2_CACHE_SYNC_REG               0x730
 136 #define L2_CACHE_INV_LINE_REG           0x770
 137 #define L2_CACHE_INV_WAY_REG            0x77C
 138 #define L2_CACHE_CLEAN_LINE_REG         0x7B0
 139 #define L2_CACHE_CLEAN_INV_LINE_REG     0x7F0
 140 #define L2_CACHE_DBG_CTL_REG            0xF40
 141
 142 #define CLKMODE_AUTO            0
 143 #define CLKMODE_CONSUMER        1
 144
 145 #define PLL_PD(x)               (((x) & 0xf) << 26)
 146 #define PLL_MFD(x)              (((x) & 0x3ff) << 16)
 147 #define PLL_MFI(x)              (((x) & 0xf) << 10)
 148 #define PLL_MFN(x)              (((x) & 0x3ff) << 0)
 149
 150 #define _PLL_BRM(x)     ((x) << 31)
 151 #define _PLL_PD(x)      (((x) - 1) << 26)
 152 #define _PLL_MFD(x)     (((x) - 1) << 16)
 153 #define _PLL_MFI(x)     ((x) << 10)
 154 #define _PLL_MFN(x)     (x)
 155 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
 156         (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
 157          _PLL_MFN(mfn))
 158
 159 #define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
 160 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
 161 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
 162
 163 #define CSCR_U(x)       (WEIM_CTRL_CS#x + 0)
 164 #define CSCR_L(x)       (WEIM_CTRL_CS#x + 4)
 165 #define CSCR_A(x)       (WEIM_CTRL_CS#x + 8)
 166
 167 #define IIM_SREV        0x24
 168 #define ROMPATCH_REV    0x40
 169
 170 #define IPU_CONF        IPU_CTRL_BASE_ADDR
 171
 172 #define IPU_CONF_PXL_ENDIAN     (1<<8)
 173 #define IPU_CONF_DU_EN          (1<<7)
 174 #define IPU_CONF_DI_EN          (1<<6)
 175 #define IPU_CONF_ADC_EN         (1<<5)
 176 #define IPU_CONF_SDC_EN         (1<<4)
 177 #define IPU_CONF_PF_EN          (1<<3)
 178 #define IPU_CONF_ROT_EN         (1<<2)
 179 #define IPU_CONF_IC_EN          (1<<1)
 180 #define IPU_CONF_SCI_EN         (1<<0)
 181
 182 /*
 183  * CSPI register definitions
 184  */
 185 #define MXC_CSPI
 186 #define MXC_CSPICTRL_EN         (1 << 0)
 187 #define MXC_CSPICTRL_MODE       (1 << 1)
 188 #define MXC_CSPICTRL_XCH        (1 << 2)
 189 #define MXC_CSPICTRL_SMC        (1 << 3)
 190 #define MXC_CSPICTRL_POL        (1 << 4)
 191 #define MXC_CSPICTRL_PHA        (1 << 5)
 192 #define MXC_CSPICTRL_SSCTL      (1 << 6)
 193 #define MXC_CSPICTRL_SSPOL      (1 << 7)
 194 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
 195 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
 196 #define MXC_CSPICTRL_DATARATE(x)        (((x) & 0x7) << 16)
 197 #define MXC_CSPICTRL_TC         (1 << 7)
 198 #define MXC_CSPICTRL_RXOVF      (1 << 6)
 199 #define MXC_CSPICTRL_MAXBITS    0xfff
 200 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
 201 #define MAX_SPI_BYTES   4
 202
 203 #define MXC_SPI_BASE_ADDRESSES \
 204         0x43fa4000, \
 205         0x50010000,
 206
 207 #define GPIO_PORT_NUM           3
 208 #define GPIO_NUM_PIN            32
 209
 210 #define CHIP_REV_1_0            0x10
 211 #define CHIP_REV_2_0            0x20
 212
 213 #define BOARD_REV_1_0           0x0
 214 #define BOARD_REV_2_0           0x1
 215
 216 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 217 #include <asm/types.h>
 218
 219 enum mxc_main_clocks {
 220         CPU_CLK,
 221         AHB_CLK,
 222         IPG_CLK,
 223         IPG_PER_CLK,
 224         NFC_CLK,
 225         USB_CLK,
 226         HSP_CLK,
 227 };
 228
 229 enum mxc_peri_clocks {
 230         UART1_BAUD,
 231         UART2_BAUD,
 232         UART3_BAUD,
 233         SSI1_BAUD,
 234         SSI2_BAUD,
 235         CSI_BAUD,
 236         MSHC_CLK,
 237         ESDHC1_CLK,
 238         ESDHC2_CLK,
 239         ESDHC3_CLK,
 240         SPDIF_CLK,
 241         SPI1_CLK,
 242         SPI2_CLK,
 243 };
 244
 245 /* Clock Control Module (CCM) registers */
 246 struct ccm_regs {
 247         u32 ccmr;       /* Control */
 248         u32 pdr0;       /* Post divider 0 */
 249         u32 pdr1;       /* Post divider 1 */
 250         u32 pdr2;       /* Post divider 2 */
 251         u32 pdr3;       /* Post divider 3 */
 252         u32 pdr4;       /* Post divider 4 */
 253         u32 rcsr;       /* CCM Status */
 254         u32 mpctl;      /* Core PLL Control */
 255         u32 ppctl;      /* Peripheral PLL Control */
 256         u32 acmr;       /* Audio clock mux */
 257         u32 cosr;       /* Clock out source */
 258         u32 cgr0;       /* Clock Gating Control 0 */
 259         u32 cgr1;       /* Clock Gating Control 1 */
 260         u32 cgr2;       /* Clock Gating Control 2 */
 261         u32 cgr3;       /* Clock Gating Control 3 */
 262         u32 reserved;
 263         u32 dcvr0;      /* DPTC Comparator 0 */
 264         u32 dcvr1;      /* DPTC Comparator 0 */
 265         u32 dcvr2;      /* DPTC Comparator 0 */
 266         u32 dcvr3;      /* DPTC Comparator 0 */
 267         u32 ltr0;       /* Load Tracking 0 */
 268         u32 ltr1;       /* Load Tracking 1 */
 269         u32 ltr2;       /* Load Tracking 2 */
 270         u32 ltr3;       /* Load Tracking 3 */
 271         u32 ltbr0;      /* Load Tracking Buffer 0 */
 272 };
 273
 274 /* IIM control registers */
 275 struct iim_regs {
 276         u32 iim_stat;
 277         u32 iim_statm;
 278         u32 iim_err;
 279         u32 iim_emask;
 280         u32 iim_fctl;
 281         u32 iim_ua;
 282         u32 iim_la;
 283         u32 iim_sdat;
 284         u32 iim_prev;
 285         u32 iim_srev;
 286         u32 iim_prog_p;
 287         u32 iim_scs0;
 288         u32 iim_scs1;
 289         u32 iim_scs2;
 290         u32 iim_scs3;
 291 };
 292
 293 /* General Purpose Timer (GPT) registers */
 294 struct gpt_regs {
 295         u32 ctrl;       /* control */
 296         u32 pre;        /* prescaler */
 297         u32 stat;       /* status */
 298         u32 intr;       /* interrupt */
 299         u32 cmp[3];     /* output compare 1-3 */
 300         u32 capt[2];    /* input capture 1-2 */
 301         u32 counter;    /* counter */
 302 };
 303
 304 /* CSPI registers */
 305 struct cspi_regs {
 306         u32 rxdata;
 307         u32 txdata;
 308         u32 ctrl;
 309         u32 intr;
 310         u32 dma;
 311         u32 stat;
 312         u32 period;
 313         u32 test;
 314 };
 315
 316 /* Watchdog Timer (WDOG) registers */
 317 struct wdog_regs {
 318         u16 wcr;        /* Control */
 319         u16 wsr;        /* Service */
 320         u16 wrsr;       /* Reset Status */
 321         u16 wicr;       /* Interrupt Control */
 322         u16 wmcr;       /* Misc Control */
 323 };
 324
 325 struct esdc_regs {
 326         u32     esdctl0;
 327         u32     esdcfg0;
 328         u32     esdctl1;
 329         u32     esdcfg1;
 330         u32     esdmisc;
 331         u32     reserved[4];
 332         u32     esdcdly[5];
 333         u32     esdcdlyl;
 334 };
 335
 336 #define ESDC_MISC_RST           (1 << 1)
 337 #define ESDC_MISC_MDDR_EN       (1 << 2)
 338 #define ESDC_MISC_MDDR_DL_RST   (1 << 3)
 339 #define ESDC_MISC_DDR_EN        (1 << 8)
 340 #define ESDC_MISC_DDR2_EN       (1 << 9)
 341
 342 /*
 343  * NFMS bit in RCSR register for pagesize of nandflash
 344  */
 345 #define NFMS_BIT                8
 346 #define NFMS_NF_DWIDTH          14
 347 #define NFMS_NF_PG_SZ           8
 348
 349 #define CCM_RCSR_NF_16BIT_SEL   (1 << 14)
 350
 351 #endif
 352 #endif /* __ASM_ARCH_MX35_H */