arch/arm/include/asm/arch-mx5/imx-regs.h

   1 /*
   2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
  24 #define __ASM_ARCH_MX5_IMX_REGS_H__
  25
  26 #if defined(CONFIG_MX51)
  27 #define IRAM_BASE_ADDR          0x1FFE0000      /* internal ram */
  28 #define IPU_CTRL_BASE_ADDR      0x40000000
  29 #define SPBA0_BASE_ADDR         0x70000000
  30 #define AIPS1_BASE_ADDR         0x73F00000
  31 #define AIPS2_BASE_ADDR         0x83F00000
  32 #define CSD0_BASE_ADDR          0x90000000
  33 #define CSD1_BASE_ADDR          0xA0000000
  34 #define NFC_BASE_ADDR_AXI       0xCFFF0000
  35 #define CS1_BASE_ADDR           0xB8000000
  36 #elif defined(CONFIG_MX53)
  37 #define IPU_CTRL_BASE_ADDR      0x18000000
  38 #define SPBA0_BASE_ADDR         0x50000000
  39 #define AIPS1_BASE_ADDR         0x53F00000
  40 #define AIPS2_BASE_ADDR         0x63F00000
  41 #define CSD0_BASE_ADDR          0x70000000
  42 #define CSD1_BASE_ADDR          0xB0000000
  43 #define NFC_BASE_ADDR_AXI       0xF7FF0000
  44 #define IRAM_BASE_ADDR          0xF8000000
  45 #define CS1_BASE_ADDR           0xF4000000
  46 #else
  47 #error "CPU_TYPE not defined"
  48 #endif
  49
  50 #define IRAM_SIZE               0x00020000      /* 128 KB */
  51
  52 /*
  53  * SPBA global module enabled #0
  54  */
  55 #define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
  56 #define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
  57 #define UART3_BASE              (SPBA0_BASE_ADDR + 0x0000C000)
  58 #define CSPI1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
  59 #define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
  60 #define MMC_SDHC3_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00020000)
  61 #define MMC_SDHC4_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00024000)
  62 #define SPDIF_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00028000)
  63 #define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00030000)
  64 #define SLIM_DMA_BASE_ADDR      (SPBA0_BASE_ADDR + 0x00034000)
  65 #define HSI2C_DMA_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00038000)
  66 #define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
  67
  68 /*
  69  * AIPS 1
  70  */
  71 #define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
  72 #define GPIO1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00084000)
  73 #define GPIO2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00088000)
  74 #define GPIO3_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0008C000)
  75 #define GPIO4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
  76 #define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00094000)
  77 #define WDOG1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00098000)
  78 #define WDOG2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
  79 #define GPT1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
  80 #define SRTC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A4000)
  81 #define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000A8000)
  82 #define EPIT1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000AC000)
  83 #define EPIT2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
  84 #define PWM1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000B4000)
  85 #define PWM2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000B8000)
  86 #define UART1_BASE              (AIPS1_BASE_ADDR + 0x000BC000)
  87 #define UART2_BASE              (AIPS1_BASE_ADDR + 0x000C0000)
  88 #define SRC_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000D0000)
  89 #define CCM_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000D4000)
  90 #define GPC_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000D8000)
  91
  92 #if defined(CONFIG_MX53)
  93 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
  94 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
  95 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
  96 #endif
  97 /*
  98  * AIPS 2
  99  */
 100 #define PLL1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00080000)
 101 #define PLL2_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00084000)
 102 #define PLL3_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00088000)
 103 #ifdef  CONFIG_MX53
 104 #define PLL4_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008c000)
 105 #endif
 106 #define AHBMAX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x00094000)
 107 #define IIM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00098000)
 108 #define CSU_BASE_ADDR           (AIPS2_BASE_ADDR + 0x0009C000)
 109 #define ARM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000A0000)
 110 #define OWIRE_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
 111 #define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000A8000)
 112 #define CSPI2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000AC000)
 113 #define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
 114 #define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000B4000)
 115 #define ROMCP_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000B8000)
 116 #define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000BC000)
 117 #define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000C0000)
 118 #define I2C2_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000C4000)
 119 #define I2C1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000C8000)
 120 #define SSI1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000CC000)
 121 #define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000D0000)
 122 #define M4IF_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D8000)
 123 #define ESDCTL_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000D9000)
 124 #define WEIM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DA000)
 125 #define NFC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000DB000)
 126 #define EMI_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000DBF00)
 127 #define MIPI_HSC_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000DC000)
 128 #define ATA_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
 129 #define SIM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E4000)
 130 #define SSI3BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E8000)
 131 #define FEC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000EC000)
 132 #define TVE_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000F0000)
 133 #define VPU_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000F4000)
 134 #define SAHARA_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000F8000)
 135
 136 /*
 137  * WEIM CSnGCR1
 138  */
 139 #define CSEN            1
 140 #define SWR             (1 << 1)
 141 #define SRD             (1 << 2)
 142 #define MUM             (1 << 3)
 143 #define WFL             (1 << 4)
 144 #define RFL             (1 << 5)
 145 #define CRE             (1 << 6)
 146 #define CREP            (1 << 7)
 147 #define BL(x)           (((x) & 0x7) << 8)
 148 #define WC              (1 << 11)
 149 #define BCD(x)          (((x) & 0x3) << 12)
 150 #define BCS(x)          (((x) & 0x3) << 14)
 151 #define DSZ(x)          (((x) & 0x7) << 16)
 152 #define SP              (1 << 19)
 153 #define CSREC(x)        (((x) & 0x7) << 20)
 154 #define AUS             (1 << 23)
 155 #define GBC(x)          (((x) & 0x7) << 24)
 156 #define WP              (1 << 27)
 157 #define PSZ(x)          (((x) & 0x0f << 28)
 158
 159 /*
 160  * WEIM CSnGCR2
 161  */
 162 #define ADH(x)          (((x) & 0x3))
 163 #define DAPS(x)         (((x) & 0x0f << 4)
 164 #define DAE             (1 << 8)
 165 #define DAP             (1 << 9)
 166 #define MUX16_BYP       (1 << 12)
 167
 168 /*
 169  * WEIM CSnRCR1
 170  */
 171 #define RCSN(x)         (((x) & 0x7))
 172 #define RCSA(x)         (((x) & 0x7) << 4)
 173 #define OEN(x)          (((x) & 0x7) << 8)
 174 #define OEA(x)          (((x) & 0x7) << 12)
 175 #define RADVN(x)        (((x) & 0x7) << 16)
 176 #define RAL             (1 << 19)
 177 #define RADVA(x)        (((x) & 0x7) << 20)
 178 #define RWSC(x)         (((x) & 0x3f) << 24)
 179
 180 /*
 181  * WEIM CSnRCR2
 182  */
 183 #define RBEN(x)         (((x) & 0x7))
 184 #define RBE             (1 << 3)
 185 #define RBEA(x)         (((x) & 0x7) << 4)
 186 #define RL(x)           (((x) & 0x3) << 8)
 187 #define PAT(x)          (((x) & 0x7) << 12)
 188 #define APR             (1 << 15)
 189
 190 /*
 191  * WEIM CSnWCR1
 192  */
 193 #define WCSN(x)         (((x) & 0x7))
 194 #define WCSA(x)         (((x) & 0x7) << 3)
 195 #define WEN(x)          (((x) & 0x7) << 6)
 196 #define WEA(x)          (((x) & 0x7) << 9)
 197 #define WBEN(x)         (((x) & 0x7) << 12)
 198 #define WBEA(x)         (((x) & 0x7) << 15)
 199 #define WADVN(x)        (((x) & 0x7) << 18)
 200 #define WADVA(x)        (((x) & 0x7) << 21)
 201 #define WWSC(x)         (((x) & 0x3f) << 24)
 202 #define WBED1           (1 << 30)
 203 #define WAL             (1 << 31)
 204
 205 /*
 206  * WEIM CSnWCR2
 207  */
 208 #define WBED            1
 209
 210 /*
 211  * WEIM WCR
 212  */
 213 #define BCM             1
 214 #define GBCD(x)         (((x) & 0x3) << 1)
 215 #define INTEN           (1 << 4)
 216 #define INTPOL          (1 << 5)
 217 #define WDOG_EN         (1 << 8)
 218 #define WDOG_LIMIT(x)   (((x) & 0x3) << 9)
 219
 220 #define CS0_128                                 0
 221 #define CS0_64M_CS1_64M                         1
 222 #define CS0_64M_CS1_32M_CS2_32M                 2
 223 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M         3
 224
 225 /*
 226  * Number of GPIO pins per port
 227  */
 228 #define GPIO_NUM_PIN            32
 229
 230 #define IIM_SREV        0x24
 231 #define ROM_SI_REV      0x48
 232
 233 #define NFC_BUF_SIZE    0x1000
 234
 235 /* M4IF */
 236 #define M4IF_FBPM0      0x40
 237 #define M4IF_FIDBP      0x48
 238
 239 /* Assuming 24MHz input clock with doubler ON */
 240 /*                            MFI         PDF */
 241 #define DP_OP_864       ((8 << 4) + ((1 - 1)  << 0))
 242 #define DP_MFD_864      (180 - 1) /* PL Dither mode */
 243 #define DP_MFN_864      180
 244 #define DP_MFN_800_DIT  60 /* PL Dither mode */
 245
 246 #define DP_OP_850       ((8 << 4) + ((1 - 1)  << 0))
 247 #define DP_MFD_850      (48 - 1)
 248 #define DP_MFN_850      41
 249
 250 #define DP_OP_800       ((8 << 4) + ((1 - 1)  << 0))
 251 #define DP_MFD_800      (3 - 1)
 252 #define DP_MFN_800      1
 253
 254 #define DP_OP_700       ((7 << 4) + ((1 - 1)  << 0))
 255 #define DP_MFD_700      (24 - 1)
 256 #define DP_MFN_700      7
 257
 258 #define DP_OP_665       ((6 << 4) + ((1 - 1)  << 0))
 259 #define DP_MFD_665      (96 - 1)
 260 #define DP_MFN_665      89
 261
 262 #define DP_OP_532       ((5 << 4) + ((1 - 1)  << 0))
 263 #define DP_MFD_532      (24 - 1)
 264 #define DP_MFN_532      13
 265
 266 #define DP_OP_400       ((8 << 4) + ((2 - 1)  << 0))
 267 #define DP_MFD_400      (3 - 1)
 268 #define DP_MFN_400      1
 269
 270 #define DP_OP_216       ((6 << 4) + ((3 - 1)  << 0))
 271 #define DP_MFD_216      (4 - 1)
 272 #define DP_MFN_216      3
 273
 274 #define CHIP_REV_1_0            0x10
 275 #define CHIP_REV_1_1            0x11
 276 #define CHIP_REV_2_0            0x20
 277 #define CHIP_REV_2_5            0x25
 278 #define CHIP_REV_3_0            0x30
 279
 280 #define BOARD_REV_1_0           0x0
 281 #define BOARD_REV_2_0           0x1
 282
 283 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
 284
 285 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 286 #include <asm/types.h>
 287
 288 #define __REG(x)        (*((volatile u32 *)(x)))
 289 #define __REG16(x)      (*((volatile u16 *)(x)))
 290 #define __REG8(x)       (*((volatile u8 *)(x)))
 291
 292 struct clkctl {
 293         u32     ccr;
 294         u32     ccdr;
 295         u32     csr;
 296         u32     ccsr;
 297         u32     cacrr;
 298         u32     cbcdr;
 299         u32     cbcmr;
 300         u32     cscmr1;
 301         u32     cscmr2;
 302         u32     cscdr1;
 303         u32     cs1cdr;
 304         u32     cs2cdr;
 305         u32     cdcdr;
 306         u32     chsccdr;
 307         u32     cscdr2;
 308         u32     cscdr3;
 309         u32     cscdr4;
 310         u32     cwdr;
 311         u32     cdhipr;
 312         u32     cdcr;
 313         u32     ctor;
 314         u32     clpcr;
 315         u32     cisr;
 316         u32     cimr;
 317         u32     ccosr;
 318         u32     cgpr;
 319         u32     ccgr0;
 320         u32     ccgr1;
 321         u32     ccgr2;
 322         u32     ccgr3;
 323         u32     ccgr4;
 324         u32     ccgr5;
 325         u32     ccgr6;
 326 #if defined(CONFIG_MX53)
 327         u32     ccgr7;
 328 #endif
 329         u32     cmeor;
 330 };
 331
 332 /* DPLL registers */
 333 struct dpll {
 334         u32     dp_ctl;
 335         u32     dp_config;
 336         u32     dp_op;
 337         u32     dp_mfd;
 338         u32     dp_mfn;
 339         u32     dp_mfn_minus;
 340         u32     dp_mfn_plus;
 341         u32     dp_hfs_op;
 342         u32     dp_hfs_mfd;
 343         u32     dp_hfs_mfn;
 344         u32     dp_mfn_togc;
 345         u32     dp_destat;
 346 };
 347 /* WEIM registers */
 348 struct weim {
 349         u32     cs0gcr1;
 350         u32     cs0gcr2;
 351         u32     cs0rcr1;
 352         u32     cs0rcr2;
 353         u32     cs0wcr1;
 354         u32     cs0wcr2;
 355         u32     cs1gcr1;
 356         u32     cs1gcr2;
 357         u32     cs1rcr1;
 358         u32     cs1rcr2;
 359         u32     cs1wcr1;
 360         u32     cs1wcr2;
 361         u32     cs2gcr1;
 362         u32     cs2gcr2;
 363         u32     cs2rcr1;
 364         u32     cs2rcr2;
 365         u32     cs2wcr1;
 366         u32     cs2wcr2;
 367         u32     cs3gcr1;
 368         u32     cs3gcr2;
 369         u32     cs3rcr1;
 370         u32     cs3rcr2;
 371         u32     cs3wcr1;
 372         u32     cs3wcr2;
 373         u32     cs4gcr1;
 374         u32     cs4gcr2;
 375         u32     cs4rcr1;
 376         u32     cs4rcr2;
 377         u32     cs4wcr1;
 378         u32     cs4wcr2;
 379         u32     cs5gcr1;
 380         u32     cs5gcr2;
 381         u32     cs5rcr1;
 382         u32     cs5rcr2;
 383         u32     cs5wcr1;
 384         u32     cs5wcr2;
 385         u32     wcr;
 386         u32     wiar;
 387         u32     ear;
 388 };
 389
 390 #if defined(CONFIG_MX51)
 391 struct iomuxc {
 392         u32     gpr0;
 393         u32     gpr1;
 394         u32     omux0;
 395         u32     omux1;
 396         u32     omux2;
 397         u32     omux3;
 398         u32     omux4;
 399 };
 400 #elif defined(CONFIG_MX53)
 401 struct iomuxc {
 402         u32     gpr0;
 403         u32     gpr1;
 404         u32     gpr2;
 405         u32     omux0;
 406         u32     omux1;
 407         u32     omux2;
 408         u32     omux3;
 409         u32     omux4;
 410 };
 411 #endif
 412
 413 /* System Reset Controller (SRC) */
 414 struct src {
 415         u32     scr;
 416         u32     sbmr;
 417         u32     srsr;
 418         u32     reserved1[2];
 419         u32     sisr;
 420         u32     simr;
 421 };
 422
 423 /* CSPI registers */
 424 struct cspi_regs {
 425         u32 rxdata;
 426         u32 txdata;
 427         u32 ctrl;
 428         u32 cfg;
 429         u32 intr;
 430         u32 dma;
 431         u32 stat;
 432         u32 period;
 433 };
 434
 435 struct iim_regs {
 436         u32     stat;
 437         u32     statm;
 438         u32     err;
 439         u32     emask;
 440         u32     fctl;
 441         u32     ua;
 442         u32     la;
 443         u32     sdat;
 444         u32     prev;
 445         u32     srev;
 446         u32     preg_p;
 447         u32     scs0;
 448         u32     scs1;
 449         u32     scs2;
 450         u32     scs3;
 451         u32     res0[0x1f1];
 452         struct fuse_bank {
 453                 u32     fuse_regs[0x20];
 454                 u32     fuse_rsvd[0xe0];
 455         } bank[4];
 456 };
 457
 458 struct fuse_bank1_regs {
 459         u32     fuse0_8[9];
 460         u32     mac_addr[6];
 461         u32     fuse15_31[0x11];
 462 };
 463
 464 #endif /* __ASSEMBLER__*/
 465
 466 #endif                          /* __ASM_ARCH_MX5_IMX_REGS_H__ */