arch/arm/include/asm/arch-mx6/crm_regs.h

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
   8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
   9
  10 #define CCM_CCOSR               0x020c4060
  11 #define CCM_CCGR0               0x020C4068
  12 #define CCM_CCGR1               0x020C406c
  13 #define CCM_CCGR2               0x020C4070
  14 #define CCM_CCGR3               0x020C4074
  15 #define CCM_CCGR4               0x020C4078
  16 #define CCM_CCGR5               0x020C407c
  17 #define CCM_CCGR6               0x020C4080
  18
  19 #define PMU_MISC2               0x020C8170
  20
  21 #ifndef __ASSEMBLY__
  22 struct mxc_ccm_reg {
  23         u32 ccr;        /* 0x0000 */
  24         u32 ccdr;
  25         u32 csr;
  26         u32 ccsr;
  27         u32 cacrr;      /* 0x0010*/
  28         u32 cbcdr;
  29         u32 cbcmr;
  30         u32 cscmr1;
  31         u32 cscmr2;     /* 0x0020 */
  32         u32 cscdr1;
  33         u32 cs1cdr;
  34         u32 cs2cdr;
  35         u32 cdcdr;      /* 0x0030 */
  36         u32 chsccdr;
  37         u32 cscdr2;
  38         u32 cscdr3;
  39         u32 cscdr4;     /* 0x0040 */
  40         u32 resv0;
  41         u32 cdhipr;
  42         u32 cdcr;
  43         u32 ctor;       /* 0x0050 */
  44         u32 clpcr;
  45         u32 cisr;
  46         u32 cimr;
  47         u32 ccosr;      /* 0x0060 */
  48         u32 cgpr;
  49         u32 CCGR0;
  50         u32 CCGR1;
  51         u32 CCGR2;      /* 0x0070 */
  52         u32 CCGR3;
  53         u32 CCGR4;
  54         u32 CCGR5;
  55         u32 CCGR6;      /* 0x0080 */
  56         u32 CCGR7;
  57         u32 cmeor;
  58         u32 resv[0xfdd];
  59         u32 analog_pll_sys;                     /* 0x4000 */
  60         u32 analog_pll_sys_set;
  61         u32 analog_pll_sys_clr;
  62         u32 analog_pll_sys_tog;
  63         u32 analog_usb1_pll_480_ctrl;           /* 0x4010 */
  64         u32 analog_usb1_pll_480_ctrl_set;
  65         u32 analog_usb1_pll_480_ctrl_clr;
  66         u32 analog_usb1_pll_480_ctrl_tog;
  67         u32 analog_reserved0[4];
  68         u32 analog_pll_528;                     /* 0x4030 */
  69         u32 analog_pll_528_set;
  70         u32 analog_pll_528_clr;
  71         u32 analog_pll_528_tog;
  72         u32 analog_pll_528_ss;                  /* 0x4040 */
  73         u32 analog_reserved1[3];
  74         u32 analog_pll_528_num;                 /* 0x4050 */
  75         u32 analog_reserved2[3];
  76         u32 analog_pll_528_denom;               /* 0x4060 */
  77         u32 analog_reserved3[3];
  78         u32 analog_pll_audio;                   /* 0x4070 */
  79         u32 analog_pll_audio_set;
  80         u32 analog_pll_audio_clr;
  81         u32 analog_pll_audio_tog;
  82         u32 analog_pll_audio_num;               /* 0x4080*/
  83         u32 analog_reserved4[3];
  84         u32 analog_pll_audio_denom;             /* 0x4090 */
  85         u32 analog_reserved5[3];
  86         u32 analog_pll_video;                   /* 0x40a0 */
  87         u32 analog_pll_video_set;
  88         u32 analog_pll_video_clr;
  89         u32 analog_pll_video_tog;
  90         u32 analog_pll_video_num;               /* 0x40b0 */
  91         u32 analog_reserved6[3];
  92         u32 analog_pll_video_denom;             /* 0x40c0 */
  93         u32 analog_reserved7[7];
  94         u32 analog_pll_enet;                    /* 0x40e0 */
  95         u32 analog_pll_enet_set;
  96         u32 analog_pll_enet_clr;
  97         u32 analog_pll_enet_tog;
  98         u32 analog_pfd_480;                     /* 0x40f0 */
  99         u32 analog_pfd_480_set;
 100         u32 analog_pfd_480_clr;
 101         u32 analog_pfd_480_tog;
 102         u32 analog_pfd_528;                     /* 0x4100 */
 103         u32 analog_pfd_528_set;
 104         u32 analog_pfd_528_clr;
 105         u32 analog_pfd_528_tog;
 106         /* PMU Memory Map/Register Definition */
 107         u32 pmu_reg_1p1;
 108         u32 pmu_reg_1p1_set;
 109         u32 pmu_reg_1p1_clr;
 110         u32 pmu_reg_1p1_tog;
 111         u32 pmu_reg_3p0;
 112         u32 pmu_reg_3p0_set;
 113         u32 pmu_reg_3p0_clr;
 114         u32 pmu_reg_3p0_tog;
 115         u32 pmu_reg_2p5;
 116         u32 pmu_reg_2p5_set;
 117         u32 pmu_reg_2p5_clr;
 118         u32 pmu_reg_2p5_tog;
 119         u32 pmu_reg_core;
 120         u32 pmu_reg_core_set;
 121         u32 pmu_reg_core_clr;
 122         u32 pmu_reg_core_tog;
 123         u32 pmu_misc0;
 124         u32 pmu_misc0_set;
 125         u32 pmu_misc0_clr;
 126         u32 pmu_misc0_tog;
 127         u32 pmu_misc1;
 128         u32 pmu_misc1_set;
 129         u32 pmu_misc1_clr;
 130         u32 pmu_misc1_tog;
 131         u32 pmu_misc2;
 132         u32 pmu_misc2_set;
 133         u32 pmu_misc2_clr;
 134         u32 pmu_misc2_tog;
 135         /* TEMPMON Memory Map/Register Definition */
 136         u32 tempsense0;
 137         u32 tempsense0_set;
 138         u32 tempsense0_clr;
 139         u32 tempsense0_tog;
 140         u32 tempsense1;
 141         u32 tempsense1_set;
 142         u32 tempsense1_clr;
 143         u32 tempsense1_tog;
 144         /* USB Analog Memory Map/Register Definition */
 145         u32 usb1_vbus_detect;
 146         u32 usb1_vbus_detect_set;
 147         u32 usb1_vbus_detect_clr;
 148         u32 usb1_vbus_detect_tog;
 149         u32 usb1_chrg_detect;
 150         u32 usb1_chrg_detect_set;
 151         u32 usb1_chrg_detect_clr;
 152         u32 usb1_chrg_detect_tog;
 153         u32 usb1_vbus_det_stat;
 154         u32 usb1_vbus_det_stat_set;
 155         u32 usb1_vbus_det_stat_clr;
 156         u32 usb1_vbus_det_stat_tog;
 157         u32 usb1_chrg_det_stat;
 158         u32 usb1_chrg_det_stat_set;
 159         u32 usb1_chrg_det_stat_clr;
 160         u32 usb1_chrg_det_stat_tog;
 161         u32 usb1_loopback;
 162         u32 usb1_loopback_set;
 163         u32 usb1_loopback_clr;
 164         u32 usb1_loopback_tog;
 165         u32 usb1_misc;
 166         u32 usb1_misc_set;
 167         u32 usb1_misc_clr;
 168         u32 usb1_misc_tog;
 169         u32 usb2_vbus_detect;
 170         u32 usb2_vbus_detect_set;
 171         u32 usb2_vbus_detect_clr;
 172         u32 usb2_vbus_detect_tog;
 173         u32 usb2_chrg_detect;
 174         u32 usb2_chrg_detect_set;
 175         u32 usb2_chrg_detect_clr;
 176         u32 usb2_chrg_detect_tog;
 177         u32 usb2_vbus_det_stat;
 178         u32 usb2_vbus_det_stat_set;
 179         u32 usb2_vbus_det_stat_clr;
 180         u32 usb2_vbus_det_stat_tog;
 181         u32 usb2_chrg_det_stat;
 182         u32 usb2_chrg_det_stat_set;
 183         u32 usb2_chrg_det_stat_clr;
 184         u32 usb2_chrg_det_stat_tog;
 185         u32 usb2_loopback;
 186         u32 usb2_loopback_set;
 187         u32 usb2_loopback_clr;
 188         u32 usb2_loopback_tog;
 189         u32 usb2_misc;
 190         u32 usb2_misc_set;
 191         u32 usb2_misc_clr;
 192         u32 usb2_misc_tog;
 193         u32 digprog;
 194         u32 reserved1[7];
 195         /* For i.MX 6SoloLite */
 196         u32 digprog_sololite;
 197 };
 198 #endif
 199
 200 /* Define the bits in register CCR */
 201 #define MXC_CCM_CCR_RBC_EN                              (1 << 27)
 202 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                 (0x3F << 21)
 203 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET               21
 204 /* CCR_WB does not exist on i.MX6SX/UL */
 205 #define MXC_CCM_CCR_WB_COUNT_MASK                       0x7
 206 #define MXC_CCM_CCR_WB_COUNT_OFFSET                     (1 << 16)
 207 #define MXC_CCM_CCR_COSC_EN                             (1 << 12)
 208 #ifdef CONFIG_MX6SX
 209 #define MXC_CCM_CCR_OSCNT_MASK                          0x7F
 210 #else
 211 #define MXC_CCM_CCR_OSCNT_MASK                          0xFF
 212 #endif
 213 #define MXC_CCM_CCR_OSCNT_OFFSET                        0
 214
 215 /* Define the bits in register CCDR */
 216 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK                   (1 << 16)
 217 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK                   (1 << 17)
 218 /* Exists on i.MX6QP */
 219 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG               (1 << 18)
 220
 221 /* Define the bits in register CSR */
 222 #define MXC_CCM_CSR_COSC_READY                          (1 << 5)
 223 #define MXC_CCM_CSR_REF_EN_B                            (1 << 0)
 224
 225 /* Define the bits in register CCSR */
 226 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS                  (1 << 15)
 227 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS                  (1 << 14)
 228 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS                  (1 << 13)
 229 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS                  (1 << 12)
 230 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS                  (1 << 11)
 231 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS                  (1 << 10)
 232 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS                  (1 << 9)
 233 #define MXC_CCM_CCSR_STEP_SEL                           (1 << 8)
 234 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL                    (1 << 2)
 235 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL                    (1 << 1)
 236 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL                    (1 << 0)
 237
 238 /* Define the bits in register CACRR */
 239 #define MXC_CCM_CACRR_ARM_PODF_OFFSET                   0
 240 #define MXC_CCM_CACRR_ARM_PODF_MASK                     0x7
 241
 242 /* Define the bits in register CBCDR */
 243 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK             (0x7 << 27)
 244 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET           27
 245 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL                   (1 << 26)
 246 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                    (1 << 25)
 247 /* MMDC_CH0 not exists on i.MX6SX */
 248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK                (0x7 << 19)
 249 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET              19
 250 #define MXC_CCM_CBCDR_AXI_PODF_MASK                     (0x7 << 16)
 251 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET                   16
 252 #define MXC_CCM_CBCDR_AHB_PODF_MASK                     (0x7 << 10)
 253 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET                   10
 254 #define MXC_CCM_CBCDR_IPG_PODF_MASK                     (0x3 << 8)
 255 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET                   8
 256 #define MXC_CCM_CBCDR_AXI_ALT_SEL                       (1 << 7)
 257 #define MXC_CCM_CBCDR_AXI_SEL                           (1 << 6)
 258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK                (0x7 << 3)
 259 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET              3
 260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK            (0x7 << 0)
 261 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET          0
 262
 263 /* Define the bits in register CBCMR */
 264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK            (0x7 << 29)
 265 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET          29
 266 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK              (0x7 << 26)
 267 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET            26
 268 /* LCDIF on i.MX6SX/UL */
 269 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK                  (0x7 << 23)
 270 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET                23
 271 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK              (0x7 << 23)
 272 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET            23
 273 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK          (0x3 << 21)
 274 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET        21
 275 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL                  (1 << 20)
 276 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK           (0x3 << 18)
 277 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET         18
 278 #ifndef CONFIG_MX6SX
 279 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK                (0x3 << 16)
 280 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET              16
 281 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK              (0x3 << 14)
 282 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET            14
 283 #endif
 284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK              (0x3 << 12)
 285 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET            12
 286 #ifndef CONFIG_MX6SX
 287 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                    (1 << 11)
 288 #endif
 289 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                  (1 << 10)
 290 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK         (0x3 << 8)
 291 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET       8
 292 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK           (0x3 << 4)
 293 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET         4
 294 /* Exists on i.MX6QP */
 295 #define MXC_CCM_CBCMR_PRE_CLK_SEL                       (1 << 1)
 296
 297 /* Define the bits in register CSCMR1 */
 298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK               (0x3 << 29)
 299 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET             29
 300 /* QSPI1 exist on i.MX6SX/UL */
 301 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                  (0x7 << 26)
 302 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET                26
 303 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK                    (0x3 << 27)
 304 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET                  27
 305 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK          (0x7 << 23)
 306 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET        23
 307 /* LCFIF2_PODF on i.MX6SX */
 308 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK                 (0x7 << 20)
 309 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET               20
 310 /* ACLK_EMI on i.MX6DQ/SDL/DQP */
 311 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK               (0x7 << 20)
 312 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET             20
 313 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
 314 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL                     (1 << 19)
 315 #define MXC_CCM_CSCMR1_BCH_CLK_SEL                      (1 << 18)
 316 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL                   (1 << 19)
 317 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL                   (1 << 18)
 318 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL                   (1 << 17)
 319 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL                   (1 << 16)
 320 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK                (0x3 << 14)
 321 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET              14
 322 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK                (0x3 << 12)
 323 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              12
 324 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << 10)
 325 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              10
 326 /* QSPI1 exist on i.MX6SX/UL */
 327 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK               (0x7 << 7)
 328 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET             7
 329 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
 330 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
 331 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET               6
 332
 333 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                 0x3F
 334
 335 /* Define the bits in register CSCMR2 */
 336 #ifdef CONFIG_MX6SX
 337 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                 (0x7 << 21)
 338 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET               21
 339 #endif
 340 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK                (0x3 << 19)
 341 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET              19
 342 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                  (1 << 11)
 343 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                  (1 << 10)
 344 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
 345 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                 (0x3 << 8)
 346 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET               8
 347
 348 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK                (0x3F << 2)
 349 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET              2
 350
 351 /* Define the bits in register CSCDR1 */
 352 #ifndef CONFIG_MX6SX
 353 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK                (0x7 << 25)
 354 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET              25
 355 #endif
 356 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
 357 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK                   (0x7 << 22)
 358 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET                 22
 359 #define MXC_CCM_CSCDR1_BCH_PODF_MASK                    (0x7 << 19)
 360 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET                  19
 361
 362 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                 (0x7 << 22)
 363 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET               22
 364 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                 (0x7 << 19)
 365 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET               19
 366 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK                 (0x7 << 16)
 367 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET               16
 368 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                 (0x7 << 11)
 369 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET               11
 370 #ifndef CONFIG_MX6SX
 371 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET           8
 372 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK             (0x7 << 8)
 373 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET           6
 374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK             (0x3 << 6)
 375 #endif
 376 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK               0x3F
 377 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET             0
 378 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
 379 #define MXC_CCM_CSCDR1_UART_CLK_SEL                     (1 << 6)
 380
 381 /* Define the bits in register CS1CDR */
 382 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK               (0x3F << 25)
 383 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET             25
 384 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK               (0x7 << 22)
 385 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET             22
 386 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK               (0x3F << 16)
 387 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET             16
 388 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK               (0x3 << 9)
 389 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET             9
 390 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK               (0x7 << 6)
 391 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET             6
 392 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK               0x3F
 393 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET             0
 394
 395 /* Define the bits in register CS2CDR */
 396 /* QSPI2 on i.MX6SX */
 397 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << 21)
 398 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
 399 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                       (((v) & 0x3f) << 21)
 400 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK             (0x7 << 18)
 401 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET           18
 402 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)                       (((v) & 0x7) << 18)
 403 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK              (0x7 << 15)
 404 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET            15
 405 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                        (((v) & 0x7) << 15)
 406
 407 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK               (0x3F << 21)
 408 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET             21
 409 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                 (((v) & 0x3f) << 21)
 410 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK               (0x7 << 18)
 411 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET             18
 412 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                 (((v) & 0x7) << 18)
 413
 414 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP            (0x7 << 15)
 415 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP          15
 416 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v)              (((v) & 0x7) << 15)
 417 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ             (0x3 << 16)
 418 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ           16
 419 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)               (((v) & 0x3) << 16)
 420
 421 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK                \
 422         ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
 423          MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP :         \
 424          MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
 425 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET              \
 426         ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
 427          MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP :       \
 428          MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
 429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)                  \
 430         ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?  \
 431          MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :           \
 432          MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
 433
 434 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK             (0x7 << 12)
 435 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET           12
 436 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK             (0x7 << 9)
 437 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET           9
 438 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK               (0x7 << 6)
 439 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET             6
 440 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK               0x3F
 441 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET             0
 442
 443 /* Define the bits in register CDCDR */
 444 #ifndef CONFIG_MX6SX
 445 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                  (0x7 << 29)
 446 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET                29
 447 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL                    (1 << 28)
 448 #endif
 449 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK              (0x7 << 25)
 450 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET            25
 451 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK              (0x7 << 22)
 452 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET            22
 453 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK               (0x3 << 20)
 454 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET             20
 455 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK              (0x7 << 12)
 456 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET            12
 457 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK              (0x7 << 9)
 458 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET            9
 459 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK               (0x3 << 7)
 460 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET             7
 461
 462 /* Define the bits in register CHSCCDR */
 463 #ifdef CONFIG_MX6SX
 464 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK           (0x7 << 15)
 465 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET         15
 466 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                  (0x7 << 12)
 467 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET                12
 468 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK               (0x7 << 9)
 469 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET             9
 470 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK             (0x7 << 6)
 471 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET           6
 472 #define MXC_CCM_CHSCCDR_M4_PODF_MASK                    (0x7 << 3)
 473 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET                  3
 474 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK                 (0x7)
 475 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET               0
 476 #else
 477 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK       (0x7 << 15)
 478 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET     15
 479 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK              (0x7 << 12)
 480 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET            12
 481 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK           (0x7 << 9)
 482 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET         9
 483 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK       (0x7 << 6)
 484 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET     6
 485 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK              (0x7 << 3)
 486 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET            3
 487 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK           (0x7)
 488 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET         0
 489 #endif
 490
 491 #define CHSCCDR_CLK_SEL_LDB_DI0                         3
 492 #define CHSCCDR_PODF_DIVIDE_BY_3                        2
 493 #define CHSCCDR_IPU_PRE_CLK_540M_PFD                    5
 494
 495 /* Define the bits in register CSCDR2 */
 496 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK              (0x3F << 19)
 497 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET            19
 498 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
 499 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK               (0x1 << 18)
 500 /* LCDIF1 on i.MX6SX/UL */
 501 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK             (0x7 << 15)
 502 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET           15
 503 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK              (0x7 << 12)
 504 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET            12
 505 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK              (0x7 << 9)
 506 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET            9
 507 /* LCDIF2 on i.MX6SX */
 508 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK             (0x7 << 6)
 509 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET           6
 510 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK              (0x7 << 3)
 511 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET            3
 512 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK              (0x7 << 0)
 513 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET             0
 514
 515 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 516 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK       (0x7 << 15)
 517 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET     15
 518 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK              (0x7 << 12)
 519 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET            12
 520 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK           (0x7 << 9)
 521 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET         9
 522 /* All IPU2_DI0 are LCDIF2 on MX6SX */
 523 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK       (0x7 << 6)
 524 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET     6
 525 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK              (0x7 << 3)
 526 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET            3
 527 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK           0x7
 528 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET         0
 529
 530 /* Define the bits in register CSCDR3 */
 531 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK               (0x7 << 16)
 532 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET             16
 533 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK            (0x3 << 14)
 534 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET          14
 535 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK               (0x7 << 11)
 536 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET             11
 537 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK            (0x3 << 9)
 538 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET          9
 539
 540 /* Define the bits in register CDHIPR */
 541 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY                    (1 << 16)
 542 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY              (1 << 5)
 543 #ifndef CONFIG_MX6SX
 544 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY               (1 << 4)
 545 #endif
 546 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY             (1 << 3)
 547 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY               (1 << 2)
 548 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY                    (1 << 1)
 549 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY                    1
 550
 551 /* Define the bits in register CLPCR */
 552 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE                    (1 << 27)
 553 #define MXC_CCM_CLPCR_MASK_SCU_IDLE                     (1 << 26)
 554 #ifndef CONFIG_MX6SX
 555 #define MXC_CCM_CLPCR_MASK_CORE3_WFI                    (1 << 25)
 556 #define MXC_CCM_CLPCR_MASK_CORE2_WFI                    (1 << 24)
 557 #define MXC_CCM_CLPCR_MASK_CORE1_WFI                    (1 << 23)
 558 #endif
 559 #define MXC_CCM_CLPCR_MASK_CORE0_WFI                    (1 << 22)
 560 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS               (1 << 21)
 561 #ifndef CONFIG_MX6SX
 562 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS               (1 << 19)
 563 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                    (1 << 17)
 564 #endif
 565 #define MXC_CCM_CLPCR_WB_PER_AT_LPM                     (1 << 16)
 566 #define MXC_CCM_CLPCR_COSC_PWRDOWN                      (1 << 11)
 567 #define MXC_CCM_CLPCR_STBY_COUNT_MASK                   (0x3 << 9)
 568 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                 9
 569 #define MXC_CCM_CLPCR_VSTBY                             (1 << 8)
 570 #define MXC_CCM_CLPCR_DIS_REF_OSC                       (1 << 7)
 571 #define MXC_CCM_CLPCR_SBYOS                             (1 << 6)
 572 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM                (1 << 5)
 573 #ifndef CONFIG_MX6SX
 574 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                 (0x3 << 3)
 575 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET               3
 576 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY           (1 << 2)
 577 #endif
 578 #define MXC_CCM_CLPCR_LPM_MASK                          0x3
 579 #define MXC_CCM_CLPCR_LPM_OFFSET                        0
 580
 581 /* Define the bits in register CISR */
 582 #define MXC_CCM_CISR_ARM_PODF_LOADED                    (1 << 26)
 583 #ifndef CONFIG_MX6SX
 584 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED               (1 << 23)
 585 #endif
 586 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED              (1 << 22)
 587 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED               (1 << 21)
 588 #define MXC_CCM_CISR_AHB_PODF_LOADED                    (1 << 20)
 589 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED             (1 << 19)
 590 #define MXC_CCM_CISR_AXI_PODF_LOADED                    (1 << 17)
 591 #define MXC_CCM_CISR_COSC_READY                         (1 << 6)
 592 #define MXC_CCM_CISR_LRF_PLL                            1
 593
 594 /* Define the bits in register CIMR */
 595 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED               (1 << 26)
 596 #ifndef CONFIG_MX6SX
 597 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED          (1 << 23)
 598 #endif
 599 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED         (1 << 22)
 600 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED          (1 << 21)
 601 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED               (1 << 20)
 602 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED        (1 << 19)
 603 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED               (1 << 17)
 604 #define MXC_CCM_CIMR_MASK_COSC_READY                    (1 << 6)
 605 #define MXC_CCM_CIMR_MASK_LRF_PLL                       1
 606
 607 /* Define the bits in register CCOSR */
 608 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET                    (1 << 24)
 609 #define MXC_CCM_CCOSR_CKO2_DIV_MASK                     (0x7 << 21)
 610 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                   21
 611 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                   16
 612 #define MXC_CCM_CCOSR_CKO2_SEL_MASK                     (0x1F << 16)
 613 #define MXC_CCM_CCOSR_CLK_OUT_SEL                       (0x1 << 8)
 614 #define MXC_CCM_CCOSR_CKOL_EN                           (0x1 << 7)
 615 #define MXC_CCM_CCOSR_CKOL_DIV_MASK                     (0x7 << 4)
 616 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                   4
 617 #define MXC_CCM_CCOSR_CKOL_SEL_MASK                     0xF
 618 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                   0
 619
 620 /* Define the bits in registers CGPR */
 621 #define MXC_CCM_CGPR_FAST_PLL_EN                        (1 << 16)
 622 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE             (1 << 4)
 623 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS                   (1 << 2)
 624 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER                  1
 625
 626 /* Define the bits in registers CCGRx */
 627 #define MXC_CCM_CCGR_CG_MASK                            3
 628
 629 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET                   0
 630 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
 631 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET                   2
 632 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
 633 #define MXC_CCM_CCGR0_APBHDMA_OFFSET                    4
 634 #define MXC_CCM_CCGR0_APBHDMA_MASK                      (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
 635 #define MXC_CCM_CCGR0_ASRC_OFFSET                       6
 636 #define MXC_CCM_CCGR0_ASRC_MASK                         (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
 637 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET            8
 638 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK              (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
 639 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET          10
 640 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK            (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
 641 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET           12
 642 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK             (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
 643 #define MXC_CCM_CCGR0_CAN1_OFFSET                       14
 644 #define MXC_CCM_CCGR0_CAN1_MASK                         (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
 645 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET                16
 646 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK                  (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
 647 #define MXC_CCM_CCGR0_CAN2_OFFSET                       18
 648 #define MXC_CCM_CCGR0_CAN2_MASK                         (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
 649 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET                20
 650 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK                  (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
 651 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET            22
 652 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK              (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
 653 #define MXC_CCM_CCGR0_DCIC1_OFFSET                      24
 654 #define MXC_CCM_CCGR0_DCIC1_MASK                        (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 655 #define MXC_CCM_CCGR0_DCIC2_OFFSET                      26
 656 #define MXC_CCM_CCGR0_DCIC2_MASK                        (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
 657 #ifdef CONFIG_MX6SX
 658 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET                   30
 659 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
 660 #else
 661 #define MXC_CCM_CCGR0_DTCP_OFFSET                       28
 662 #define MXC_CCM_CCGR0_DTCP_MASK                         (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
 663 #endif
 664
 665 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET                    0
 666 #define MXC_CCM_CCGR1_ECSPI1S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
 667 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET                    2
 668 #define MXC_CCM_CCGR1_ECSPI2S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
 669 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET                    4
 670 #define MXC_CCM_CCGR1_ECSPI3S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
 671 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET                    6
 672 #define MXC_CCM_CCGR1_ECSPI4S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 673 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                    8
 674 #define MXC_CCM_CCGR1_ECSPI5S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
 675 /* CCGR1_ENET does not exist on i.MX6SX/UL */
 676 #define MXC_CCM_CCGR1_ENET_OFFSET                       10
 677 #define MXC_CCM_CCGR1_ENET_MASK                         (3 << MXC_CCM_CCGR1_ENET_OFFSET)
 678 #define MXC_CCM_CCGR1_EPIT1S_OFFSET                     12
 679 #define MXC_CCM_CCGR1_EPIT1S_MASK                       (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
 680 #define MXC_CCM_CCGR1_EPIT2S_OFFSET                     14
 681 #define MXC_CCM_CCGR1_EPIT2S_MASK                       (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 682 #define MXC_CCM_CCGR1_ESAIS_OFFSET                      16
 683 #define MXC_CCM_CCGR1_ESAIS_MASK                        (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
 684 #ifdef CONFIG_MX6SX
 685 #define MXC_CCM_CCGR1_WAKEUP_OFFSET                     18
 686 #define MXC_CCM_CCGR1_WAKEUP_MASK                       (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
 687 #endif
 688 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET                    20
 689 #define MXC_CCM_CCGR1_GPT_BUS_MASK                      (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 690 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                 22
 691 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK                   (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
 692 #ifndef CONFIG_MX6SX
 693 #define MXC_CCM_CCGR1_GPU2D_OFFSET                      24
 694 #define MXC_CCM_CCGR1_GPU2D_MASK                        (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 695 #endif
 696 #define MXC_CCM_CCGR1_GPU3D_OFFSET                      26
 697 #define MXC_CCM_CCGR1_GPU3D_MASK                        (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
 698 #ifdef CONFIG_MX6SX
 699 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET                    28
 700 #define MXC_CCM_CCGR1_OCRAM_S_MASK                      (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
 701 #define MXC_CCM_CCGR1_CANFD_OFFSET                      30
 702 #define MXC_CCM_CCGR1_CANFD_MASK                        (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
 703 #endif
 704
 705 #ifndef CONFIG_MX6SX
 706 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET            0
 707 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK              (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
 708 #else
 709 #define MXC_CCM_CCGR2_CSI_OFFSET                        2
 710 #define MXC_CCM_CCGR2_CSI_MASK                          (3 << MXC_CCM_CCGR2_CSI_OFFSET)
 711 #endif
 712 #ifndef CONFIG_MX6SX
 713 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET            4
 714 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK              (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 715 #endif
 716 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET                6
 717 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
 718 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET                8
 719 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 720 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET                10
 721 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
 722 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET                8
 723 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK                  (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 724 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                 12
 725 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                   (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 726 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET           14
 727 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK             (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
 728 #define MXC_CCM_CCGR2_IPMUX1_OFFSET                     16
 729 #define MXC_CCM_CCGR2_IPMUX1_MASK                       (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
 730 #define MXC_CCM_CCGR2_IPMUX2_OFFSET                     18
 731 #define MXC_CCM_CCGR2_IPMUX2_MASK                       (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
 732 #define MXC_CCM_CCGR2_IPMUX3_OFFSET                     20
 733 #define MXC_CCM_CCGR2_IPMUX3_MASK                       (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 734 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET  22
 735 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK    (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
 736 /* i.MX6SX/UL LCD and PXP */
 737 #define MXC_CCM_CCGR2_LCD_OFFSET                        28
 738 #define MXC_CCM_CCGR2_LCD_MASK                          (3 << MXC_CCM_CCGR2_LCD_OFFSET)
 739 #define MXC_CCM_CCGR2_PXP_OFFSET                        30
 740 #define MXC_CCM_CCGR2_PXP_MASK                          (3 << MXC_CCM_CCGR2_PXP_OFFSET)
 741
 742 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET   24
 743 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK     (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
 744 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
 745 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK   (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 746
 747 /* Exist on i.MX6SX */
 748 #define MXC_CCM_CCGR3_M4_OFFSET                                 2
 749 #define MXC_CCM_CCGR3_M4_MASK                                   (3 << MXC_CCM_CCGR3_M4_OFFSET)
 750 #define MXC_CCM_CCGR3_ENET_OFFSET                               4
 751 #define MXC_CCM_CCGR3_ENET_MASK                                 (3 << MXC_CCM_CCGR3_ENET_OFFSET)
 752 #define MXC_CCM_CCGR3_QSPI_OFFSET                               14
 753 #define MXC_CCM_CCGR3_QSPI_MASK                                 (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
 754
 755 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET                           0
 756 #define MXC_CCM_CCGR3_IPU1_IPU_MASK                             (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
 757 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET                       2
 758 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK                         (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
 759 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET                       4
 760 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK                         (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
 761
 762 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET                           6
 763 #define MXC_CCM_CCGR3_IPU2_IPU_MASK                             (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
 764 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET                       8
 765 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK                         (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
 766 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET                       10
 767 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                         (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 768 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                            12
 769 #define MXC_CCM_CCGR3_LDB_DI0_MASK                              (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
 770
 771 /* QSPI1 exists on i.MX6SX/UL */
 772 #define MXC_CCM_CCGR3_QSPI1_OFFSET                              14
 773 #define MXC_CCM_CCGR3_QSPI1_MASK                                (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
 774
 775 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET                            14
 776 #define MXC_CCM_CCGR3_LDB_DI1_MASK                              (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
 777 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET                      16
 778 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK                        (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
 779
 780 /* A7_CLKDIV/WDOG1 on i.MX6UL */
 781 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET                   16
 782 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK                     (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
 783 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET                    18
 784 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK                      (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
 785
 786 #define MXC_CCM_CCGR3_MLB_OFFSET                                18
 787 #define MXC_CCM_CCGR3_MLB_MASK                                  (3 << MXC_CCM_CCGR3_MLB_OFFSET)
 788 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET        20
 789 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK          (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
 790 #ifndef CONFIG_MX6SX
 791 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET        22
 792 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK          (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 793 #endif
 794 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET               24
 795 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK                 (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
 796 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET               26
 797 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                 (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
 798
 799 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET                           6
 800 #define MXC_CCM_CCGR3_DISP_AXI_MASK                             (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
 801 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET                         8
 802 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
 803 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET                         10
 804 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
 805 /* AXI on i.MX6UL */
 806 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET                            28
 807 #define MXC_CCM_CCGR3_AXI_CLK_MASK                              (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
 808 #define MXC_CCM_CCGR3_OCRAM_OFFSET                              28
 809 #define MXC_CCM_CCGR3_OCRAM_MASK                                (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
 810
 811 /* GPIO4 on i.MX6UL */
 812 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET                          30
 813 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK                            (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
 814
 815 #ifndef CONFIG_MX6SX
 816 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                       30
 817 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                         (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 818 #endif
 819
 820 #define MXC_CCM_CCGR4_PCIE_OFFSET                               0
 821 #define MXC_CCM_CCGR4_PCIE_MASK                                 (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
 822 /* QSPI2 on i.MX6SX */
 823 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET                         10
 824 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK                           (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
 825 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET               8
 826 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK                 (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
 827 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET                 12
 828 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK                   (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
 829 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET      14
 830 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK        (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
 831 #define MXC_CCM_CCGR4_PWM1_OFFSET                               16
 832 #define MXC_CCM_CCGR4_PWM1_MASK                                 (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
 833 #define MXC_CCM_CCGR4_PWM2_OFFSET                               18
 834 #define MXC_CCM_CCGR4_PWM2_MASK                                 (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
 835 #define MXC_CCM_CCGR4_PWM3_OFFSET                               20
 836 #define MXC_CCM_CCGR4_PWM3_MASK                                 (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
 837 #define MXC_CCM_CCGR4_PWM4_OFFSET                               22
 838 #define MXC_CCM_CCGR4_PWM4_MASK                                 (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
 839 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET            24
 840 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK              (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
 841 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET       26
 842 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK         (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
 843 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET   28
 844 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK     (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
 845 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET           30
 846 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK             (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
 847
 848 #define MXC_CCM_CCGR5_ROM_OFFSET                        0
 849 #define MXC_CCM_CCGR5_ROM_MASK                          (3 << MXC_CCM_CCGR5_ROM_OFFSET)
 850 #ifndef CONFIG_MX6SX
 851 #define MXC_CCM_CCGR5_SATA_OFFSET                       4
 852 #define MXC_CCM_CCGR5_SATA_MASK                         (3 << MXC_CCM_CCGR5_SATA_OFFSET)
 853 #endif
 854 #define MXC_CCM_CCGR5_SDMA_OFFSET                       6
 855 #define MXC_CCM_CCGR5_SDMA_MASK                         (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
 856 #define MXC_CCM_CCGR5_SPBA_OFFSET                       12
 857 #define MXC_CCM_CCGR5_SPBA_MASK                         (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
 858 #define MXC_CCM_CCGR5_SPDIF_OFFSET                      14
 859 #define MXC_CCM_CCGR5_SPDIF_MASK                        (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
 860 #define MXC_CCM_CCGR5_SSI1_OFFSET                       18
 861 #define MXC_CCM_CCGR5_SSI1_MASK                         (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
 862 #define MXC_CCM_CCGR5_SSI2_OFFSET                       20
 863 #define MXC_CCM_CCGR5_SSI2_MASK                         (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
 864 #define MXC_CCM_CCGR5_SSI3_OFFSET                       22
 865 #define MXC_CCM_CCGR5_SSI3_MASK                         (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
 866 #define MXC_CCM_CCGR5_UART_OFFSET                       24
 867 #define MXC_CCM_CCGR5_UART_MASK                         (3 << MXC_CCM_CCGR5_UART_OFFSET)
 868 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET                26
 869 #define MXC_CCM_CCGR5_UART_SERIAL_MASK                  (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
 870 #ifdef CONFIG_MX6SX
 871 #define MXC_CCM_CCGR5_SAI1_OFFSET                       20
 872 #define MXC_CCM_CCGR5_SAI1_MASK                         (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
 873 #define MXC_CCM_CCGR5_SAI2_OFFSET                       30
 874 #define MXC_CCM_CCGR5_SAI2_MASK                         (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
 875 #endif
 876
 877 /* PRG_CLK0 exists on i.MX6QP */
 878 #define MXC_CCM_CCGR6_PRG_CLK0_MASK             (3 << 24)
 879
 880 #define MXC_CCM_CCGR6_USBOH3_OFFSET             0
 881 #define MXC_CCM_CCGR6_USBOH3_MASK               (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
 882 #define MXC_CCM_CCGR6_USDHC1_OFFSET             2
 883 #define MXC_CCM_CCGR6_USDHC1_MASK               (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
 884 #define MXC_CCM_CCGR6_USDHC2_OFFSET             4
 885 #define MXC_CCM_CCGR6_USDHC2_MASK               (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
 886 /* GPMI/BCH on i.MX6UL */
 887 #define MXC_CCM_CCGR6_BCH_OFFSET                6
 888 #define MXC_CCM_CCGR6_BCH_MASK                  (3 << MXC_CCM_CCGR6_BCH_OFFSET)
 889 #define MXC_CCM_CCGR6_GPMI_OFFSET               8
 890 #define MXC_CCM_CCGR6_GPMI_MASK         (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
 891
 892 #define MXC_CCM_CCGR6_USDHC3_OFFSET             6
 893 #define MXC_CCM_CCGR6_USDHC3_MASK               (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
 894 #define MXC_CCM_CCGR6_USDHC4_OFFSET             8
 895 #define MXC_CCM_CCGR6_USDHC4_MASK               (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 896 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET           10
 897 #define MXC_CCM_CCGR6_EMI_SLOW_MASK             (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
 898 /* The following *CCGR6* exist only i.MX6SX */
 899 #define MXC_CCM_CCGR6_PWM8_OFFSET               16
 900 #define MXC_CCM_CCGR6_PWM8_MASK                 (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
 901 #define MXC_CCM_CCGR6_VADC_OFFSET               20
 902 #define MXC_CCM_CCGR6_VADC_MASK                 (3 << MXC_CCM_CCGR6_VADC_OFFSET)
 903 #define MXC_CCM_CCGR6_GIS_OFFSET                22
 904 #define MXC_CCM_CCGR6_GIS_MASK                  (3 << MXC_CCM_CCGR6_GIS_OFFSET)
 905 #define MXC_CCM_CCGR6_I2C4_OFFSET               24
 906 #define MXC_CCM_CCGR6_I2C4_MASK                 (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
 907 #define MXC_CCM_CCGR6_PWM5_OFFSET               26
 908 #define MXC_CCM_CCGR6_PWM5_MASK                 (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
 909 #define MXC_CCM_CCGR6_PWM6_OFFSET               28
 910 #define MXC_CCM_CCGR6_PWM6_MASK                 (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
 911 #define MXC_CCM_CCGR6_PWM7_OFFSET               30
 912 #define MXC_CCM_CCGR6_PWM7_MASK                 (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
 913 /* The two does not exist on i.MX6SX */
 914 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET          12
 915 #define MXC_CCM_CCGR6_VDOAXICLK_MASK            (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
 916
 917 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
 918 #define BP_ANADIG_PLL_SYS_RSVD0      20
 919 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
 920 #define BF_ANADIG_PLL_SYS_RSVD0(v)  \
 921         (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
 922 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
 923 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
 924 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
 925 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
 926 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
 927 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
 928 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  \
 929         (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
 930 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
 931 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
 932 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
 933 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
 934 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
 935 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
 936 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
 937 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
 938 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
 939 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
 940 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
 941 #define BP_ANADIG_PLL_SYS_DIV_SELECT      0
 942 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
 943 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  \
 944         (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
 945
 946 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
 947 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1      17
 948 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
 949 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v)  \
 950         (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
 951 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
 952 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
 953 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
 954 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  \
 955         (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
 956 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
 957 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
 958 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
 959 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
 960 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
 961 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
 962 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
 963 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
 964 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
 965 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
 966 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
 967 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
 968 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
 969 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
 970 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
 971 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  \
 972         (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
 973 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
 974 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
 975 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  \
 976         (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
 977
 978 #define BM_ANADIG_PLL_528_LOCK 0x80000000
 979 #define BP_ANADIG_PLL_528_RSVD1      19
 980 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
 981 #define BF_ANADIG_PLL_528_RSVD1(v)  \
 982         (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
 983 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
 984 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
 985 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
 986 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
 987 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
 988 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  \
 989         (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
 990 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
 991 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
 992 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
 993 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
 994 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
 995 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
 996 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
 997 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
 998 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
 999 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
1000 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
1001 #define BP_ANADIG_PLL_528_RSVD0      1
1002 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
1003 #define BF_ANADIG_PLL_528_RSVD0(v)  \
1004         (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1005 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
1006
1007 #define BP_ANADIG_PLL_528_SS_STOP      16
1008 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
1009 #define BF_ANADIG_PLL_528_SS_STOP(v) \
1010         (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1011 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
1012 #define BP_ANADIG_PLL_528_SS_STEP      0
1013 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
1014 #define BF_ANADIG_PLL_528_SS_STEP(v)  \
1015         (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1016
1017 #define BP_ANADIG_PLL_528_NUM_RSVD0      30
1018 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
1019 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
1020         (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1021 #define BP_ANADIG_PLL_528_NUM_A      0
1022 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
1023 #define BF_ANADIG_PLL_528_NUM_A(v)  \
1024         (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1025
1026 #define BP_ANADIG_PLL_528_DENOM_RSVD0      30
1027 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
1028 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
1029         (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1030 #define BP_ANADIG_PLL_528_DENOM_B      0
1031 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
1032 #define BF_ANADIG_PLL_528_DENOM_B(v)  \
1033         (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1034
1035 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
1036 #define BP_ANADIG_PLL_AUDIO_RSVD0      22
1037 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
1038 #define BF_ANADIG_PLL_AUDIO_RSVD0(v)  \
1039         (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1040 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
1041 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
1042 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
1043 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  \
1044         (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1045 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
1046 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
1047 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
1048 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
1049 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
1050 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  \
1051         (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1052 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
1053 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1054 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1055 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
1056 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
1057 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
1058 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
1059 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
1060 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
1061 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
1062 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
1063 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
1064 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
1065 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  \
1066         (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1067
1068 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0      30
1069 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
1070 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
1071         (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1072 #define BP_ANADIG_PLL_AUDIO_NUM_A      0
1073 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
1074 #define BF_ANADIG_PLL_AUDIO_NUM_A(v)  \
1075         (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1076
1077 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0      30
1078 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
1079 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
1080         (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1081 #define BP_ANADIG_PLL_AUDIO_DENOM_B      0
1082 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
1083 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  \
1084         (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1085
1086 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
1087 #define BP_ANADIG_PLL_VIDEO_RSVD0      22
1088 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
1089 #define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
1090         (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1091 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
1092 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT      19
1093 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
1094 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)  \
1095         (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1096 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
1097 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
1098 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
1099 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
1100 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
1101 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  \
1102         (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1103 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
1104 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1105 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1106 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
1107 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
1108 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
1109 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
1110 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
1111 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
1112 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
1113 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
1114 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
1115 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
1116 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  \
1117         (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1118
1119 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0      30
1120 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
1121 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
1122         (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1123 #define BP_ANADIG_PLL_VIDEO_NUM_A      0
1124 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
1125 #define BF_ANADIG_PLL_VIDEO_NUM_A(v)  \
1126         (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1127
1128 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0      30
1129 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
1130 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
1131         (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1132 #define BP_ANADIG_PLL_VIDEO_DENOM_B      0
1133 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
1134 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  \
1135         (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1136
1137 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
1138 #define BP_ANADIG_PLL_ENET_RSVD1      21
1139 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
1140 #define BF_ANADIG_PLL_ENET_RSVD1(v)  \
1141         (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1142 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
1143 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
1144 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
1145 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
1146 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
1147 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
1148 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
1149 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
1150 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  \
1151         (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1152 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
1153 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1154 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1155 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
1156 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1157 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1158 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1159 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1160 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1161 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1162 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1163 #define BP_ANADIG_PLL_ENET_RSVD0      2
1164 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1165 #define BF_ANADIG_PLL_ENET_RSVD0(v)  \
1166         (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1167 #define BP_ANADIG_PLL_ENET_DIV_SELECT      0
1168 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1169 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
1170         (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1171
1172 /* ENET2 for i.MX6SX/UL */
1173 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
1174 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
1175 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \
1176         (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
1177
1178 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1179 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1180 #define BP_ANADIG_PFD_480_PFD3_FRAC      24
1181 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1182 #define BF_ANADIG_PFD_480_PFD3_FRAC(v)  \
1183         (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1184 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1185 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1186 #define BP_ANADIG_PFD_480_PFD2_FRAC      16
1187 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1188 #define BF_ANADIG_PFD_480_PFD2_FRAC(v)  \
1189         (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1190 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1191 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1192 #define BP_ANADIG_PFD_480_PFD1_FRAC      8
1193 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1194 #define BF_ANADIG_PFD_480_PFD1_FRAC(v)  \
1195         (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1196 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1197 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1198 #define BP_ANADIG_PFD_480_PFD0_FRAC      0
1199 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1200 #define BF_ANADIG_PFD_480_PFD0_FRAC(v)  \
1201         (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1202
1203 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1204 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1205 #define BP_ANADIG_PFD_528_PFD3_FRAC      24
1206 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1207 #define BF_ANADIG_PFD_528_PFD3_FRAC(v)  \
1208         (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1209 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1210 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1211 #define BP_ANADIG_PFD_528_PFD2_FRAC      16
1212 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1213 #define BF_ANADIG_PFD_528_PFD2_FRAC(v)  \
1214         (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1215 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1216 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1217 #define BP_ANADIG_PFD_528_PFD1_FRAC      8
1218 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1219 #define BF_ANADIG_PFD_528_PFD1_FRAC(v)  \
1220         (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1221 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1222 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1223 #define BP_ANADIG_PFD_528_PFD0_FRAC      0
1224 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1225 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
1226         (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1227
1228 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1229
1230 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
1231 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23
1232
1233 #define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
1234 #define BP_PMU_MISC2_AUDIO_DIV_LSB 15
1235
1236 #define PMU_MISC2_AUDIO_DIV(v) \
1237         (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
1238         (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
1239         ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
1240          BP_PMU_MISC2_AUDIO_DIV_LSB))
1241
1242 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */