arch/arm/include/asm/arch-omap3/mmc_host_def.h

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Syed Mohammed Khasim <khasim@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef MMC_HOST_DEF_H
  26 #define MMC_HOST_DEF_H
  27
  28 /* T2 Register definitions */
  29 #define T2_BASE                 0x48002000
  30
  31 typedef struct t2 {
  32         unsigned char res1[0x274];      /* 0x000 */
  33         unsigned int devconf0;          /* 0x274 */
  34         unsigned char res2[0x060];      /* 0x278 */
  35         unsigned int devconf1;          /* 0x2D8 */
  36         unsigned char res3[0x16C];      /* 0x2DC */
  37         unsigned int ctl_prog_io1;      /* 0x448 */
  38         unsigned char res4[0x0D4];      /* 0x44C */
  39         unsigned int pbias_lite;        /* 0x520 */
  40 } t2_t;
  41
  42 #define MMCSDIO1ADPCLKISEL              (1 << 24)
  43 #define MMCSDIO2ADPCLKISEL              (1 << 6)
  44
  45 #define EN_MMC1                         (1 << 24)
  46 #define EN_MMC2                         (1 << 25)
  47 #define EN_MMC3                         (1 << 30)
  48
  49 #define PBIASLITEPWRDNZ0                (1 << 1)
  50 #define PBIASSPEEDCTRL0                 (1 << 2)
  51 #define PBIASLITEPWRDNZ1                (1 << 9)
  52
  53 #define CTLPROGIO1SPEEDCTRL             (1 << 20)
  54
  55 /*
  56  * OMAP HSMMC register definitions
  57  */
  58 #define OMAP_HSMMC1_BASE        0x4809C000
  59 #define OMAP_HSMMC2_BASE        0x480B4000
  60 #define OMAP_HSMMC3_BASE        0x480AD000
  61
  62 struct hsmmc {
  63         unsigned char res1[0x10];
  64         unsigned int sysconfig;         /* 0x10 */
  65         unsigned int sysstatus;         /* 0x14 */
  66         unsigned char res2[0x14];
  67         unsigned int con;               /* 0x2C */
  68         unsigned char res3[0xD4];
  69         unsigned int blk;               /* 0x104 */
  70         unsigned int arg;               /* 0x108 */
  71         unsigned int cmd;               /* 0x10C */
  72         unsigned int rsp10;             /* 0x110 */
  73         unsigned int rsp32;             /* 0x114 */
  74         unsigned int rsp54;             /* 0x118 */
  75         unsigned int rsp76;             /* 0x11C */
  76         unsigned int data;              /* 0x120 */
  77         unsigned int pstate;            /* 0x124 */
  78         unsigned int hctl;              /* 0x128 */
  79         unsigned int sysctl;            /* 0x12C */
  80         unsigned int stat;              /* 0x130 */
  81         unsigned int ie;                /* 0x134 */
  82         unsigned char res4[0x8];
  83         unsigned int capa;              /* 0x140 */
  84 };
  85
  86 /*
  87  * OMAP HS MMC Bit definitions
  88  */
  89 #define MMC_SOFTRESET                   (0x1 << 1)
  90 #define RESETDONE                       (0x1 << 0)
  91 #define NOOPENDRAIN                     (0x0 << 0)
  92 #define OPENDRAIN                       (0x1 << 0)
  93 #define OD                              (0x1 << 0)
  94 #define INIT_NOINIT                     (0x0 << 1)
  95 #define INIT_INITSTREAM                 (0x1 << 1)
  96 #define HR_NOHOSTRESP                   (0x0 << 2)
  97 #define STR_BLOCK                       (0x0 << 3)
  98 #define MODE_FUNC                       (0x0 << 4)
  99 #define DW8_1_4BITMODE                  (0x0 << 5)
 100 #define MIT_CTO                         (0x0 << 6)
 101 #define CDP_ACTIVEHIGH                  (0x0 << 7)
 102 #define WPP_ACTIVEHIGH                  (0x0 << 8)
 103 #define RESERVED_MASK                   (0x3 << 9)
 104 #define CTPL_MMC_SD                     (0x0 << 11)
 105 #define BLEN_512BYTESLEN                (0x200 << 0)
 106 #define NBLK_STPCNT                     (0x0 << 16)
 107 #define DE_DISABLE                      (0x0 << 0)
 108 #define BCE_DISABLE                     (0x0 << 1)
 109 #define BCE_ENABLE                      (0x1 << 1)
 110 #define ACEN_DISABLE                    (0x0 << 2)
 111 #define DDIR_OFFSET                     (4)
 112 #define DDIR_MASK                       (0x1 << 4)
 113 #define DDIR_WRITE                      (0x0 << 4)
 114 #define DDIR_READ                       (0x1 << 4)
 115 #define MSBS_SGLEBLK                    (0x0 << 5)
 116 #define MSBS_MULTIBLK                   (0x1 << 5)
 117 #define RSP_TYPE_OFFSET                 (16)
 118 #define RSP_TYPE_MASK                   (0x3 << 16)
 119 #define RSP_TYPE_NORSP                  (0x0 << 16)
 120 #define RSP_TYPE_LGHT136                (0x1 << 16)
 121 #define RSP_TYPE_LGHT48                 (0x2 << 16)
 122 #define RSP_TYPE_LGHT48B                (0x3 << 16)
 123 #define CCCE_NOCHECK                    (0x0 << 19)
 124 #define CCCE_CHECK                      (0x1 << 19)
 125 #define CICE_NOCHECK                    (0x0 << 20)
 126 #define CICE_CHECK                      (0x1 << 20)
 127 #define DP_OFFSET                       (21)
 128 #define DP_MASK                         (0x1 << 21)
 129 #define DP_NO_DATA                      (0x0 << 21)
 130 #define DP_DATA                         (0x1 << 21)
 131 #define CMD_TYPE_NORMAL                 (0x0 << 22)
 132 #define INDEX_OFFSET                    (24)
 133 #define INDEX_MASK                      (0x3f << 24)
 134 #define INDEX(i)                        (i << 24)
 135 #define DATI_MASK                       (0x1 << 1)
 136 #define CMDI_MASK                       (0x1 << 0)
 137 #define DTW_1_BITMODE                   (0x0 << 1)
 138 #define DTW_4_BITMODE                   (0x1 << 1)
 139 #define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
 140 #define SDBP_PWROFF                     (0x0 << 8)
 141 #define SDBP_PWRON                      (0x1 << 8)
 142 #define SDVS_1V8                        (0x5 << 9)
 143 #define SDVS_3V0                        (0x6 << 9)
 144 #define ICE_MASK                        (0x1 << 0)
 145 #define ICE_STOP                        (0x0 << 0)
 146 #define ICS_MASK                        (0x1 << 1)
 147 #define ICS_NOTREADY                    (0x0 << 1)
 148 #define ICE_OSCILLATE                   (0x1 << 0)
 149 #define CEN_MASK                        (0x1 << 2)
 150 #define CEN_DISABLE                     (0x0 << 2)
 151 #define CEN_ENABLE                      (0x1 << 2)
 152 #define CLKD_OFFSET                     (6)
 153 #define CLKD_MASK                       (0x3FF << 6)
 154 #define DTO_MASK                        (0xF << 16)
 155 #define DTO_15THDTO                     (0xE << 16)
 156 #define SOFTRESETALL                    (0x1 << 24)
 157 #define CC_MASK                         (0x1 << 0)
 158 #define TC_MASK                         (0x1 << 1)
 159 #define BWR_MASK                        (0x1 << 4)
 160 #define BRR_MASK                        (0x1 << 5)
 161 #define ERRI_MASK                       (0x1 << 15)
 162 #define IE_CC                           (0x01 << 0)
 163 #define IE_TC                           (0x01 << 1)
 164 #define IE_BWR                          (0x01 << 4)
 165 #define IE_BRR                          (0x01 << 5)
 166 #define IE_CTO                          (0x01 << 16)
 167 #define IE_CCRC                         (0x01 << 17)
 168 #define IE_CEB                          (0x01 << 18)
 169 #define IE_CIE                          (0x01 << 19)
 170 #define IE_DTO                          (0x01 << 20)
 171 #define IE_DCRC                         (0x01 << 21)
 172 #define IE_DEB                          (0x01 << 22)
 173 #define IE_CERR                         (0x01 << 28)
 174 #define IE_BADA                         (0x01 << 29)
 175
 176 #define VS30_3V0SUP                     (1 << 25)
 177 #define VS18_1V8SUP                     (1 << 26)
 178
 179 /* Driver definitions */
 180 #define MMCSD_SECTOR_SIZE               512
 181 #define MMC_CARD                        0
 182 #define SD_CARD                         1
 183 #define BYTE_MODE                       0
 184 #define SECTOR_MODE                     1
 185 #define CLK_INITSEQ                     0
 186 #define CLK_400KHZ                      1
 187 #define CLK_MISC                        2
 188
 189 #define RSP_TYPE_NONE   (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 190 #define MMC_CMD0        (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 191
 192 /* Clock Configurations and Macros */
 193 #define MMC_CLOCK_REFERENCE     96 /* MHz */
 194
 195 #define mmc_reg_out(addr, mask, val)\
 196         writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 197
 198 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
 199
 200 #endif /* MMC_HOST_DEF_H */