arch/arm/include/asm/arch-omap5/omap.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Authors:
   6  *      Aneesh V <aneesh@ti.com>
   7  *      Sricharan R <r.sricharan@ti.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef _OMAP5_H_
  29 #define _OMAP5_H_
  30
  31 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  32 #include <asm/types.h>
  33 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  34
  35 /*
  36  * L4 Peripherals - L4 Wakeup and L4 Core now
  37  */
  38 #define OMAP54XX_L4_CORE_BASE   0x4A000000
  39 #define OMAP54XX_L4_WKUP_BASE   0x4Ae00000
  40 #define OMAP54XX_L4_PER_BASE    0x48000000
  41
  42 #define OMAP54XX_DRAM_ADDR_SPACE_START  0x80000000
  43 #define OMAP54XX_DRAM_ADDR_SPACE_END    0xD0000000
  44 #define DRAM_ADDR_SPACE_START   OMAP54XX_DRAM_ADDR_SPACE_START
  45 #define DRAM_ADDR_SPACE_END     OMAP54XX_DRAM_ADDR_SPACE_END
  46
  47 /* CONTROL */
  48 #define CTRL_BASE               (OMAP54XX_L4_CORE_BASE + 0x2000)
  49 #define CONTROL_PADCONF_CORE    (CTRL_BASE + 0x0800)
  50 #define CONTROL_PADCONF_WKUP    (OMAP54XX_L4_WKUP_BASE + 0xc800)
  51
  52 /* LPDDR2 IO regs. To be verified */
  53 #define LPDDR2_IO_REGS_BASE     0x4A100638
  54
  55 /* CONTROL_ID_CODE */
  56 #define CONTROL_ID_CODE         (CTRL_BASE + 0x204)
  57
  58 /* To be verified */
  59 #define OMAP5_CONTROL_ID_CODE_ES1_0     0x0B85202F
  60
  61 /* STD_FUSE_PROD_ID_1 */
  62 #define STD_FUSE_PROD_ID_1              (CTRL_BASE + 0x218)
  63 #define PROD_ID_1_SILICON_TYPE_SHIFT    16
  64 #define PROD_ID_1_SILICON_TYPE_MASK     (3 << 16)
  65
  66 /* UART */
  67 #define UART1_BASE              (OMAP54XX_L4_PER_BASE + 0x6a000)
  68 #define UART2_BASE              (OMAP54XX_L4_PER_BASE + 0x6c000)
  69 #define UART3_BASE              (OMAP54XX_L4_PER_BASE + 0x20000)
  70
  71 /* General Purpose Timers */
  72 #define GPT1_BASE               (OMAP54XX_L4_WKUP_BASE + 0x18000)
  73 #define GPT2_BASE               (OMAP54XX_L4_PER_BASE  + 0x32000)
  74 #define GPT3_BASE               (OMAP54XX_L4_PER_BASE  + 0x34000)
  75
  76 /* Watchdog Timer2 - MPU watchdog */
  77 #define WDT2_BASE               (OMAP54XX_L4_WKUP_BASE + 0x14000)
  78
  79 /* 32KTIMER */
  80 #define SYNC_32KTIMER_BASE      (OMAP54XX_L4_WKUP_BASE + 0x4000)
  81
  82 /* GPMC */
  83 #define OMAP54XX_GPMC_BASE      0x50000000
  84
  85 /* SYSTEM CONTROL MODULE */
  86 #define SYSCTRL_GENERAL_CORE_BASE       0x4A002000
  87
  88 /*
  89  * Hardware Register Details
  90  */
  91
  92 /* Watchdog Timer */
  93 #define WD_UNLOCK1              0xAAAA
  94 #define WD_UNLOCK2              0x5555
  95
  96 /* GP Timer */
  97 #define TCLR_ST                 (0x1 << 0)
  98 #define TCLR_AR                 (0x1 << 1)
  99 #define TCLR_PRE                (0x1 << 5)
 100
 101 /*
 102  * PRCM
 103  */
 104
 105 /* PRM */
 106 #define PRM_BASE                0x4AE06000
 107 #define PRM_DEVICE_BASE         (PRM_BASE + 0x1B00)
 108
 109 #define PRM_RSTCTRL             PRM_DEVICE_BASE
 110 #define PRM_RSTCTRL_RESET       0x01
 111
 112 /* Control Module */
 113 #define LDOSRAM_ACTMODE_VSET_IN_MASK    (0x1F << 5)
 114 #define LDOSRAM_VOLT_CTRL_OVERRIDE      0x0401040f
 115 #define CONTROL_EFUSE_1_OVERRIDE        0x1C4D0110
 116 #define CONTROL_EFUSE_2_OVERRIDE        0x00084000
 117
 118 /* LPDDR2 IO regs */
 119 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN      0x1C1C1C1C
 120 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER    0x9E9E9E9E
 121 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN     0x7C7C7C7C
 122 #define LPDDR2IO_GR10_WD_MASK                           (3 << 17)
 123 #define CONTROL_LPDDR2IO_3_VAL          0xA0888C00
 124
 125 /* CONTROL_EFUSE_2 */
 126 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1            0x00ffc000
 127
 128 #define MMC1_PWRDNZ                                     (1 << 26)
 129 #define MMC1_PBIASLITE_PWRDNZ                           (1 << 22)
 130 #define MMC1_PBIASLITE_VMODE                            (1 << 21)
 131
 132 #ifndef __ASSEMBLY__
 133
 134 struct s32ktimer {
 135         unsigned char res[0x10];
 136         unsigned int s32k_cr;   /* 0x10 */
 137 };
 138
 139 struct omap4_sys_ctrl_regs {
 140         unsigned int pad1[129];
 141         unsigned int control_id_code;                   /* 0x4A002204 */
 142         unsigned int pad11[22];
 143         unsigned int control_std_fuse_opp_bgap;         /* 0x4a002260 */
 144         unsigned int pad2[47];
 145         unsigned int control_ldosram_iva_voltage_ctrl;  /* 0x4A002320 */
 146         unsigned int control_ldosram_mpu_voltage_ctrl;  /* 0x4A002324 */
 147         unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
 148         unsigned int pad3[260277];
 149         unsigned int control_pbiaslite;                 /* 0x4A100600 */
 150         unsigned int pad4[63];
 151         unsigned int control_efuse_1;                   /* 0x4A100700 */
 152         unsigned int control_efuse_2;                   /* 0x4A100704 */
 153 };
 154
 155 struct control_lpddr2io_regs {
 156         unsigned int control_lpddr2io1_0;
 157         unsigned int control_lpddr2io1_1;
 158         unsigned int control_lpddr2io1_2;
 159         unsigned int control_lpddr2io1_3;
 160         unsigned int control_lpddr2io2_0;
 161         unsigned int control_lpddr2io2_1;
 162         unsigned int control_lpddr2io2_2;
 163         unsigned int control_lpddr2io2_3;
 164 };
 165 #endif /* __ASSEMBLY__ */
 166
 167 /*
 168  * Non-secure SRAM Addresses
 169  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
 170  * at 0x40304000(EMU base) so that our code works for both EMU and GP
 171  */
 172 #define NON_SECURE_SRAM_START   0x40304000
 173 #define NON_SECURE_SRAM_END     0x40320000      /* Not inclusive */
 174 /* base address for indirect vectors (internal boot mode) */
 175 #define SRAM_ROM_VECT_BASE      0x4031F000
 176 /* Temporary SRAM stack used while low level init is done */
 177 #define LOW_LEVEL_SRAM_STACK    NON_SECURE_SRAM_END
 178
 179 #define SRAM_SCRATCH_SPACE_ADDR         NON_SECURE_SRAM_START
 180 /*
 181  * SRAM scratch space entries
 182  */
 183 #define OMAP5_SRAM_SCRATCH_OMAP5_REV    SRAM_SCRATCH_SPACE_ADDR
 184 #define OMAP5_SRAM_SCRATCH_EMIF_SIZE    (SRAM_SCRATCH_SPACE_ADDR + 0x4)
 185 #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM   (SRAM_SCRATCH_SPACE_ADDR + 0xC)
 186 #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN   (SRAM_SCRATCH_SPACE_ADDR + 0x10)
 187 #define OMAP5_SRAM_SCRATCH_SPACE_END    (SRAM_SCRATCH_SPACE_ADDR + 0x14)
 188
 189 /* Silicon revisions */
 190 #define OMAP4430_SILICON_ID_INVALID     0xFFFFFFFF
 191 #define OMAP4430_ES1_0  0x44300100
 192 #define OMAP4430_ES2_0  0x44300200
 193 #define OMAP4430_ES2_1  0x44300210
 194 #define OMAP4430_ES2_2  0x44300220
 195 #define OMAP4430_ES2_3  0x44300230
 196 #define OMAP4460_ES1_0  0x44600100
 197 #define OMAP4460_ES1_1  0x44600110
 198
 199 /* ROM code defines */
 200 /* Boot device */
 201 #define BOOT_DEVICE_MASK        0xFF
 202 #define BOOT_DEVICE_OFFSET      0x8
 203 #define DEV_DESC_PTR_OFFSET     0x4
 204 #define DEV_DATA_PTR_OFFSET     0x18
 205 #define BOOT_MODE_OFFSET        0x8
 206 #define RESET_REASON_OFFSET     0x9
 207 #define CH_FLAGS_OFFSET         0xA
 208
 209 #define CH_FLAGS_CHSETTINGS     (0x1 << 0)
 210 #define CH_FLAGS_CHRAM          (0x1 << 1)
 211 #define CH_FLAGS_CHFLASH        (0x1 << 2)
 212 #define CH_FLAGS_CHMMCSD        (0x1 << 3)
 213
 214 #ifndef __ASSEMBLY__
 215 struct omap_boot_parameters {
 216         char *boot_message;
 217         unsigned int mem_boot_descriptor;
 218         unsigned char omap_bootdevice;
 219         unsigned char reset_reason;
 220         unsigned char ch_flags;
 221 };
 222 #endif /* __ASSEMBLY__ */
 223 #endif