arch/arm/include/asm/arch-omap5/omap.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Authors:
   6  *      Aneesh V <aneesh@ti.com>
   7  *      Sricharan R <r.sricharan@ti.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef _OMAP5_H_
  29 #define _OMAP5_H_
  30
  31 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  32 #include <asm/types.h>
  33 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  34
  35 /*
  36  * L4 Peripherals - L4 Wakeup and L4 Core now
  37  */
  38 #define OMAP54XX_L4_CORE_BASE   0x4A000000
  39 #define OMAP54XX_L4_WKUP_BASE   0x4Ae00000
  40 #define OMAP54XX_L4_PER_BASE    0x48000000
  41
  42 #define OMAP54XX_DRAM_ADDR_SPACE_START  0x80000000
  43 #define OMAP54XX_DRAM_ADDR_SPACE_END    0xFFFFFFFF
  44 #define DRAM_ADDR_SPACE_START   OMAP54XX_DRAM_ADDR_SPACE_START
  45 #define DRAM_ADDR_SPACE_END     OMAP54XX_DRAM_ADDR_SPACE_END
  46
  47 /* CONTROL ID CODE */
  48 #define CONTROL_CORE_ID_CODE    0x4A002204
  49 #define CONTROL_WKUP_ID_CODE    0x4AE0C204
  50
  51 #ifdef CONFIG_DRA7XX
  52 #define CONTROL_ID_CODE         CONTROL_WKUP_ID_CODE
  53 #else
  54 #define CONTROL_ID_CODE         CONTROL_CORE_ID_CODE
  55 #endif
  56
  57 /* To be verified */
  58 #define OMAP5430_CONTROL_ID_CODE_ES1_0          0x0B94202F
  59 #define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
  60 #define OMAP5432_CONTROL_ID_CODE_ES1_0          0x0B99802F
  61 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
  62 #define DRA752_CONTROL_ID_CODE_ES1_0            0x0B99002F
  63
  64 /* UART */
  65 #define UART1_BASE              (OMAP54XX_L4_PER_BASE + 0x6a000)
  66 #define UART2_BASE              (OMAP54XX_L4_PER_BASE + 0x6c000)
  67 #define UART3_BASE              (OMAP54XX_L4_PER_BASE + 0x20000)
  68
  69 /* General Purpose Timers */
  70 #define GPT1_BASE               (OMAP54XX_L4_WKUP_BASE + 0x18000)
  71 #define GPT2_BASE               (OMAP54XX_L4_PER_BASE  + 0x32000)
  72 #define GPT3_BASE               (OMAP54XX_L4_PER_BASE  + 0x34000)
  73
  74 /* Watchdog Timer2 - MPU watchdog */
  75 #define WDT2_BASE               (OMAP54XX_L4_WKUP_BASE + 0x14000)
  76
  77 /* GPMC */
  78 #define OMAP54XX_GPMC_BASE      0x50000000
  79
  80 /*
  81  * Hardware Register Details
  82  */
  83
  84 /* Watchdog Timer */
  85 #define WD_UNLOCK1              0xAAAA
  86 #define WD_UNLOCK2              0x5555
  87
  88 /* GP Timer */
  89 #define TCLR_ST                 (0x1 << 0)
  90 #define TCLR_AR                 (0x1 << 1)
  91 #define TCLR_PRE                (0x1 << 5)
  92
  93 /* Control Module */
  94 #define LDOSRAM_ACTMODE_VSET_IN_MASK    (0x1F << 5)
  95 #define LDOSRAM_VOLT_CTRL_OVERRIDE      0x0401040f
  96 #define CONTROL_EFUSE_1_OVERRIDE        0x1C4D0110
  97 #define CONTROL_EFUSE_2_OVERRIDE        0x00084000
  98
  99 /* LPDDR2 IO regs */
 100 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN      0x1C1C1C1C
 101 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER    0x9E9E9E9E
 102 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN     0x7C7C7C7C
 103 #define LPDDR2IO_GR10_WD_MASK                           (3 << 17)
 104 #define CONTROL_LPDDR2IO_3_VAL          0xA0888C00
 105
 106 /* CONTROL_EFUSE_2 */
 107 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1            0x00ffc000
 108
 109 #define SDCARD_BIAS_PWRDNZ                              (1 << 27)
 110 #define SDCARD_PWRDNZ                                   (1 << 26)
 111 #define SDCARD_BIAS_HIZ_MODE                            (1 << 25)
 112 #define SDCARD_PBIASLITE_VMODE                          (1 << 21)
 113
 114 #ifndef __ASSEMBLY__
 115
 116 struct s32ktimer {
 117         unsigned char res[0x10];
 118         unsigned int s32k_cr;   /* 0x10 */
 119 };
 120
 121 #define DEVICE_TYPE_SHIFT 0x6
 122 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
 123 #define DEVICE_GP 0x3
 124
 125 /* Output impedance control */
 126 #define ds_120_ohm      0x0
 127 #define ds_60_ohm       0x1
 128 #define ds_45_ohm       0x2
 129 #define ds_30_ohm       0x3
 130 #define ds_mask         0x3
 131
 132 /* Slew rate control */
 133 #define sc_slow         0x0
 134 #define sc_medium       0x1
 135 #define sc_fast         0x2
 136 #define sc_na           0x3
 137 #define sc_mask         0x3
 138
 139 /* Target capacitance control */
 140 #define lb_5_12_pf      0x0
 141 #define lb_12_25_pf     0x1
 142 #define lb_25_50_pf     0x2
 143 #define lb_50_80_pf     0x3
 144 #define lb_mask         0x3
 145
 146 #define usb_i_mask      0x7
 147
 148 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
 149 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
 150 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
 151 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
 152 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
 153
 154 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL     0x7C7C7C6C
 155 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL        0x64646464
 156 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE                          0xBAE8C631
 157 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE                          0xBC6318DC
 158 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE                          0x0
 159
 160 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
 161 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
 162 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
 163 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
 164 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
 165
 166 #define EFUSE_1 0x45145100
 167 #define EFUSE_2 0x45145100
 168 #define EFUSE_3 0x45145100
 169 #define EFUSE_4 0x45145100
 170 #endif /* __ASSEMBLY__ */
 171
 172 #ifdef CONFIG_DRA7XX
 173 #define NON_SECURE_SRAM_START   0x40300000
 174 #define NON_SECURE_SRAM_END     0x40380000      /* Not inclusive */
 175 #else
 176 #define NON_SECURE_SRAM_START   0x40300000
 177 #define NON_SECURE_SRAM_END     0x40320000      /* Not inclusive */
 178 #endif
 179
 180 /* base address for indirect vectors (internal boot mode) */
 181 #define SRAM_ROM_VECT_BASE      0x4031F000
 182
 183 /* CONTROL_SRCOMP_XXX_SIDE */
 184 #define OVERRIDE_XS_SHIFT               30
 185 #define OVERRIDE_XS_MASK                (1 << 30)
 186 #define SRCODE_READ_XS_SHIFT            12
 187 #define SRCODE_READ_XS_MASK             (0xff << 12)
 188 #define PWRDWN_XS_SHIFT                 11
 189 #define PWRDWN_XS_MASK                  (1 << 11)
 190 #define DIVIDE_FACTOR_XS_SHIFT          4
 191 #define DIVIDE_FACTOR_XS_MASK           (0x7f << 4)
 192 #define MULTIPLY_FACTOR_XS_SHIFT        1
 193 #define MULTIPLY_FACTOR_XS_MASK         (0x7 << 1)
 194 #define SRCODE_OVERRIDE_SEL_XS_SHIFT    0
 195 #define SRCODE_OVERRIDE_SEL_XS_MASK     (1 << 0)
 196
 197 /* ABB settings */
 198 #define OMAP_ABB_SETTLING_TIME          50
 199 #define OMAP_ABB_CLOCK_CYCLES           16
 200
 201 /* ABB tranxdone mask */
 202 #define OMAP_ABB_MPU_TXDONE_MASK                (0x1 << 7)
 203
 204 /* ABB efuse masks */
 205 #define OMAP5_ABB_FUSE_VSET_MASK                (0x1F << 24)
 206 #define OMAP5_ABB_FUSE_ENABLE_MASK              (0x1 << 29)
 207 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK       (0x1 << 10)
 208 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK       (0x1f << 0)
 209
 210 #ifndef __ASSEMBLY__
 211 struct srcomp_params {
 212         s8 divide_factor;
 213         s8 multiply_factor;
 214 };
 215
 216 struct ctrl_ioregs {
 217         u32 ctrl_ddrch;
 218         u32 ctrl_lpddr2ch;
 219         u32 ctrl_ddr3ch;
 220         u32 ctrl_ddrio_0;
 221         u32 ctrl_ddrio_1;
 222         u32 ctrl_ddrio_2;
 223         u32 ctrl_emif_sdram_config_ext;
 224         u32 ctrl_ddr_ctrl_ext_0;
 225 };
 226 #endif /* __ASSEMBLY__ */
 227 #endif