arch/arm/include/asm/arch-omap5/omap.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Authors:
   6  *      Aneesh V <aneesh@ti.com>
   7  *      Sricharan R <r.sricharan@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef _OMAP5_H_
  13 #define _OMAP5_H_
  14
  15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  16 #include <asm/types.h>
  17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  18
  19 /*
  20  * L4 Peripherals - L4 Wakeup and L4 Core now
  21  */
  22 #define OMAP54XX_L4_CORE_BASE   0x4A000000
  23 #define OMAP54XX_L4_WKUP_BASE   0x4Ae00000
  24 #define OMAP54XX_L4_PER_BASE    0x48000000
  25
  26 #define OMAP54XX_DRAM_ADDR_SPACE_START  0x80000000
  27 #define OMAP54XX_DRAM_ADDR_SPACE_END    0xFFFFFFFF
  28 #define DRAM_ADDR_SPACE_START   OMAP54XX_DRAM_ADDR_SPACE_START
  29 #define DRAM_ADDR_SPACE_END     OMAP54XX_DRAM_ADDR_SPACE_END
  30
  31 /* CONTROL ID CODE */
  32 #define CONTROL_CORE_ID_CODE    0x4A002204
  33 #define CONTROL_WKUP_ID_CODE    0x4AE0C204
  34
  35 #ifdef CONFIG_DRA7XX
  36 #define CONTROL_ID_CODE         CONTROL_WKUP_ID_CODE
  37 #else
  38 #define CONTROL_ID_CODE         CONTROL_CORE_ID_CODE
  39 #endif
  40
  41 /* To be verified */
  42 #define OMAP5430_CONTROL_ID_CODE_ES1_0          0x0B94202F
  43 #define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
  44 #define OMAP5432_CONTROL_ID_CODE_ES1_0          0x0B99802F
  45 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
  46 #define DRA752_CONTROL_ID_CODE_ES1_0            0x0B99002F
  47 #define DRA752_CONTROL_ID_CODE_ES1_1            0x1B99002F
  48
  49 /* UART */
  50 #define UART1_BASE              (OMAP54XX_L4_PER_BASE + 0x6a000)
  51 #define UART2_BASE              (OMAP54XX_L4_PER_BASE + 0x6c000)
  52 #define UART3_BASE              (OMAP54XX_L4_PER_BASE + 0x20000)
  53 #define UART4_BASE              (OMAP54XX_L4_PER_BASE + 0x6e000)
  54
  55 /* General Purpose Timers */
  56 #define GPT1_BASE               (OMAP54XX_L4_WKUP_BASE + 0x18000)
  57 #define GPT2_BASE               (OMAP54XX_L4_PER_BASE  + 0x32000)
  58 #define GPT3_BASE               (OMAP54XX_L4_PER_BASE  + 0x34000)
  59
  60 /* Watchdog Timer2 - MPU watchdog */
  61 #define WDT2_BASE               (OMAP54XX_L4_WKUP_BASE + 0x14000)
  62
  63 /* GPMC */
  64 #define OMAP54XX_GPMC_BASE      0x50000000
  65
  66 /* QSPI */
  67 #define QSPI_BASE               0x4B300000
  68
  69 /* SATA */
  70 #define DWC_AHSATA_BASE         0x4A140000
  71
  72 /*
  73  * Hardware Register Details
  74  */
  75
  76 /* Watchdog Timer */
  77 #define WD_UNLOCK1              0xAAAA
  78 #define WD_UNLOCK2              0x5555
  79
  80 /* GP Timer */
  81 #define TCLR_ST                 (0x1 << 0)
  82 #define TCLR_AR                 (0x1 << 1)
  83 #define TCLR_PRE                (0x1 << 5)
  84
  85 /* Control Module */
  86 #define LDOSRAM_ACTMODE_VSET_IN_MASK    (0x1F << 5)
  87 #define LDOSRAM_VOLT_CTRL_OVERRIDE      0x0401040f
  88 #define CONTROL_EFUSE_1_OVERRIDE        0x1C4D0110
  89 #define CONTROL_EFUSE_2_OVERRIDE        0x00084000
  90
  91 /* LPDDR2 IO regs */
  92 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN      0x1C1C1C1C
  93 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER    0x9E9E9E9E
  94 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN     0x7C7C7C7C
  95 #define LPDDR2IO_GR10_WD_MASK                           (3 << 17)
  96 #define CONTROL_LPDDR2IO_3_VAL          0xA0888C00
  97
  98 /* CONTROL_EFUSE_2 */
  99 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1            0x00ffc000
 100
 101 #define SDCARD_BIAS_PWRDNZ                              (1 << 27)
 102 #define SDCARD_PWRDNZ                                   (1 << 26)
 103 #define SDCARD_BIAS_HIZ_MODE                            (1 << 25)
 104 #define SDCARD_PBIASLITE_VMODE                          (1 << 21)
 105
 106 #ifndef __ASSEMBLY__
 107
 108 struct s32ktimer {
 109         unsigned char res[0x10];
 110         unsigned int s32k_cr;   /* 0x10 */
 111 };
 112
 113 #define DEVICE_TYPE_SHIFT 0x6
 114 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
 115 #define DEVICE_GP 0x3
 116
 117 /* Output impedance control */
 118 #define ds_120_ohm      0x0
 119 #define ds_60_ohm       0x1
 120 #define ds_45_ohm       0x2
 121 #define ds_30_ohm       0x3
 122 #define ds_mask         0x3
 123
 124 /* Slew rate control */
 125 #define sc_slow         0x0
 126 #define sc_medium       0x1
 127 #define sc_fast         0x2
 128 #define sc_na           0x3
 129 #define sc_mask         0x3
 130
 131 /* Target capacitance control */
 132 #define lb_5_12_pf      0x0
 133 #define lb_12_25_pf     0x1
 134 #define lb_25_50_pf     0x2
 135 #define lb_50_80_pf     0x3
 136 #define lb_mask         0x3
 137
 138 #define usb_i_mask      0x7
 139
 140 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
 141 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
 142 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
 143 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
 144 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
 145
 146 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL     0x7C7C7C6C
 147 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL        0x64646464
 148 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE                          0xBAE8C631
 149 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE                          0xBC6318DC
 150 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE                          0x0
 151
 152 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
 153 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
 154 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
 155 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
 156 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
 157
 158 #define EFUSE_1 0x45145100
 159 #define EFUSE_2 0x45145100
 160 #define EFUSE_3 0x45145100
 161 #define EFUSE_4 0x45145100
 162 #endif /* __ASSEMBLY__ */
 163
 164 /*
 165  * In all cases, the TRM defines the RAM Memory Map for the processor
 166  * and indicates the area for the downloaded image.  We use all of that
 167  * space for download and once up and running may use other parts of the
 168  * map for our needs.  We set a scratch space that is at the end of the
 169  * OMAP5 download area, but within the DRA7xx download area (as it is
 170  * much larger) and do not, at this time, make use of the additional
 171  * space.
 172  */
 173 #ifdef CONFIG_DRA7XX
 174 #define NON_SECURE_SRAM_START   0x40300000
 175 #define NON_SECURE_SRAM_END     0x40380000      /* Not inclusive */
 176 #else
 177 #define NON_SECURE_SRAM_START   0x40300000
 178 #define NON_SECURE_SRAM_END     0x40320000      /* Not inclusive */
 179 #endif
 180 #define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
 181
 182 /* base address for indirect vectors (internal boot mode) */
 183 #define SRAM_ROM_VECT_BASE      0x4031F000
 184
 185 /* CONTROL_SRCOMP_XXX_SIDE */
 186 #define OVERRIDE_XS_SHIFT               30
 187 #define OVERRIDE_XS_MASK                (1 << 30)
 188 #define SRCODE_READ_XS_SHIFT            12
 189 #define SRCODE_READ_XS_MASK             (0xff << 12)
 190 #define PWRDWN_XS_SHIFT                 11
 191 #define PWRDWN_XS_MASK                  (1 << 11)
 192 #define DIVIDE_FACTOR_XS_SHIFT          4
 193 #define DIVIDE_FACTOR_XS_MASK           (0x7f << 4)
 194 #define MULTIPLY_FACTOR_XS_SHIFT        1
 195 #define MULTIPLY_FACTOR_XS_MASK         (0x7 << 1)
 196 #define SRCODE_OVERRIDE_SEL_XS_SHIFT    0
 197 #define SRCODE_OVERRIDE_SEL_XS_MASK     (1 << 0)
 198
 199 /* ABB settings */
 200 #define OMAP_ABB_SETTLING_TIME          50
 201 #define OMAP_ABB_CLOCK_CYCLES           16
 202
 203 /* ABB tranxdone mask */
 204 #define OMAP_ABB_MPU_TXDONE_MASK                (0x1 << 7)
 205
 206 /* ABB efuse masks */
 207 #define OMAP5_ABB_FUSE_VSET_MASK                (0x1F << 24)
 208 #define OMAP5_ABB_FUSE_ENABLE_MASK              (0x1 << 29)
 209 #define DRA7_ABB_FUSE_VSET_MASK                 (0x1F << 20)
 210 #define DRA7_ABB_FUSE_ENABLE_MASK               (0x1 << 25)
 211 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK       (0x1 << 10)
 212 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK       (0x1f << 0)
 213
 214 /* IO Delay module defines */
 215 #define CFG_IO_DELAY_BASE               0x4844A000
 216 #define CFG_IO_DELAY_LOCK               (CFG_IO_DELAY_BASE + 0x02C)
 217
 218 /* CPSW IO Delay registers*/
 219 #define CFG_RGMII0_TXCTL                (CFG_IO_DELAY_BASE + 0x74C)
 220 #define CFG_RGMII0_TXD0                 (CFG_IO_DELAY_BASE + 0x758)
 221 #define CFG_RGMII0_TXD1                 (CFG_IO_DELAY_BASE + 0x764)
 222 #define CFG_RGMII0_TXD2                 (CFG_IO_DELAY_BASE + 0x770)
 223 #define CFG_RGMII0_TXD3                 (CFG_IO_DELAY_BASE + 0x77C)
 224 #define CFG_VIN2A_D13                   (CFG_IO_DELAY_BASE + 0xA7C)
 225 #define CFG_VIN2A_D17                   (CFG_IO_DELAY_BASE + 0xAAC)
 226 #define CFG_VIN2A_D16                   (CFG_IO_DELAY_BASE + 0xAA0)
 227 #define CFG_VIN2A_D15                   (CFG_IO_DELAY_BASE + 0xA94)
 228 #define CFG_VIN2A_D14                   (CFG_IO_DELAY_BASE + 0xA88)
 229
 230 #define CFG_IO_DELAY_UNLOCK_KEY         0x0000AAAA
 231 #define CFG_IO_DELAY_LOCK_KEY           0x0000AAAB
 232 #define CFG_IO_DELAY_ACCESS_PATTERN     0x00029000
 233 #define CFG_IO_DELAY_LOCK_MASK          0x400
 234
 235 #ifndef __ASSEMBLY__
 236 struct srcomp_params {
 237         s8 divide_factor;
 238         s8 multiply_factor;
 239 };
 240
 241 struct ctrl_ioregs {
 242         u32 ctrl_ddrch;
 243         u32 ctrl_lpddr2ch;
 244         u32 ctrl_ddr3ch;
 245         u32 ctrl_ddrio_0;
 246         u32 ctrl_ddrio_1;
 247         u32 ctrl_ddrio_2;
 248         u32 ctrl_emif_sdram_config_ext;
 249         u32 ctrl_emif_sdram_config_ext_final;
 250         u32 ctrl_ddr_ctrl_ext_0;
 251 };
 252
 253 struct io_delay {
 254         u32 addr;
 255         u32 dly;
 256 };
 257 #endif /* __ASSEMBLY__ */
 258 #endif