arch/arm/include/asm/arch-pxa/macro.h

   1 /*
   2  * arch/arm/include/asm/arch-pxa/macro.h
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __ASM_ARCH_PXA_MACRO_H__
  26 #define __ASM_ARCH_PXA_MACRO_H__
  27 #ifdef __ASSEMBLY__
  28
  29 #include <asm/macro.h>
  30 #include <asm/arch/pxa-regs.h>
  31
  32 /*
  33  * This macro performs a 32bit write to a memory location and makes sure the
  34  * write operation really happened by performing a read back.
  35  *
  36  * Clobbered regs: r4, r5
  37  */
  38 .macro  write32rb addr, data
  39         ldr     r4, =\addr
  40         ldr     r5, =\data
  41         str     r5, [r4]
  42         ldr     r5, [r4]
  43 .endm
  44
  45 /*
  46  * This macro waits according to OSCR incrementation
  47  *
  48  * Clobbered regs: r4, r5, r6
  49  */
  50 .macro  pxa_wait_ticks ticks
  51         ldr     r4, =OSCR
  52         mov     r5, #0
  53         str     r5, [r4]
  54         ldr     r5, =\ticks
  55 1:
  56         ldr     r6, [r4]
  57         cmp     r5, r6
  58         bgt     1b
  59 .endm
  60
  61 /*
  62  * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
  63  *
  64  * Clobbered regs: r4, r5
  65  */
  66 .macro  pxa_gpio_setup
  67         write32 GPSR0, CONFIG_SYS_GPSR0_VAL
  68         write32 GPSR1, CONFIG_SYS_GPSR1_VAL
  69         write32 GPSR2, CONFIG_SYS_GPSR2_VAL
  70 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  71         write32 GPSR3, CONFIG_SYS_GPSR3_VAL
  72 #endif
  73
  74         write32 GPCR0, CONFIG_SYS_GPCR0_VAL
  75         write32 GPCR1, CONFIG_SYS_GPCR1_VAL
  76         write32 GPCR2, CONFIG_SYS_GPCR2_VAL
  77 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  78         write32 GPCR3, CONFIG_SYS_GPCR3_VAL
  79 #endif
  80
  81         write32 GPDR0, CONFIG_SYS_GPDR0_VAL
  82         write32 GPDR1, CONFIG_SYS_GPDR1_VAL
  83         write32 GPDR2, CONFIG_SYS_GPDR2_VAL
  84 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  85         write32 GPDR3, CONFIG_SYS_GPDR3_VAL
  86 #endif
  87
  88         write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
  89         write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
  90         write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
  91         write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
  92         write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
  93         write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
  94 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  95         write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
  96         write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
  97 #endif
  98
  99         write32 PSSR, CONFIG_SYS_PSSR_VAL
 100 .endm
 101
 102 /*
 103  * This macro sets up the Memory controller of the PXA2xx CPU
 104  *
 105  * Clobbered regs: r3, r4, r5
 106  */
 107 .macro  pxa_mem_setup
 108         /* This comes handy when setting MDREFR */
 109         ldr     r3, =MEMC_BASE
 110
 111         /*
 112          * 1) Initialize Asynchronous static memory controller
 113          */
 114
 115         /* MSC0: nCS(0,1) */
 116         write32rb       (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
 117         /* MSC1: nCS(2,3) */
 118         write32rb       (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
 119         /* MSC2: nCS(4,5) */
 120         write32rb       (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
 121
 122         /*
 123          * 2) Initialize Card Interface
 124          */
 125
 126         /* MECR: Memory Expansion Card Register */
 127         write32rb       (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
 128         /* MCMEM0: Card Interface slot 0 timing */
 129         write32rb       (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
 130         /* MCMEM1: Card Interface slot 1 timing */
 131         write32rb       (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
 132         /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
 133         write32rb       (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
 134         /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
 135         write32rb       (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
 136         /* MCIO0: Card Interface I/O Space Timing, slot 0 */
 137         write32rb       (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
 138         /* MCIO1: Card Interface I/O Space Timing, slot 1 */
 139         write32rb       (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
 140
 141         /*
 142          * 3) Configure Fly-By DMA register
 143          */
 144
 145         write32rb       (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
 146
 147         /*
 148          * 4) Initialize Timing for Sync Memory (SDCLK0)
 149          */
 150
 151         /*
 152          * Before accessing MDREFR we need a valid DRI field, so we set
 153          * this to power on defaults + DRI field.
 154          */
 155         ldr     r5, [r3, #MDREFR_OFFSET]
 156         bic     r5, r5, #0x0ff
 157         bic     r5, r5, #0xf00  /* MDREFR user config with zeroed DRI */
 158
 159         ldr     r4, =CONFIG_SYS_MDREFR_VAL
 160         mov     r6, r4
 161         lsl     r4, #20
 162         lsr     r4, #20         /* Get a valid DRI field */
 163
 164         orr     r5, r5, r4      /* MDREFR user config with correct DRI */
 165
 166         orr     r5, #MDREFR_K0RUN
 167         orr     r5, #MDREFR_SLFRSH
 168         bic     r5, #MDREFR_APD
 169         bic     r5, #MDREFR_E1PIN
 170
 171         str     r5, [r3, #MDREFR_OFFSET]
 172         ldr     r4, [r3, #MDREFR_OFFSET]
 173
 174         /*
 175          * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
 176          */
 177
 178         /* Initialize SXCNFG register. Assert the enable bits.
 179          *
 180          * Write SXMRS to cause an MRS command to all enabled banks of
 181          * synchronous static memory. Note that SXLCR need not be written
 182          * at this time.
 183          */
 184         write32rb       (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
 185
 186         /*
 187          * 6) Initialize SDRAM
 188          */
 189
 190         bic     r6, #MDREFR_SLFRSH
 191         str     r6, [r3, #MDREFR_OFFSET]
 192         ldr     r4, [r3, #MDREFR_OFFSET]
 193
 194         orr     r6, #MDREFR_E1PIN
 195         str     r6, [r3, #MDREFR_OFFSET]
 196         ldr     r4, [r3, #MDREFR_OFFSET]
 197
 198         /*
 199          * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
 200          *    but not enable each SDRAM partition pair.
 201          */
 202
 203         /* Fetch platform value of MDCNFG */
 204         ldr     r4, =CONFIG_SYS_MDCNFG_VAL
 205         /* Disable all sdram banks */
 206         bic     r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
 207         bic     r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
 208         /* Write initial value of MDCNFG, w/o enabling sdram banks */
 209         str     r4, [r3, #MDCNFG_OFFSET]
 210         ldr     r4, [r3, #MDCNFG_OFFSET]
 211
 212         /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
 213         pxa_wait_ticks  0x300
 214
 215         /*
 216          * 8) Trigger a number (usually 8) refresh cycles by attempting
 217          *    non-burst read or write accesses to disabled SDRAM, as commonly
 218          *    specified in the power up sequence documented in SDRAM data
 219          *    sheets. The address(es) used for this purpose must not be
 220          *    cacheable.
 221          */
 222
 223         ldr     r4, =CONFIG_SYS_DRAM_BASE
 224 .rept 9
 225         str     r5, [r4]
 226 .endr
 227
 228         /*
 229          * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
 230          */
 231
 232         ldr     r5, =CONFIG_SYS_MDCNFG_VAL
 233         ldr     r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
 234         and     r5, r5, r4
 235         ldr     r4, [r3, #MDCNFG_OFFSET]
 236         orr     r4, r4, r5
 237         str     r4, [r3, #MDCNFG_OFFSET]
 238         ldr     r4, [r3, #MDCNFG_OFFSET]
 239
 240         /*
 241          * 10) Write MDMRS.
 242          */
 243
 244         ldr     r4, =CONFIG_SYS_MDMRS_VAL
 245         str     r4, [r3, #MDMRS_OFFSET]
 246         ldr     r4, [r3, #MDMRS_OFFSET]
 247
 248         /*
 249          * 11) Enable APD
 250          */
 251
 252         ldr     r4, [r3, #MDREFR_OFFSET]
 253         and     r6, r6, #MDREFR_APD
 254         orr     r4, r4, r6
 255         str     r4, [r3, #MDREFR_OFFSET]
 256         ldr     r4, [r3, #MDREFR_OFFSET]
 257 .endm
 258
 259 /*
 260  * This macro tests if the CPU woke up from sleep and eventually resumes
 261  *
 262  * Clobbered regs: r4, r5
 263  */
 264 .macro  pxa_wakeup
 265         ldr     r4, =RCSR
 266         ldr     r5, [r4]
 267         and     r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
 268         str     r5, [r4]
 269         teq     r5, #RCSR_SMR
 270
 271         bne     pxa_wakeup_exit
 272
 273         ldr     r4, =PSSR
 274         mov     r5, #PSSR_PH
 275         str     r5, [r4]
 276
 277         ldr     r4, =PSPR
 278         ldr     pc, [r4]
 279 pxa_wakeup_exit:
 280 .endm
 281
 282 /*
 283  * This macro disables all interupts on PXA2xx/PXA3xx CPU
 284  *
 285  * Clobbered regs: r4, r5
 286  */
 287 .macro  pxa_intr_setup
 288         write32 ICLR, 0
 289         write32 ICMR, 0
 290 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 291         write32 ICLR2, 0
 292         write32 ICMR2, 0
 293 #endif
 294 .endm
 295
 296 /*
 297  * This macro configures clock on PXA2xx/PXA3xx CPU
 298  *
 299  * Clobbered regs: r4, r5
 300  */
 301 .macro  pxa_clock_setup
 302         /* Disable the peripheral clocks, and set the core clock frequency */
 303
 304         /* Turn Off ALL on-chip peripheral clocks for re-configuration */
 305         write32 CKEN, CONFIG_SYS_CKEN
 306
 307         /* Write CCCR */
 308         write32 CCCR, CONFIG_SYS_CCCR
 309
 310 #ifdef CONFIG_RTC
 311         /* enable the 32Khz oscillator for RTC and PowerManager */
 312         write32 OSCC, #OSCC_OON
 313         ldr     r4, =OSCC
 314
 315         /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
 316 2:
 317         ldr     r5, [r4]
 318         ands    r5, r5, #1
 319         beq     2b
 320 #endif
 321 .endm
 322
 323 #endif /* __ASSEMBLY__ */
 324 #endif /* __ASM_ARCH_PXA_MACRO_H__ */