arch/arm/include/asm/arch-rockchip/clock.h

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef _ASM_ARCH_CLOCK_H
   8 #define _ASM_ARCH_CLOCK_H
   9
  10 /* define pll mode */
  11 #define RKCLK_PLL_MODE_SLOW             0
  12 #define RKCLK_PLL_MODE_NORMAL           1
  13
  14 enum {
  15         ROCKCHIP_SYSCON_NOC,
  16         ROCKCHIP_SYSCON_GRF,
  17         ROCKCHIP_SYSCON_SGRF,
  18         ROCKCHIP_SYSCON_PMU,
  19         ROCKCHIP_SYSCON_PMUGRF,
  20 };
  21
  22 /* Standard Rockchip clock numbers */
  23 enum rk_clk_id {
  24         CLK_OSC,
  25         CLK_ARM,
  26         CLK_DDR,
  27         CLK_CODEC,
  28         CLK_GENERAL,
  29         CLK_NEW,
  30
  31         CLK_COUNT,
  32 };
  33
  34 static inline int rk_pll_id(enum rk_clk_id clk_id)
  35 {
  36         return clk_id - 1;
  37 }
  38
  39 /**
  40  * clk_get_divisor() - Calculate the required clock divisior
  41  *
  42  * Given an input rate and a required output_rate, calculate the Rockchip
  43  * divisor needed to achieve this.
  44  *
  45  * @input_rate:         Input clock rate in Hz
  46  * @output_rate:        Output clock rate in Hz
  47  * @return divisor register value to use
  48  */
  49 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  50 {
  51         uint clk_div;
  52
  53         clk_div = input_rate / output_rate;
  54         clk_div = (clk_div + 1) & 0xfffe;
  55
  56         return clk_div;
  57 }
  58
  59 /**
  60  * rockchip_get_cru() - get a pointer to the clock/reset unit registers
  61  *
  62  * @return pointer to registers, or -ve error on error
  63  */
  64 void *rockchip_get_cru(void);
  65
  66 struct rk3288_cru;
  67 struct rk3288_grf;
  68
  69 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
  70
  71 int rockchip_get_clk(struct udevice **devp);
  72
  73 #endif