arch/arm/include/asm/arch-rockchip/cru_rk3288.h

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * (C) Copyright 2008-2014 Rockchip Electronics
   5  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #ifndef _ASM_ARCH_CRU_RK3288_H
  10 #define _ASM_ARCH_CRU_RK3288_H
  11
  12 #define OSC_HZ          (24 * 1000 * 1000)
  13
  14 #define APLL_HZ         (1800 * 1000000)
  15 #define GPLL_HZ         (594 * 1000000)
  16 #define CPLL_HZ         (384 * 1000000)
  17 #define NPLL_HZ         (384 * 1000000)
  18
  19 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
  20 #define PD_BUS_ACLK_HZ  297000000
  21 #define PD_BUS_HCLK_HZ  148500000
  22 #define PD_BUS_PCLK_HZ  74250000
  23
  24 #define PERI_ACLK_HZ    148500000
  25 #define PERI_HCLK_HZ    148500000
  26 #define PERI_PCLK_HZ    74250000
  27
  28 struct rk3288_cru {
  29         struct rk3288_pll {
  30                 u32 con0;
  31                 u32 con1;
  32                 u32 con2;
  33                 u32 con3;
  34         } pll[5];
  35         u32 cru_mode_con;
  36         u32 reserved0[3];
  37         u32 cru_clksel_con[43];
  38         u32 reserved1[21];
  39         u32 cru_clkgate_con[19];
  40         u32 reserved2;
  41         u32 cru_glb_srst_fst_value;
  42         u32 cru_glb_srst_snd_value;
  43         u32 cru_softrst_con[12];
  44         u32 cru_misc_con;
  45         u32 cru_glb_cnt_th;
  46         u32 cru_glb_rst_con;
  47         u32 reserved3;
  48         u32 cru_glb_rst_st;
  49         u32 reserved4;
  50         u32 cru_sdmmc_con[2];
  51         u32 cru_sdio0_con[2];
  52         u32 cru_sdio1_con[2];
  53         u32 cru_emmc_con[2];
  54 };
  55 check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
  56
  57 /* CRU_CLKSEL11_CON */
  58 enum {
  59         HSICPHY_DIV_SHIFT       = 8,
  60         HSICPHY_DIV_MASK        = 0x3f,
  61
  62         MMC0_PLL_SHIFT          = 6,
  63         MMC0_PLL_MASK           = 3,
  64         MMC0_PLL_SELECT_CODEC   = 0,
  65         MMC0_PLL_SELECT_GENERAL,
  66         MMC0_PLL_SELECT_24MHZ,
  67
  68         MMC0_DIV_SHIFT          = 0,
  69         MMC0_DIV_MASK           = 0x3f,
  70 };
  71
  72 /* CRU_CLKSEL12_CON */
  73 enum {
  74         EMMC_PLL_SHIFT          = 0xe,
  75         EMMC_PLL_MASK           = 3,
  76         EMMC_PLL_SELECT_CODEC   = 0,
  77         EMMC_PLL_SELECT_GENERAL,
  78         EMMC_PLL_SELECT_24MHZ,
  79
  80         EMMC_DIV_SHIFT          = 8,
  81         EMMC_DIV_MASK           = 0x3f,
  82
  83         SDIO0_PLL_SHIFT         = 6,
  84         SDIO0_PLL_MASK          = 3,
  85         SDIO0_PLL_SELECT_CODEC  = 0,
  86         SDIO0_PLL_SELECT_GENERAL,
  87         SDIO0_PLL_SELECT_24MHZ,
  88
  89         SDIO0_DIV_SHIFT         = 0,
  90         SDIO0_DIV_MASK          = 0x3f,
  91 };
  92
  93 /* CRU_CLKSEL25_CON */
  94 enum {
  95         SPI1_PLL_SHIFT          = 0xf,
  96         SPI1_PLL_MASK           = 1,
  97         SPI1_PLL_SELECT_CODEC   = 0,
  98         SPI1_PLL_SELECT_GENERAL,
  99
 100         SPI1_DIV_SHIFT          = 8,
 101         SPI1_DIV_MASK           = 0x7f,
 102
 103         SPI0_PLL_SHIFT          = 7,
 104         SPI0_PLL_MASK           = 1,
 105         SPI0_PLL_SELECT_CODEC   = 0,
 106         SPI0_PLL_SELECT_GENERAL,
 107
 108         SPI0_DIV_SHIFT          = 0,
 109         SPI0_DIV_MASK           = 0x7f,
 110 };
 111
 112 /* CRU_CLKSEL39_CON */
 113 enum {
 114         ACLK_HEVC_PLL_SHIFT     = 0xe,
 115         ACLK_HEVC_PLL_MASK      = 3,
 116         ACLK_HEVC_PLL_SELECT_CODEC = 0,
 117         ACLK_HEVC_PLL_SELECT_GENERAL,
 118         ACLK_HEVC_PLL_SELECT_NEW,
 119
 120         ACLK_HEVC_DIV_SHIFT     = 8,
 121         ACLK_HEVC_DIV_MASK      = 0x1f,
 122
 123         SPI2_PLL_SHIFT          = 7,
 124         SPI2_PLL_MASK           = 1,
 125         SPI2_PLL_SELECT_CODEC   = 0,
 126         SPI2_PLL_SELECT_GENERAL,
 127
 128         SPI2_DIV_SHIFT          = 0,
 129         SPI2_DIV_MASK           = 0x7f,
 130 };
 131
 132 /* CRU_MODE_CON */
 133 enum {
 134         NPLL_WORK_SHIFT         = 0xe,
 135         NPLL_WORK_MASK          = 3,
 136         NPLL_WORK_SLOW          = 0,
 137         NPLL_WORK_NORMAL,
 138         NPLL_WORK_DEEP,
 139
 140         GPLL_WORK_SHIFT         = 0xc,
 141         GPLL_WORK_MASK          = 3,
 142         GPLL_WORK_SLOW          = 0,
 143         GPLL_WORK_NORMAL,
 144         GPLL_WORK_DEEP,
 145
 146         CPLL_WORK_SHIFT         = 8,
 147         CPLL_WORK_MASK          = 3,
 148         CPLL_WORK_SLOW          = 0,
 149         CPLL_WORK_NORMAL,
 150         CPLL_WORK_DEEP,
 151
 152         DPLL_WORK_SHIFT         = 4,
 153         DPLL_WORK_MASK          = 3,
 154         DPLL_WORK_SLOW          = 0,
 155         DPLL_WORK_NORMAL,
 156         DPLL_WORK_DEEP,
 157
 158         APLL_WORK_SHIFT         = 0,
 159         APLL_WORK_MASK          = 3,
 160         APLL_WORK_SLOW          = 0,
 161         APLL_WORK_NORMAL,
 162         APLL_WORK_DEEP,
 163 };
 164
 165 /* CRU_APLL_CON0 */
 166 enum {
 167         CLKR_SHIFT              = 8,
 168         CLKR_MASK               = 0x3f,
 169
 170         CLKOD_SHIFT             = 0,
 171         CLKOD_MASK              = 0xf,
 172 };
 173
 174 /* CRU_APLL_CON1 */
 175 enum {
 176         LOCK_SHIFT              = 0x1f,
 177         LOCK_MASK               = 1,
 178         LOCK_UNLOCK             = 0,
 179         LOCK_LOCK,
 180
 181         CLKF_SHIFT              = 0,
 182         CLKF_MASK               = 0x1fff,
 183 };
 184
 185 #endif