arch/arm/include/asm/arch-tegra/ap.h

   1 /*
   2  * (C) Copyright 2010-2011
   3  * NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <asm/types.h>
  24
  25 /* Stabilization delays, in usec */
  26 #define PLL_STABILIZATION_DELAY (300)
  27 #define IO_STABILIZATION_DELAY  (1000)
  28
  29 #define PLLX_ENABLED            (1 << 30)
  30 #define CCLK_BURST_POLICY       0x20008888
  31 #define SUPER_CCLK_DIVIDER      0x80000000
  32
  33 /* Calculate clock fractional divider value from ref and target frequencies */
  34 #define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
  35
  36 /* Calculate clock frequency value from reference and clock divider value */
  37 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
  38
  39 /* AVP/CPU ID */
  40 #define PG_UP_TAG_0_PID_CPU     0x55555555      /* CPU aka "a9" aka "mpcore" */
  41 #define PG_UP_TAG_0             0x0
  42
  43 #define CORESIGHT_UNLOCK        0xC5ACCE55;
  44
  45 /* AP base physical address of internal SRAM */
  46 #define NV_PA_BASE_SRAM         0x40000000
  47
  48 #define EXCEP_VECTOR_CPU_RESET_VECTOR   (NV_PA_EVP_BASE + 0x100)
  49 #define CSITE_CPU_DBG0_LAR              (NV_PA_CSITE_BASE + 0x10FB0)
  50 #define CSITE_CPU_DBG1_LAR              (NV_PA_CSITE_BASE + 0x12FB0)
  51
  52 #define FLOW_CTLR_HALT_COP_EVENTS       (NV_PA_FLOW_BASE + 4)
  53 #define FLOW_MODE_STOP                  2
  54 #define HALT_COP_EVENT_JTAG             (1 << 28)
  55 #define HALT_COP_EVENT_IRQ_1            (1 << 11)
  56 #define HALT_COP_EVENT_FIQ_1            (1 << 9)
  57
  58 /* This is the main entry into U-Boot, used by the Cortex-A9 */
  59 extern void _start(void);
  60
  61 /**
  62  * Works out the SOC type used for clocks settings
  63  *
  64  * @return      SOC type - see TEGRA_SOC...
  65  */
  66 int tegra_get_chip_type(void);