arch/arm/include/asm/arch-tegra/tegra_i2c.h

   1 /*
   2  * NVIDIA Tegra I2C controller
   3  *
   4  * Copyright 2010-2011 NVIDIA Corporation
   5  *
   6  * This software may be used and distributed according to the
   7  * terms of the GNU Public License, Version 2, incorporated
   8  * herein by reference.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * Version 2 as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _TEGRA_I2C_H_
  26 #define _TEGRA_I2C_H_
  27
  28 #include <asm/types.h>
  29
  30 enum {
  31         I2C_TIMEOUT_USEC = 10000,       /* Wait time for completion */
  32         I2C_FIFO_DEPTH = 8,             /* I2C fifo depth */
  33 };
  34
  35 enum i2c_transaction_flags {
  36         I2C_IS_WRITE = 0x1,             /* for I2C write operation */
  37         I2C_IS_10_BIT_ADDRESS = 0x2,    /* for 10-bit I2C slave address */
  38         I2C_USE_REPEATED_START = 0x4,   /* for repeat start */
  39         I2C_NO_ACK = 0x8,               /* for slave that won't generate ACK */
  40         I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
  41         I2C_NO_STOP = 0x20,
  42 };
  43
  44 /* Contians the I2C transaction details */
  45 struct i2c_trans_info {
  46         /* flags to indicate the transaction details */
  47         enum i2c_transaction_flags flags;
  48         u32 address;    /* I2C slave device address */
  49         u32 num_bytes;  /* number of bytes to be transferred */
  50         /*
  51          * Send/receive buffer. For the I2C send operation this buffer should
  52          * be filled with the data to be sent to the slave device. For the I2C
  53          * receive operation this buffer is filled with the data received from
  54          * the slave device.
  55          */
  56         u8 *buf;
  57         int is_10bit_address;
  58 };
  59
  60 struct i2c_control {
  61         u32 tx_fifo;
  62         u32 rx_fifo;
  63         u32 packet_status;
  64         u32 fifo_control;
  65         u32 fifo_status;
  66         u32 int_mask;
  67         u32 int_status;
  68 };
  69
  70 struct dvc_ctlr {
  71         u32 ctrl1;                      /* 00: DVC_CTRL_REG1 */
  72         u32 ctrl2;                      /* 04: DVC_CTRL_REG2 */
  73         u32 ctrl3;                      /* 08: DVC_CTRL_REG3 */
  74         u32 status;                     /* 0C: DVC_STATUS_REG */
  75         u32 ctrl;                       /* 10: DVC_I2C_CTRL_REG */
  76         u32 addr_data;                  /* 14: DVC_I2C_ADDR_DATA_REG */
  77         u32 reserved_0[2];              /* 18: */
  78         u32 req;                        /* 20: DVC_REQ_REGISTER */
  79         u32 addr_data3;                 /* 24: DVC_I2C_ADDR_DATA_REG_3 */
  80         u32 reserved_1[6];              /* 28: */
  81         u32 cnfg;                       /* 40: DVC_I2C_CNFG */
  82         u32 cmd_addr0;                  /* 44: DVC_I2C_CMD_ADDR0 */
  83         u32 cmd_addr1;                  /* 48: DVC_I2C_CMD_ADDR1 */
  84         u32 cmd_data1;                  /* 4C: DVC_I2C_CMD_DATA1 */
  85         u32 cmd_data2;                  /* 50: DVC_I2C_CMD_DATA2 */
  86         u32 reserved_2[2];              /* 54: */
  87         u32 i2c_status;                 /* 5C: DVC_I2C_STATUS */
  88         struct i2c_control control;     /* 60 ~ 78 */
  89 };
  90
  91 struct i2c_ctlr {
  92         u32 cnfg;                       /* 00: I2C_I2C_CNFG */
  93         u32 cmd_addr0;                  /* 04: I2C_I2C_CMD_ADDR0 */
  94         u32 cmd_addr1;                  /* 08: I2C_I2C_CMD_DATA1 */
  95         u32 cmd_data1;                  /* 0C: I2C_I2C_CMD_DATA2 */
  96         u32 cmd_data2;                  /* 10: DVC_I2C_CMD_DATA2 */
  97         u32 reserved_0[2];              /* 14: */
  98         u32 status;                     /* 1C: I2C_I2C_STATUS */
  99         u32 sl_cnfg;                    /* 20: I2C_I2C_SL_CNFG */
 100         u32 sl_rcvd;                    /* 24: I2C_I2C_SL_RCVD */
 101         u32 sl_status;                  /* 28: I2C_I2C_SL_STATUS */
 102         u32 sl_addr1;                   /* 2C: I2C_I2C_SL_ADDR1 */
 103         u32 sl_addr2;                   /* 30: I2C_I2C_SL_ADDR2 */
 104         u32 reserved_1[2];              /* 34: */
 105         u32 sl_delay_count;             /* 3C: I2C_I2C_SL_DELAY_COUNT */
 106         u32 reserved_2[4];              /* 40: */
 107         struct i2c_control control;     /* 50 ~ 68 */
 108         u32 clk_div;                    /* 6C: I2C_I2C_CLOCK_DIVISOR */
 109 };
 110
 111 /* bit fields definitions for IO Packet Header 1 format */
 112 #define PKT_HDR1_PROTOCOL_SHIFT         4
 113 #define PKT_HDR1_PROTOCOL_MASK          (0xf << PKT_HDR1_PROTOCOL_SHIFT)
 114 #define PKT_HDR1_CTLR_ID_SHIFT          12
 115 #define PKT_HDR1_CTLR_ID_MASK           (0xf << PKT_HDR1_CTLR_ID_SHIFT)
 116 #define PKT_HDR1_PKT_ID_SHIFT           16
 117 #define PKT_HDR1_PKT_ID_MASK            (0xff << PKT_HDR1_PKT_ID_SHIFT)
 118 #define PROTOCOL_TYPE_I2C               1
 119
 120 /* bit fields definitions for IO Packet Header 2 format */
 121 #define PKT_HDR2_PAYLOAD_SIZE_SHIFT     0
 122 #define PKT_HDR2_PAYLOAD_SIZE_MASK      (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
 123
 124 /* bit fields definitions for IO Packet Header 3 format */
 125 #define PKT_HDR3_READ_MODE_SHIFT        19
 126 #define PKT_HDR3_READ_MODE_MASK         (1 << PKT_HDR3_READ_MODE_SHIFT)
 127 #define PKT_HDR3_REPEAT_START_SHIFT     16
 128 #define PKT_HDR3_REPEAT_START_MASK      (1 << PKT_HDR3_REPEAT_START_SHIFT)
 129 #define PKT_HDR3_SLAVE_ADDR_SHIFT       0
 130 #define PKT_HDR3_SLAVE_ADDR_MASK        (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
 131
 132 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT      26
 133 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK       \
 134                                 (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
 135
 136 /* I2C_CNFG */
 137 #define I2C_CNFG_NEW_MASTER_FSM_SHIFT   11
 138 #define I2C_CNFG_NEW_MASTER_FSM_MASK    (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
 139 #define I2C_CNFG_PACKET_MODE_SHIFT      10
 140 #define I2C_CNFG_PACKET_MODE_MASK       (1 << I2C_CNFG_PACKET_MODE_SHIFT)
 141
 142 /* I2C_SL_CNFG */
 143 #define I2C_SL_CNFG_NEWSL_SHIFT         2
 144 #define I2C_SL_CNFG_NEWSL_MASK          (1 << I2C_SL_CNFG_NEWSL_SHIFT)
 145
 146 /* I2C_FIFO_STATUS */
 147 #define TX_FIFO_FULL_CNT_SHIFT          0
 148 #define TX_FIFO_FULL_CNT_MASK           (0xf << TX_FIFO_FULL_CNT_SHIFT)
 149 #define TX_FIFO_EMPTY_CNT_SHIFT         4
 150 #define TX_FIFO_EMPTY_CNT_MASK          (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
 151
 152 /* I2C_INTERRUPT_STATUS */
 153 #define I2C_INT_XFER_COMPLETE_SHIFT     7
 154 #define I2C_INT_XFER_COMPLETE_MASK      (1 << I2C_INT_XFER_COMPLETE_SHIFT)
 155 #define I2C_INT_NO_ACK_SHIFT            3
 156 #define I2C_INT_NO_ACK_MASK             (1 << I2C_INT_NO_ACK_SHIFT)
 157 #define I2C_INT_ARBITRATION_LOST_SHIFT  2
 158 #define I2C_INT_ARBITRATION_LOST_MASK   (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
 159
 160 /* I2C_CLK_DIVISOR_REGISTER */
 161 #define CLK_DIV_STD_FAST_MODE           0x19
 162 #define CLK_DIV_HS_MODE                 1
 163 #define CLK_MULT_STD_FAST_MODE          8
 164
 165 /**
 166  * Returns the bus number of the DVC controller
 167  *
 168  * @return number of bus, or -1 if there is no DVC active
 169  */
 170 int tegra_i2c_get_dvc_bus_num(void);
 171
 172 #endif  /* _TEGRA_I2C_H_ */