arch/arm/include/asm/arch-tegra114/clock-tables.h

   1 /*
   2  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 /* Tegra114 clock PLL tables */
  18
  19 #ifndef _TEGRA114_CLOCK_TABLES_H_
  20 #define _TEGRA114_CLOCK_TABLES_H_
  21
  22 /* The PLLs supported by the hardware */
  23 enum clock_id {
  24         CLOCK_ID_FIRST,
  25         CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
  26         CLOCK_ID_MEMORY,
  27         CLOCK_ID_PERIPH,
  28         CLOCK_ID_AUDIO,
  29         CLOCK_ID_USB,
  30         CLOCK_ID_DISPLAY,
  31
  32         /* now the simple ones */
  33         CLOCK_ID_FIRST_SIMPLE,
  34         CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
  35         CLOCK_ID_EPCI,
  36         CLOCK_ID_SFROM32KHZ,
  37
  38         /* These are the base clocks (inputs to the Tegra SOC) */
  39         CLOCK_ID_32KHZ,
  40         CLOCK_ID_OSC,
  41         CLOCK_ID_CLK_M,
  42
  43         CLOCK_ID_COUNT, /* number of PLLs */
  44         CLOCK_ID_DISPLAY2,      /* placeholder */
  45         CLOCK_ID_NONE = -1,
  46 };
  47
  48 /* The clocks supported by the hardware */
  49 enum periph_id {
  50         PERIPH_ID_FIRST,
  51
  52         /* Low word: 31:0 (DEVICES_L) */
  53         PERIPH_ID_CPU = PERIPH_ID_FIRST,
  54         PERIPH_ID_COP,
  55         PERIPH_ID_TRIGSYS,
  56         PERIPH_ID_RESERVED3,
  57         PERIPH_ID_RTC,
  58         PERIPH_ID_TMR,
  59         PERIPH_ID_UART1,
  60         PERIPH_ID_UART2,
  61
  62         /* 8 */
  63         PERIPH_ID_GPIO,
  64         PERIPH_ID_SDMMC2,
  65         PERIPH_ID_SPDIF,
  66         PERIPH_ID_I2S1,
  67         PERIPH_ID_I2C1,
  68         PERIPH_ID_NDFLASH,
  69         PERIPH_ID_SDMMC1,
  70         PERIPH_ID_SDMMC4,
  71
  72         /* 16 */
  73         PERIPH_ID_RESERVED16,
  74         PERIPH_ID_PWM,
  75         PERIPH_ID_I2S2,
  76         PERIPH_ID_EPP,
  77         PERIPH_ID_VI,
  78         PERIPH_ID_2D,
  79         PERIPH_ID_USBD,
  80         PERIPH_ID_ISP,
  81
  82         /* 24 */
  83         PERIPH_ID_3D,
  84         PERIPH_ID_RESERVED24,
  85         PERIPH_ID_DISP2,
  86         PERIPH_ID_DISP1,
  87         PERIPH_ID_HOST1X,
  88         PERIPH_ID_VCP,
  89         PERIPH_ID_I2S0,
  90         PERIPH_ID_CACHE2,
  91
  92         /* Middle word: 63:32 (DEVICES_H) */
  93         PERIPH_ID_MEM,
  94         PERIPH_ID_AHBDMA,
  95         PERIPH_ID_APBDMA,
  96         PERIPH_ID_RESERVED35,
  97         PERIPH_ID_KBC,
  98         PERIPH_ID_STAT_MON,
  99         PERIPH_ID_PMC,
 100         PERIPH_ID_FUSE,
 101
 102         /* 40 */
 103         PERIPH_ID_KFUSE,
 104         PERIPH_ID_SBC1,
 105         PERIPH_ID_SNOR,
 106         PERIPH_ID_RESERVED43,
 107         PERIPH_ID_SBC2,
 108         PERIPH_ID_RESERVED45,
 109         PERIPH_ID_SBC3,
 110         PERIPH_ID_I2C5,
 111
 112         /* 48 */
 113         PERIPH_ID_DSI,
 114         PERIPH_ID_TVO,
 115         PERIPH_ID_MIPI,
 116         PERIPH_ID_HDMI,
 117         PERIPH_ID_CSI,
 118         PERIPH_ID_TVDAC,
 119         PERIPH_ID_I2C2,
 120         PERIPH_ID_UART3,
 121
 122         /* 56 */
 123         PERIPH_ID_RESERVED56,
 124         PERIPH_ID_EMC,
 125         PERIPH_ID_USB2,
 126         PERIPH_ID_USB3,
 127         PERIPH_ID_MPE,
 128         PERIPH_ID_VDE,
 129         PERIPH_ID_BSEA,
 130         PERIPH_ID_BSEV,
 131
 132         /* Upper word 95:64 (DEVICES_U) */
 133         PERIPH_ID_SPEEDO,
 134         PERIPH_ID_UART4,
 135         PERIPH_ID_UART5,
 136         PERIPH_ID_I2C3,
 137         PERIPH_ID_SBC4,
 138         PERIPH_ID_SDMMC3,
 139         PERIPH_ID_PCIE,
 140         PERIPH_ID_OWR,
 141
 142         /* 72 */
 143         PERIPH_ID_AFI,
 144         PERIPH_ID_CORESIGHT,
 145         PERIPH_ID_PCIEXCLK,
 146         PERIPH_ID_AVPUCQ,
 147         PERIPH_ID_RESERVED76,
 148         PERIPH_ID_RESERVED77,
 149         PERIPH_ID_RESERVED78,
 150         PERIPH_ID_DTV,
 151
 152         /* 80 */
 153         PERIPH_ID_NANDSPEED,
 154         PERIPH_ID_I2CSLOW,
 155         PERIPH_ID_DSIB,
 156         PERIPH_ID_RESERVED83,
 157         PERIPH_ID_IRAMA,
 158         PERIPH_ID_IRAMB,
 159         PERIPH_ID_IRAMC,
 160         PERIPH_ID_IRAMD,
 161
 162         /* 88 */
 163         PERIPH_ID_CRAM2,
 164         PERIPH_ID_RESERVED89,
 165         PERIPH_ID_MDOUBLER,
 166         PERIPH_ID_RESERVED91,
 167         PERIPH_ID_SUSOUT,
 168         PERIPH_ID_RESERVED93,
 169         PERIPH_ID_RESERVED94,
 170         PERIPH_ID_RESERVED95,
 171
 172         PERIPH_ID_VW_FIRST,
 173         /* V word: 31:0 */
 174         PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
 175         PERIPH_ID_CPULP,
 176         PERIPH_ID_3D2,
 177         PERIPH_ID_MSELECT,
 178         PERIPH_ID_TSENSOR,
 179         PERIPH_ID_I2S3,
 180         PERIPH_ID_I2S4,
 181         PERIPH_ID_I2C4,
 182
 183         /* 104 */
 184         PERIPH_ID_SBC5,
 185         PERIPH_ID_SBC6,
 186         PERIPH_ID_AUDIO,
 187         PERIPH_ID_APBIF,
 188         PERIPH_ID_DAM0,
 189         PERIPH_ID_DAM1,
 190         PERIPH_ID_DAM2,
 191         PERIPH_ID_HDA2CODEC2X,
 192
 193         /* 112 */
 194         PERIPH_ID_ATOMICS,
 195         PERIPH_ID_EX_RESERVED17,
 196         PERIPH_ID_EX_RESERVED18,
 197         PERIPH_ID_EX_RESERVED19,
 198         PERIPH_ID_EX_RESERVED20,
 199         PERIPH_ID_EX_RESERVED21,
 200         PERIPH_ID_EX_RESERVED22,
 201         PERIPH_ID_ACTMON,
 202
 203         /* 120 */
 204         PERIPH_ID_EX_RESERVED24,
 205         PERIPH_ID_EX_RESERVED25,
 206         PERIPH_ID_EX_RESERVED26,
 207         PERIPH_ID_EX_RESERVED27,
 208         PERIPH_ID_SATA,
 209         PERIPH_ID_HDA,
 210         PERIPH_ID_EX_RESERVED30,
 211         PERIPH_ID_EX_RESERVED31,
 212
 213         /* W word: 31:0 */
 214         PERIPH_ID_HDA2HDMICODEC,
 215         PERIPH_ID_RESERVED1_SATACOLD,
 216         PERIPH_ID_RESERVED2_PCIERX0,
 217         PERIPH_ID_RESERVED3_PCIERX1,
 218         PERIPH_ID_RESERVED4_PCIERX2,
 219         PERIPH_ID_RESERVED5_PCIERX3,
 220         PERIPH_ID_RESERVED6_PCIERX4,
 221         PERIPH_ID_RESERVED7_PCIERX5,
 222
 223         /* 136 */
 224         PERIPH_ID_CEC,
 225         PERIPH_ID_PCIE2_IOBIST,
 226         PERIPH_ID_EMC_IOBIST,
 227         PERIPH_ID_HDMI_IOBIST,
 228         PERIPH_ID_SATA_IOBIST,
 229         PERIPH_ID_MIPI_IOBIST,
 230         PERIPH_ID_EMC1_IOBIST,
 231         PERIPH_ID_XUSB,
 232
 233         /* 144 */
 234         PERIPH_ID_CILAB,
 235         PERIPH_ID_CILCD,
 236         PERIPH_ID_CILE,
 237         PERIPH_ID_DSIA_LP,
 238         PERIPH_ID_DSIB_LP,
 239         PERIPH_ID_RESERVED21_ENTROPY,
 240         PERIPH_ID_RESERVED22_W,
 241         PERIPH_ID_RESERVED23_W,
 242
 243         /* 152 */
 244         PERIPH_ID_RESERVED24_W,
 245         PERIPH_ID_AMX0,
 246         PERIPH_ID_ADX0,
 247         PERIPH_ID_DVFS,
 248         PERIPH_ID_XUSB_SS,
 249         PERIPH_ID_EMC_DLL,
 250         PERIPH_ID_MC1,
 251         PERIPH_ID_EMC1,
 252
 253         PERIPH_ID_COUNT,
 254         PERIPH_ID_NONE = -1,
 255 };
 256
 257 enum pll_out_id {
 258         PLL_OUT1,
 259         PLL_OUT2,
 260         PLL_OUT3,
 261         PLL_OUT4
 262 };
 263
 264 /*
 265  * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
 266  * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
 267  * confusion bewteen PERIPH_ID_... and PERIPHC_...
 268  *
 269  * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
 270  * confusing.
 271  */
 272 enum periphc_internal_id {
 273         /* 0x00 */
 274         PERIPHC_I2S1,
 275         PERIPHC_I2S2,
 276         PERIPHC_SPDIF_OUT,
 277         PERIPHC_SPDIF_IN,
 278         PERIPHC_PWM,
 279         PERIPHC_05h,
 280         PERIPHC_SBC2,
 281         PERIPHC_SBC3,
 282
 283         /* 0x08 */
 284         PERIPHC_08h,
 285         PERIPHC_I2C1,
 286         PERIPHC_I2C5,
 287         PERIPHC_0bh,
 288         PERIPHC_0ch,
 289         PERIPHC_SBC1,
 290         PERIPHC_DISP1,
 291         PERIPHC_DISP2,
 292
 293         /* 0x10 */
 294         PERIPHC_CVE,
 295         PERIPHC_11h,
 296         PERIPHC_VI,
 297         PERIPHC_13h,
 298         PERIPHC_SDMMC1,
 299         PERIPHC_SDMMC2,
 300         PERIPHC_G3D,
 301         PERIPHC_G2D,
 302
 303         /* 0x18 */
 304         PERIPHC_NDFLASH,
 305         PERIPHC_SDMMC4,
 306         PERIPHC_VFIR,
 307         PERIPHC_EPP,
 308         PERIPHC_MPE,
 309         PERIPHC_MIPI,
 310         PERIPHC_UART1,
 311         PERIPHC_UART2,
 312
 313         /* 0x20 */
 314         PERIPHC_HOST1X,
 315         PERIPHC_21h,
 316         PERIPHC_TVO,
 317         PERIPHC_HDMI,
 318         PERIPHC_24h,
 319         PERIPHC_TVDAC,
 320         PERIPHC_I2C2,
 321         PERIPHC_EMC,
 322
 323         /* 0x28 */
 324         PERIPHC_UART3,
 325         PERIPHC_29h,
 326         PERIPHC_VI_SENSOR,
 327         PERIPHC_2bh,
 328         PERIPHC_2ch,
 329         PERIPHC_SBC4,
 330         PERIPHC_I2C3,
 331         PERIPHC_SDMMC3,
 332
 333         /* 0x30 */
 334         PERIPHC_UART4,
 335         PERIPHC_UART5,
 336         PERIPHC_VDE,
 337         PERIPHC_OWR,
 338         PERIPHC_NOR,
 339         PERIPHC_CSITE,
 340         PERIPHC_I2S0,
 341         PERIPHC_37h,
 342
 343         PERIPHC_VW_FIRST,
 344         /* 0x38 */
 345         PERIPHC_G3D2 = PERIPHC_VW_FIRST,
 346         PERIPHC_MSELECT,
 347         PERIPHC_TSENSOR,
 348         PERIPHC_I2S3,
 349         PERIPHC_I2S4,
 350         PERIPHC_I2C4,
 351         PERIPHC_SBC5,
 352         PERIPHC_SBC6,
 353
 354         /* 0x40 */
 355         PERIPHC_AUDIO,
 356         PERIPHC_41h,
 357         PERIPHC_DAM0,
 358         PERIPHC_DAM1,
 359         PERIPHC_DAM2,
 360         PERIPHC_HDA2CODEC2X,
 361         PERIPHC_ACTMON,
 362         PERIPHC_EXTPERIPH1,
 363
 364         /* 0x48 */
 365         PERIPHC_EXTPERIPH2,
 366         PERIPHC_EXTPERIPH3,
 367         PERIPHC_NANDSPEED,
 368         PERIPHC_I2CSLOW,
 369         PERIPHC_SYS,
 370         PERIPHC_SPEEDO,
 371         PERIPHC_4eh,
 372         PERIPHC_4fh,
 373
 374         /* 0x50 */
 375         PERIPHC_50h,
 376         PERIPHC_51h,
 377         PERIPHC_52h,
 378         PERIPHC_53h,
 379         PERIPHC_SATAOOB,
 380         PERIPHC_SATA,
 381         PERIPHC_HDA,
 382
 383         PERIPHC_COUNT,
 384
 385         PERIPHC_NONE = -1,
 386 };
 387
 388 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
 389 #define PERIPH_REG(id) \
 390         (id < PERIPH_ID_VW_FIRST) ? \
 391                 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
 392
 393 /* Mask value for a clock (within PERIPH_REG(id)) */
 394 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
 395
 396 /* return 1 if a PLL ID is in range */
 397 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
 398
 399 /* return 1 if a peripheral ID is in range */
 400 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
 401                 (id) < PERIPH_ID_COUNT)
 402
 403 #endif  /* _TEGRA114_CLOCK_TABLES_H_ */