arch/arm/include/asm/arch-tegra30/clock-tables.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 /* Tegra30 clock PLL tables */
   7
   8 #ifndef _TEGRA30_CLOCK_TABLES_H_
   9 #define _TEGRA30_CLOCK_TABLES_H_
  10
  11 /* The PLLs supported by the hardware */
  12 enum clock_id {
  13         CLOCK_ID_FIRST,
  14         CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
  15         CLOCK_ID_MEMORY,
  16         CLOCK_ID_PERIPH,
  17         CLOCK_ID_AUDIO,
  18         CLOCK_ID_USB,
  19         CLOCK_ID_DISPLAY,
  20
  21         /* now the simple ones */
  22         CLOCK_ID_FIRST_SIMPLE,
  23         CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
  24         CLOCK_ID_EPCI,
  25         CLOCK_ID_SFROM32KHZ,
  26
  27         /* These are the base clocks (inputs to the Tegra SOC) */
  28         CLOCK_ID_32KHZ,
  29         CLOCK_ID_OSC,
  30         CLOCK_ID_CLK_M,
  31
  32         CLOCK_ID_COUNT, /* number of PLLs */
  33         CLOCK_ID_DISPLAY2,      /* Tegra3, placeholder */
  34         CLOCK_ID_NONE = -1,
  35 };
  36
  37 /* The clocks supported by the hardware */
  38 enum periph_id {
  39         PERIPH_ID_FIRST,
  40
  41         /* Low word: 31:0 */
  42         PERIPH_ID_CPU = PERIPH_ID_FIRST,
  43         PERIPH_ID_COP,
  44         PERIPH_ID_TRIGSYS,
  45         PERIPH_ID_RESERVED3,
  46         PERIPH_ID_RESERVED4,
  47         PERIPH_ID_TMR,
  48         PERIPH_ID_UART1,
  49         PERIPH_ID_UART2,
  50
  51         /* 8 */
  52         PERIPH_ID_GPIO,
  53         PERIPH_ID_SDMMC2,
  54         PERIPH_ID_SPDIF,
  55         PERIPH_ID_I2S1,
  56         PERIPH_ID_I2C1,
  57         PERIPH_ID_NDFLASH,
  58         PERIPH_ID_SDMMC1,
  59         PERIPH_ID_SDMMC4,
  60
  61         /* 16 */
  62         PERIPH_ID_RESERVED16,
  63         PERIPH_ID_PWM,
  64         PERIPH_ID_I2S2,
  65         PERIPH_ID_EPP,
  66         PERIPH_ID_VI,
  67         PERIPH_ID_2D,
  68         PERIPH_ID_USBD,
  69         PERIPH_ID_ISP,
  70
  71         /* 24 */
  72         PERIPH_ID_3D,
  73         PERIPH_ID_RESERVED24,
  74         PERIPH_ID_DISP2,
  75         PERIPH_ID_DISP1,
  76         PERIPH_ID_HOST1X,
  77         PERIPH_ID_VCP,
  78         PERIPH_ID_I2S0,
  79         PERIPH_ID_CACHE2,
  80
  81         /* Middle word: 63:32 */
  82         PERIPH_ID_MEM,
  83         PERIPH_ID_AHBDMA,
  84         PERIPH_ID_APBDMA,
  85         PERIPH_ID_RESERVED35,
  86         PERIPH_ID_KBC,
  87         PERIPH_ID_STAT_MON,
  88         PERIPH_ID_PMC,
  89         PERIPH_ID_FUSE,
  90
  91         /* 40 */
  92         PERIPH_ID_KFUSE,
  93         PERIPH_ID_SBC1,
  94         PERIPH_ID_SNOR,
  95         PERIPH_ID_RESERVED43,
  96         PERIPH_ID_SBC2,
  97         PERIPH_ID_RESERVED45,
  98         PERIPH_ID_SBC3,
  99         PERIPH_ID_DVC_I2C,
 100
 101         /* 48 */
 102         PERIPH_ID_DSI,
 103         PERIPH_ID_TVO,
 104         PERIPH_ID_MIPI,
 105         PERIPH_ID_HDMI,
 106         PERIPH_ID_CSI,
 107         PERIPH_ID_TVDAC,
 108         PERIPH_ID_I2C2,
 109         PERIPH_ID_UART3,
 110
 111         /* 56 */
 112         PERIPH_ID_RESERVED56,
 113         PERIPH_ID_EMC,
 114         PERIPH_ID_USB2,
 115         PERIPH_ID_USB3,
 116         PERIPH_ID_MPE,
 117         PERIPH_ID_VDE,
 118         PERIPH_ID_BSEA,
 119         PERIPH_ID_BSEV,
 120
 121         /* Upper word 95:64 */
 122         PERIPH_ID_SPEEDO,
 123         PERIPH_ID_UART4,
 124         PERIPH_ID_UART5,
 125         PERIPH_ID_I2C3,
 126         PERIPH_ID_SBC4,
 127         PERIPH_ID_SDMMC3,
 128         PERIPH_ID_PCIE,
 129         PERIPH_ID_OWR,
 130
 131         /* 72 */
 132         PERIPH_ID_AFI,
 133         PERIPH_ID_CORESIGHT,
 134         PERIPH_ID_PCIEXCLK,
 135         PERIPH_ID_AVPUCQ,
 136         PERIPH_ID_RESERVED76,
 137         PERIPH_ID_RESERVED77,
 138         PERIPH_ID_RESERVED78,
 139         PERIPH_ID_DTV,
 140
 141         /* 80 */
 142         PERIPH_ID_NANDSPEED,
 143         PERIPH_ID_I2CSLOW,
 144         PERIPH_ID_DSIB,
 145         PERIPH_ID_RESERVED83,
 146         PERIPH_ID_IRAMA,
 147         PERIPH_ID_IRAMB,
 148         PERIPH_ID_IRAMC,
 149         PERIPH_ID_IRAMD,
 150
 151         /* 88 */
 152         PERIPH_ID_CRAM2,
 153         PERIPH_ID_RESERVED89,
 154         PERIPH_ID_MDOUBLER,
 155         PERIPH_ID_RESERVED91,
 156         PERIPH_ID_SUSOUT,
 157         PERIPH_ID_RESERVED93,
 158         PERIPH_ID_RESERVED94,
 159         PERIPH_ID_RESERVED95,
 160
 161         PERIPH_ID_VW_FIRST,
 162         /* V word: 31:0 */
 163         PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
 164         PERIPH_ID_CPULP,
 165         PERIPH_ID_3D2,
 166         PERIPH_ID_MSELECT,
 167         PERIPH_ID_TSENSOR,
 168         PERIPH_ID_I2S3,
 169         PERIPH_ID_I2S4,
 170         PERIPH_ID_I2C4,
 171
 172         /* 08 */
 173         PERIPH_ID_SBC5,
 174         PERIPH_ID_SBC6,
 175         PERIPH_ID_AUDIO,
 176         PERIPH_ID_APBIF,
 177         PERIPH_ID_DAM0,
 178         PERIPH_ID_DAM1,
 179         PERIPH_ID_DAM2,
 180         PERIPH_ID_HDA2CODEC2X,
 181
 182         /* 16 */
 183         PERIPH_ID_ATOMICS,
 184         PERIPH_ID_EX_RESERVED17,
 185         PERIPH_ID_EX_RESERVED18,
 186         PERIPH_ID_EX_RESERVED19,
 187         PERIPH_ID_EX_RESERVED20,
 188         PERIPH_ID_EX_RESERVED21,
 189         PERIPH_ID_EX_RESERVED22,
 190         PERIPH_ID_ACTMON,
 191
 192         /* 24 */
 193         PERIPH_ID_EX_RESERVED24,
 194         PERIPH_ID_EX_RESERVED25,
 195         PERIPH_ID_EX_RESERVED26,
 196         PERIPH_ID_EX_RESERVED27,
 197         PERIPH_ID_SATA,
 198         PERIPH_ID_HDA,
 199         PERIPH_ID_EX_RESERVED30,
 200         PERIPH_ID_EX_RESERVED31,
 201
 202         /* W word: 31:0 */
 203         PERIPH_ID_HDA2HDMICODEC,
 204         PERIPH_ID_SATACOLD,
 205         PERIPH_ID_RESERVED0_PCIERX0,
 206         PERIPH_ID_RESERVED1_PCIERX1,
 207         PERIPH_ID_RESERVED2_PCIERX2,
 208         PERIPH_ID_RESERVED3_PCIERX3,
 209         PERIPH_ID_RESERVED4_PCIERX4,
 210         PERIPH_ID_RESERVED5_PCIERX5,
 211
 212         /* 40 */
 213         PERIPH_ID_CEC,
 214         PERIPH_ID_RESERVED6_PCIE2,
 215         PERIPH_ID_RESERVED7_EMC,
 216         PERIPH_ID_RESERVED8_HDMI,
 217         PERIPH_ID_RESERVED9_SATA,
 218         PERIPH_ID_RESERVED10_MIPI,
 219         PERIPH_ID_EX_RESERVED46,
 220         PERIPH_ID_EX_RESERVED47,
 221
 222         PERIPH_ID_COUNT,
 223         PERIPH_ID_NONE = -1,
 224 };
 225
 226 enum pll_out_id {
 227         PLL_OUT1,
 228         PLL_OUT2,
 229         PLL_OUT3,
 230         PLL_OUT4
 231 };
 232
 233 /*
 234  * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
 235  * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
 236  * confusion bewteen PERIPH_ID_... and PERIPHC_...
 237  *
 238  * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
 239  * confusing.
 240  */
 241 enum periphc_internal_id {
 242         /* 0x00 */
 243         PERIPHC_I2S1,
 244         PERIPHC_I2S2,
 245         PERIPHC_SPDIF_OUT,
 246         PERIPHC_SPDIF_IN,
 247         PERIPHC_PWM,
 248         PERIPHC_05h,
 249         PERIPHC_SBC2,
 250         PERIPHC_SBC3,
 251
 252         /* 0x08 */
 253         PERIPHC_08h,
 254         PERIPHC_I2C1,
 255         PERIPHC_DVC_I2C,
 256         PERIPHC_0bh,
 257         PERIPHC_0ch,
 258         PERIPHC_SBC1,
 259         PERIPHC_DISP1,
 260         PERIPHC_DISP2,
 261
 262         /* 0x10 */
 263         PERIPHC_CVE,
 264         PERIPHC_11h,
 265         PERIPHC_VI,
 266         PERIPHC_13h,
 267         PERIPHC_SDMMC1,
 268         PERIPHC_SDMMC2,
 269         PERIPHC_G3D,
 270         PERIPHC_G2D,
 271
 272         /* 0x18 */
 273         PERIPHC_NDFLASH,
 274         PERIPHC_SDMMC4,
 275         PERIPHC_VFIR,
 276         PERIPHC_EPP,
 277         PERIPHC_MPE,
 278         PERIPHC_MIPI,
 279         PERIPHC_UART1,
 280         PERIPHC_UART2,
 281
 282         /* 0x20 */
 283         PERIPHC_HOST1X,
 284         PERIPHC_21h,
 285         PERIPHC_TVO,
 286         PERIPHC_HDMI,
 287         PERIPHC_24h,
 288         PERIPHC_TVDAC,
 289         PERIPHC_I2C2,
 290         PERIPHC_EMC,
 291
 292         /* 0x28 */
 293         PERIPHC_UART3,
 294         PERIPHC_29h,
 295         PERIPHC_VI_SENSOR,
 296         PERIPHC_2bh,
 297         PERIPHC_2ch,
 298         PERIPHC_SBC4,
 299         PERIPHC_I2C3,
 300         PERIPHC_SDMMC3,
 301
 302         /* 0x30 */
 303         PERIPHC_UART4,
 304         PERIPHC_UART5,
 305         PERIPHC_VDE,
 306         PERIPHC_OWR,
 307         PERIPHC_NOR,
 308         PERIPHC_CSITE,
 309         PERIPHC_I2S0,
 310         PERIPHC_37h,
 311
 312         PERIPHC_VW_FIRST,
 313         /* 0x38 */
 314         PERIPHC_G3D2 = PERIPHC_VW_FIRST,
 315         PERIPHC_MSELECT,
 316         PERIPHC_TSENSOR,
 317         PERIPHC_I2S3,
 318         PERIPHC_I2S4,
 319         PERIPHC_I2C4,
 320         PERIPHC_SBC5,
 321         PERIPHC_SBC6,
 322
 323         /* 0x40 */
 324         PERIPHC_AUDIO,
 325         PERIPHC_41h,
 326         PERIPHC_DAM0,
 327         PERIPHC_DAM1,
 328         PERIPHC_DAM2,
 329         PERIPHC_HDA2CODEC2X,
 330         PERIPHC_ACTMON,
 331         PERIPHC_EXTPERIPH1,
 332
 333         /* 0x48 */
 334         PERIPHC_EXTPERIPH2,
 335         PERIPHC_EXTPERIPH3,
 336         PERIPHC_NANDSPEED,
 337         PERIPHC_I2CSLOW,
 338         PERIPHC_SYS,
 339         PERIPHC_SPEEDO,
 340         PERIPHC_4eh,
 341         PERIPHC_4fh,
 342
 343         /* 0x50 */
 344         PERIPHC_50h,
 345         PERIPHC_51h,
 346         PERIPHC_52h,
 347         PERIPHC_53h,
 348         PERIPHC_SATAOOB,
 349         PERIPHC_SATA,
 350         PERIPHC_HDA,
 351
 352         PERIPHC_COUNT,
 353
 354         PERIPHC_NONE = -1,
 355 };
 356
 357 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
 358 #define PERIPH_REG(id) \
 359         (id < PERIPH_ID_VW_FIRST) ? \
 360                 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
 361
 362 /* Mask value for a clock (within PERIPH_REG(id)) */
 363 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
 364
 365 /* return 1 if a PLL ID is in range */
 366 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
 367
 368 /* return 1 if a peripheral ID is in range */
 369 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
 370                 (id) < PERIPH_ID_COUNT)
 371
 372 #endif  /* _TEGRA30_CLOCK_TABLES_H_ */