2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _TEGRA30_PINMUX_H_
8 #define _TEGRA30_PINMUX_H_
11 PMUX_PINGRP_ULPI_DATA0_PO1
,
12 PMUX_PINGRP_ULPI_DATA1_PO2
,
13 PMUX_PINGRP_ULPI_DATA2_PO3
,
14 PMUX_PINGRP_ULPI_DATA3_PO4
,
15 PMUX_PINGRP_ULPI_DATA4_PO5
,
16 PMUX_PINGRP_ULPI_DATA5_PO6
,
17 PMUX_PINGRP_ULPI_DATA6_PO7
,
18 PMUX_PINGRP_ULPI_DATA7_PO0
,
19 PMUX_PINGRP_ULPI_CLK_PY0
,
20 PMUX_PINGRP_ULPI_DIR_PY1
,
21 PMUX_PINGRP_ULPI_NXT_PY2
,
22 PMUX_PINGRP_ULPI_STP_PY3
,
23 PMUX_PINGRP_DAP3_FS_PP0
,
24 PMUX_PINGRP_DAP3_DIN_PP1
,
25 PMUX_PINGRP_DAP3_DOUT_PP2
,
26 PMUX_PINGRP_DAP3_SCLK_PP3
,
29 PMUX_PINGRP_SDMMC1_CLK_PZ0
,
30 PMUX_PINGRP_SDMMC1_CMD_PZ1
,
31 PMUX_PINGRP_SDMMC1_DAT3_PY4
,
32 PMUX_PINGRP_SDMMC1_DAT2_PY5
,
33 PMUX_PINGRP_SDMMC1_DAT1_PY6
,
34 PMUX_PINGRP_SDMMC1_DAT0_PY7
,
37 PMUX_PINGRP_CLK2_OUT_PW5
,
38 PMUX_PINGRP_CLK2_REQ_PCC5
,
39 PMUX_PINGRP_LCD_PWR1_PC1
,
40 PMUX_PINGRP_LCD_PWR2_PC6
,
41 PMUX_PINGRP_LCD_SDIN_PZ2
,
42 PMUX_PINGRP_LCD_SDOUT_PN5
,
43 PMUX_PINGRP_LCD_WR_N_PZ3
,
44 PMUX_PINGRP_LCD_CS0_N_PN4
,
45 PMUX_PINGRP_LCD_DC0_PN6
,
46 PMUX_PINGRP_LCD_SCK_PZ4
,
47 PMUX_PINGRP_LCD_PWR0_PB2
,
48 PMUX_PINGRP_LCD_PCLK_PB3
,
49 PMUX_PINGRP_LCD_DE_PJ1
,
50 PMUX_PINGRP_LCD_HSYNC_PJ3
,
51 PMUX_PINGRP_LCD_VSYNC_PJ4
,
52 PMUX_PINGRP_LCD_D0_PE0
,
53 PMUX_PINGRP_LCD_D1_PE1
,
54 PMUX_PINGRP_LCD_D2_PE2
,
55 PMUX_PINGRP_LCD_D3_PE3
,
56 PMUX_PINGRP_LCD_D4_PE4
,
57 PMUX_PINGRP_LCD_D5_PE5
,
58 PMUX_PINGRP_LCD_D6_PE6
,
59 PMUX_PINGRP_LCD_D7_PE7
,
60 PMUX_PINGRP_LCD_D8_PF0
,
61 PMUX_PINGRP_LCD_D9_PF1
,
62 PMUX_PINGRP_LCD_D10_PF2
,
63 PMUX_PINGRP_LCD_D11_PF3
,
64 PMUX_PINGRP_LCD_D12_PF4
,
65 PMUX_PINGRP_LCD_D13_PF5
,
66 PMUX_PINGRP_LCD_D14_PF6
,
67 PMUX_PINGRP_LCD_D15_PF7
,
68 PMUX_PINGRP_LCD_D16_PM0
,
69 PMUX_PINGRP_LCD_D17_PM1
,
70 PMUX_PINGRP_LCD_D18_PM2
,
71 PMUX_PINGRP_LCD_D19_PM3
,
72 PMUX_PINGRP_LCD_D20_PM4
,
73 PMUX_PINGRP_LCD_D21_PM5
,
74 PMUX_PINGRP_LCD_D22_PM6
,
75 PMUX_PINGRP_LCD_D23_PM7
,
76 PMUX_PINGRP_LCD_CS1_N_PW0
,
77 PMUX_PINGRP_LCD_M1_PW1
,
78 PMUX_PINGRP_LCD_DC1_PD2
,
79 PMUX_PINGRP_HDMI_INT_PN7
,
80 PMUX_PINGRP_DDC_SCL_PV4
,
81 PMUX_PINGRP_DDC_SDA_PV5
,
82 PMUX_PINGRP_CRT_HSYNC_PV6
,
83 PMUX_PINGRP_CRT_VSYNC_PV7
,
84 PMUX_PINGRP_VI_D0_PT4
,
85 PMUX_PINGRP_VI_D1_PD5
,
86 PMUX_PINGRP_VI_D2_PL0
,
87 PMUX_PINGRP_VI_D3_PL1
,
88 PMUX_PINGRP_VI_D4_PL2
,
89 PMUX_PINGRP_VI_D5_PL3
,
90 PMUX_PINGRP_VI_D6_PL4
,
91 PMUX_PINGRP_VI_D7_PL5
,
92 PMUX_PINGRP_VI_D8_PL6
,
93 PMUX_PINGRP_VI_D9_PL7
,
94 PMUX_PINGRP_VI_D10_PT2
,
95 PMUX_PINGRP_VI_D11_PT3
,
96 PMUX_PINGRP_VI_PCLK_PT0
,
97 PMUX_PINGRP_VI_MCLK_PT1
,
98 PMUX_PINGRP_VI_VSYNC_PD6
,
99 PMUX_PINGRP_VI_HSYNC_PD7
,
100 PMUX_PINGRP_UART2_RXD_PC3
,
101 PMUX_PINGRP_UART2_TXD_PC2
,
102 PMUX_PINGRP_UART2_RTS_N_PJ6
,
103 PMUX_PINGRP_UART2_CTS_N_PJ5
,
104 PMUX_PINGRP_UART3_TXD_PW6
,
105 PMUX_PINGRP_UART3_RXD_PW7
,
106 PMUX_PINGRP_UART3_CTS_N_PA1
,
107 PMUX_PINGRP_UART3_RTS_N_PC0
,
115 PMUX_PINGRP_GEN1_I2C_SDA_PC5
,
116 PMUX_PINGRP_GEN1_I2C_SCL_PC4
,
117 PMUX_PINGRP_DAP4_FS_PP4
,
118 PMUX_PINGRP_DAP4_DIN_PP5
,
119 PMUX_PINGRP_DAP4_DOUT_PP6
,
120 PMUX_PINGRP_DAP4_SCLK_PP7
,
121 PMUX_PINGRP_CLK3_OUT_PEE0
,
122 PMUX_PINGRP_CLK3_REQ_PEE1
,
123 PMUX_PINGRP_GMI_WP_N_PC7
,
124 PMUX_PINGRP_GMI_IORDY_PI5
,
125 PMUX_PINGRP_GMI_WAIT_PI7
,
126 PMUX_PINGRP_GMI_ADV_N_PK0
,
127 PMUX_PINGRP_GMI_CLK_PK1
,
128 PMUX_PINGRP_GMI_CS0_N_PJ0
,
129 PMUX_PINGRP_GMI_CS1_N_PJ2
,
130 PMUX_PINGRP_GMI_CS2_N_PK3
,
131 PMUX_PINGRP_GMI_CS3_N_PK4
,
132 PMUX_PINGRP_GMI_CS4_N_PK2
,
133 PMUX_PINGRP_GMI_CS6_N_PI3
,
134 PMUX_PINGRP_GMI_CS7_N_PI6
,
135 PMUX_PINGRP_GMI_AD0_PG0
,
136 PMUX_PINGRP_GMI_AD1_PG1
,
137 PMUX_PINGRP_GMI_AD2_PG2
,
138 PMUX_PINGRP_GMI_AD3_PG3
,
139 PMUX_PINGRP_GMI_AD4_PG4
,
140 PMUX_PINGRP_GMI_AD5_PG5
,
141 PMUX_PINGRP_GMI_AD6_PG6
,
142 PMUX_PINGRP_GMI_AD7_PG7
,
143 PMUX_PINGRP_GMI_AD8_PH0
,
144 PMUX_PINGRP_GMI_AD9_PH1
,
145 PMUX_PINGRP_GMI_AD10_PH2
,
146 PMUX_PINGRP_GMI_AD11_PH3
,
147 PMUX_PINGRP_GMI_AD12_PH4
,
148 PMUX_PINGRP_GMI_AD13_PH5
,
149 PMUX_PINGRP_GMI_AD14_PH6
,
150 PMUX_PINGRP_GMI_AD15_PH7
,
151 PMUX_PINGRP_GMI_A16_PJ7
,
152 PMUX_PINGRP_GMI_A17_PB0
,
153 PMUX_PINGRP_GMI_A18_PB1
,
154 PMUX_PINGRP_GMI_A19_PK7
,
155 PMUX_PINGRP_GMI_WR_N_PI0
,
156 PMUX_PINGRP_GMI_OE_N_PI1
,
157 PMUX_PINGRP_GMI_DQS_PI2
,
158 PMUX_PINGRP_GMI_RST_N_PI4
,
159 PMUX_PINGRP_GEN2_I2C_SCL_PT5
,
160 PMUX_PINGRP_GEN2_I2C_SDA_PT6
,
161 PMUX_PINGRP_SDMMC4_CLK_PCC4
,
162 PMUX_PINGRP_SDMMC4_CMD_PT7
,
163 PMUX_PINGRP_SDMMC4_DAT0_PAA0
,
164 PMUX_PINGRP_SDMMC4_DAT1_PAA1
,
165 PMUX_PINGRP_SDMMC4_DAT2_PAA2
,
166 PMUX_PINGRP_SDMMC4_DAT3_PAA3
,
167 PMUX_PINGRP_SDMMC4_DAT4_PAA4
,
168 PMUX_PINGRP_SDMMC4_DAT5_PAA5
,
169 PMUX_PINGRP_SDMMC4_DAT6_PAA6
,
170 PMUX_PINGRP_SDMMC4_DAT7_PAA7
,
171 PMUX_PINGRP_SDMMC4_RST_N_PCC3
,
172 PMUX_PINGRP_CAM_MCLK_PCC0
,
175 PMUX_PINGRP_CAM_I2C_SCL_PBB1
,
176 PMUX_PINGRP_CAM_I2C_SDA_PBB2
,
183 PMUX_PINGRP_JTAG_RTCK_PU7
,
184 PMUX_PINGRP_PWR_I2C_SCL_PZ6
,
185 PMUX_PINGRP_PWR_I2C_SDA_PZ7
,
186 PMUX_PINGRP_KB_ROW0_PR0
,
187 PMUX_PINGRP_KB_ROW1_PR1
,
188 PMUX_PINGRP_KB_ROW2_PR2
,
189 PMUX_PINGRP_KB_ROW3_PR3
,
190 PMUX_PINGRP_KB_ROW4_PR4
,
191 PMUX_PINGRP_KB_ROW5_PR5
,
192 PMUX_PINGRP_KB_ROW6_PR6
,
193 PMUX_PINGRP_KB_ROW7_PR7
,
194 PMUX_PINGRP_KB_ROW8_PS0
,
195 PMUX_PINGRP_KB_ROW9_PS1
,
196 PMUX_PINGRP_KB_ROW10_PS2
,
197 PMUX_PINGRP_KB_ROW11_PS3
,
198 PMUX_PINGRP_KB_ROW12_PS4
,
199 PMUX_PINGRP_KB_ROW13_PS5
,
200 PMUX_PINGRP_KB_ROW14_PS6
,
201 PMUX_PINGRP_KB_ROW15_PS7
,
202 PMUX_PINGRP_KB_COL0_PQ0
,
203 PMUX_PINGRP_KB_COL1_PQ1
,
204 PMUX_PINGRP_KB_COL2_PQ2
,
205 PMUX_PINGRP_KB_COL3_PQ3
,
206 PMUX_PINGRP_KB_COL4_PQ4
,
207 PMUX_PINGRP_KB_COL5_PQ5
,
208 PMUX_PINGRP_KB_COL6_PQ6
,
209 PMUX_PINGRP_KB_COL7_PQ7
,
210 PMUX_PINGRP_CLK_32K_OUT_PA0
,
211 PMUX_PINGRP_SYS_CLK_REQ_PZ5
,
212 PMUX_PINGRP_CORE_PWR_REQ
,
213 PMUX_PINGRP_CPU_PWR_REQ
,
214 PMUX_PINGRP_PWR_INT_N
,
215 PMUX_PINGRP_CLK_32K_IN
,
217 PMUX_PINGRP_DAP1_FS_PN0
,
218 PMUX_PINGRP_DAP1_DIN_PN1
,
219 PMUX_PINGRP_DAP1_DOUT_PN2
,
220 PMUX_PINGRP_DAP1_SCLK_PN3
,
221 PMUX_PINGRP_CLK1_REQ_PEE2
,
222 PMUX_PINGRP_CLK1_OUT_PW4
,
223 PMUX_PINGRP_SPDIF_IN_PK6
,
224 PMUX_PINGRP_SPDIF_OUT_PK5
,
225 PMUX_PINGRP_DAP2_FS_PA2
,
226 PMUX_PINGRP_DAP2_DIN_PA4
,
227 PMUX_PINGRP_DAP2_DOUT_PA5
,
228 PMUX_PINGRP_DAP2_SCLK_PA3
,
229 PMUX_PINGRP_SPI2_MOSI_PX0
,
230 PMUX_PINGRP_SPI2_MISO_PX1
,
231 PMUX_PINGRP_SPI2_CS0_N_PX3
,
232 PMUX_PINGRP_SPI2_SCK_PX2
,
233 PMUX_PINGRP_SPI1_MOSI_PX4
,
234 PMUX_PINGRP_SPI1_SCK_PX5
,
235 PMUX_PINGRP_SPI1_CS0_N_PX6
,
236 PMUX_PINGRP_SPI1_MISO_PX7
,
237 PMUX_PINGRP_SPI2_CS1_N_PW2
,
238 PMUX_PINGRP_SPI2_CS2_N_PW3
,
239 PMUX_PINGRP_SDMMC3_CLK_PA6
,
240 PMUX_PINGRP_SDMMC3_CMD_PA7
,
241 PMUX_PINGRP_SDMMC3_DAT0_PB7
,
242 PMUX_PINGRP_SDMMC3_DAT1_PB6
,
243 PMUX_PINGRP_SDMMC3_DAT2_PB5
,
244 PMUX_PINGRP_SDMMC3_DAT3_PB4
,
245 PMUX_PINGRP_SDMMC3_DAT4_PD1
,
246 PMUX_PINGRP_SDMMC3_DAT5_PD0
,
247 PMUX_PINGRP_SDMMC3_DAT6_PD3
,
248 PMUX_PINGRP_SDMMC3_DAT7_PD4
,
249 PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0
,
250 PMUX_PINGRP_PEX_L0_RST_N_PDD1
,
251 PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2
,
252 PMUX_PINGRP_PEX_WAKE_N_PDD3
,
253 PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4
,
254 PMUX_PINGRP_PEX_L1_RST_N_PDD5
,
255 PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6
,
256 PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7
,
257 PMUX_PINGRP_PEX_L2_RST_N_PCC6
,
258 PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7
,
259 PMUX_PINGRP_HDMI_CEC_PEE3
,
289 PMUX_DRVGRP_SDIO1
= (0x84 / 4),
290 PMUX_DRVGRP_CRT
= (0x90 / 4),
304 PMUX_DRVGRP_CEC
= (0xd0 / 4),
312 PMUX_FUNC_CLK_12M_OUT
,
313 PMUX_FUNC_CLK_32K_IN
,
314 PMUX_FUNC_CORE_PWR_REQ
,
315 PMUX_FUNC_CPU_PWR_REQ
,
323 PMUX_FUNC_EXTPERIPH1
,
324 PMUX_FUNC_EXTPERIPH2
,
325 PMUX_FUNC_EXTPERIPH3
,
394 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
395 #define TEGRA_PMX_SOC_HAS_DRVGRPS
396 #define TEGRA_PMX_GRPS_HAVE_LPMD
397 #define TEGRA_PMX_GRPS_HAVE_SCHMT
398 #define TEGRA_PMX_GRPS_HAVE_HSM
399 #define TEGRA_PMX_PINS_HAVE_E_INPUT
400 #define TEGRA_PMX_PINS_HAVE_LOCK
401 #define TEGRA_PMX_PINS_HAVE_OD
402 #define TEGRA_PMX_PINS_HAVE_IO_RESET
403 #include <asm/arch-tegra/pinmux.h>
405 #endif /* _TEGRA30_PINMUX_H_ */