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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/include/asm/arch-vf610/crm_regs.h
2d7a32d85a47113cfce01095ee3098e587c701f0
2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
12 /* Clock Controller Module (CCM) */
56 /* Analog components control digital interface (ANADIG) */
58 u32 reserved_0x000
[4];
60 u32 reserved_0x014
[3];
62 u32 reserved_0x024
[3];
64 u32 reserved_0x034
[3];
66 u32 reserved_0x044
[3];
68 u32 reserved_0x054
[3];
70 u32 reserved_0x064
[3];
72 u32 reserved_0x074
[3];
74 u32 reserved_0x084
[3];
76 u32 reserved_0x094
[3];
78 u32 reserved_0x0A4
[3];
80 u32 reserved_0x0B4
[3];
82 u32 reserved_0x0C4
[7];
84 u32 reserved_0x0E4
[3];
86 u32 reserved_0x0F4
[3];
88 u32 reserved_0x104
[3];
90 u32 reserved_0x114
[3];
92 u32 reserved_0x124
[3];
94 u32 reserved_0x134
[7];
96 u32 reserved_0x154
[3];
98 u32 reserved_0x164
[63];
100 u32 reserved_0x264
[3];
102 u32 reserved_0x274
[3];
104 u32 reserved_0x284
[3];
106 u32 reserved_0x294
[3];
108 u32 reserved_0x2A4
[3];
110 u32 reserved_0x2B4
[3];
115 #define CCM_CCR_FIRC_EN (1 << 16)
116 #define CCM_CCR_OSCNT_MASK 0xff
117 #define CCM_CCR_OSCNT(v) ((v) & 0xff)
119 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
120 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
121 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
123 #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
124 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
125 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
127 #define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
128 #define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
129 #define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
130 #define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
131 #define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
132 #define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
133 #define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
134 #define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
136 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
137 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
139 #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
140 #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
141 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
143 #define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
144 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
145 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
146 #define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
147 #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
148 #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
149 #define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
150 #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
151 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
153 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
154 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
155 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
157 #define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
159 #define CCM_CSCDR2_ESDHC1_EN (1 << 29)
160 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
161 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
162 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
164 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
165 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
166 #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
168 #define CCM_REG_CTRL_MASK 0xffffffff
169 #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
170 #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
171 #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
172 #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
173 #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
174 #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
175 #define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
176 #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
177 #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
178 #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
179 #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
180 #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
181 #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
182 #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
183 #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
184 #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
185 #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
186 #define CCM_CCGR9_FEC0_CTRL_MASK 0x3
187 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
189 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
190 #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
191 #define ANADIG_PLL2_CTRL_DIV_SELECT 1
192 #define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
193 #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
194 #define ANADIG_PLL1_CTRL_DIV_SELECT 1
196 #define FASE_CLK_FREQ 24000000
197 #define SLOW_CLK_FREQ 32000
198 #define PLL1_PFD1_FREQ 500000000
199 #define PLL1_PFD2_FREQ 452000000
200 #define PLL1_PFD3_FREQ 396000000
201 #define PLL1_PFD4_FREQ 528000000
202 #define PLL1_MAIN_FREQ 528000000
203 #define PLL2_PFD1_FREQ 500000000
204 #define PLL2_PFD2_FREQ 396000000
205 #define PLL2_PFD3_FREQ 339000000
206 #define PLL2_PFD4_FREQ 413000000
207 #define PLL2_MAIN_FREQ 528000000
208 #define PLL3_MAIN_FREQ 480000000
209 #define PLL3_PFD3_FREQ 298000000
210 #define PLL5_MAIN_FREQ 500000000
212 #define ENET_EXTERNAL_CLK 50000000
213 #define AUDIO_EXTERNAL_CLK 24576000
215 #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */