arch/arm/include/asm/arch-vf610/imx-regs.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __ASM_ARCH_IMX_REGS_H__
  21 #define __ASM_ARCH_IMX_REGS_H__
  22
  23 #define ARCH_MXC
  24
  25 #define IRAM_BASE_ADDR          0x3F000000      /* internal ram */
  26 #define IRAM_SIZE               0x00080000      /* 512 KB */
  27
  28 #define AIPS0_BASE_ADDR         0x40000000
  29 #define AIPS1_BASE_ADDR         0x40080000
  30
  31 /* AIPS 0 */
  32 #define MSCM_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00001000)
  33 #define MSCM_IR_BASE_ADDR       (AIPS0_BASE_ADDR + 0x00001800)
  34 #define CA5SCU_BASE_ADDR        (AIPS0_BASE_ADDR + 0x00002000)
  35 #define CA5_INTD_BASE_ADDR      (AIPS0_BASE_ADDR + 0x00003000)
  36 #define CA5_L2C_BASE_ADDR       (AIPS0_BASE_ADDR + 0x00006000)
  37 #define NIC0_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00008000)
  38 #define NIC1_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00009000)
  39 #define NIC2_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0000A000)
  40 #define NIC3_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0000B000)
  41 #define NIC4_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0000C000)
  42 #define NIC5_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0000D000)
  43 #define NIC6_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0000E000)
  44 #define NIC7_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0000F000)
  45 #define AHBTZASC_BASE_ADDR      (AIPS0_BASE_ADDR + 0x00010000)
  46 #define TZASC_SYS0_BASE_ADDR    (AIPS0_BASE_ADDR + 0x00011000)
  47 #define TZASC_SYS1_BASE_ADDR    (AIPS0_BASE_ADDR + 0x00012000)
  48 #define TZASC_GFX_BASE_ADDR     (AIPS0_BASE_ADDR + 0x00013000)
  49 #define TZASC_DDR0_BASE_ADDR    (AIPS0_BASE_ADDR + 0x00014000)
  50 #define TZASC_DDR1_BASE_ADDR    (AIPS0_BASE_ADDR + 0x00015000)
  51 #define CSU_BASE_ADDR           (AIPS0_BASE_ADDR + 0x00017000)
  52 #define DMA0_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00018000)
  53 #define DMA0_TCD_BASE_ADDR      (AIPS0_BASE_ADDR + 0x00019000)
  54 #define SEMA4_BASE_ADDR         (AIPS0_BASE_ADDR + 0x0001D000)
  55 #define FB_BASE_ADDR            (AIPS0_BASE_ADDR + 0x0001E000)
  56 #define DMA_MUX0_BASE_ADDR      (AIPS0_BASE_ADDR + 0x00024000)
  57 #define UART0_BASE              (AIPS0_BASE_ADDR + 0x00027000)
  58 #define UART1_BASE              (AIPS0_BASE_ADDR + 0x00028000)
  59 #define UART2_BASE              (AIPS0_BASE_ADDR + 0x00029000)
  60 #define UART3_BASE              (AIPS0_BASE_ADDR + 0x0002A000)
  61 #define SPI0_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0002C000)
  62 #define SPI1_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0002D000)
  63 #define SAI0_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0002F000)
  64 #define SAI1_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00030000)
  65 #define SAI2_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00031000)
  66 #define SAI3_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00032000)
  67 #define CRC_BASE_ADDR           (AIPS0_BASE_ADDR + 0x00033000)
  68 #define PDB_BASE_ADDR           (AIPS0_BASE_ADDR + 0x00036000)
  69 #define PIT_BASE_ADDR           (AIPS0_BASE_ADDR + 0x00037000)
  70 #define FTM0_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00038000)
  71 #define FTM1_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00039000)
  72 #define ADC_BASE_ADDR           (AIPS0_BASE_ADDR + 0x0003B000)
  73 #define TCON0_BASE_ADDR         (AIPS0_BASE_ADDR + 0x0003D000)
  74 #define WDOG1_BASE_ADDR         (AIPS0_BASE_ADDR + 0x0003E000)
  75 #define LPTMR_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00040000)
  76 #define RLE_BASE_ADDR           (AIPS0_BASE_ADDR + 0x00042000)
  77 #define MLB_BASE_ADDR           (AIPS0_BASE_ADDR + 0x00043000)
  78 #define QSPI0_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00044000)
  79 #define IOMUXC_BASE_ADDR        (AIPS0_BASE_ADDR + 0x00048000)
  80 #define ANADIG_BASE_ADDR        (AIPS0_BASE_ADDR + 0x00050000)
  81 #define SCSCM_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00052000)
  82 #define ASRC_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00060000)
  83 #define SPDIF_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00061000)
  84 #define ESAI_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00062000)
  85 #define ESAI_FIFO_BASE_ADDR     (AIPS0_BASE_ADDR + 0x00063000)
  86 #define WDOG_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00065000)
  87 #define I2C0_BASE_ADDR          (AIPS0_BASE_ADDR + 0x00066000)
  88 #define WKUP_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0006A000)
  89 #define CCM_BASE_ADDR           (AIPS0_BASE_ADDR + 0x0006B000)
  90 #define GPC_BASE_ADDR           (AIPS0_BASE_ADDR + 0x0006C000)
  91 #define VREG_DIG_BASE_ADDR      (AIPS0_BASE_ADDR + 0x0006D000)
  92 #define SRC_BASE_ADDR           (AIPS0_BASE_ADDR + 0x0006E000)
  93 #define CMU_BASE_ADDR           (AIPS0_BASE_ADDR + 0x0006F000)
  94
  95 /* AIPS 1 */
  96 #define OCOTP_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00025000)
  97 #define DDR_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0002E000)
  98 #define ESDHC0_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00031000)
  99 #define ESDHC1_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00032000)
 100 #define ENET_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00050000)
 101
 102 /* MUX mode and PAD ctrl are in one register */
 103 #define CONFIG_IOMUX_SHARE_CONF_REG
 104
 105 #define FEC_QUIRK_ENET_MAC
 106
 107 /* MSCM interrupt rounter */
 108 #define MSCM_IRSPRC_CP0_EN                              1
 109 #define MSCM_IRSPRC_NUM                                 112
 110
 111 /* DDRMC */
 112 #define DDRMC_PHY_DQ_TIMING                             0x00002613
 113 #define DDRMC_PHY_DQS_TIMING                            0x00002615
 114 #define DDRMC_PHY_CTRL                                  0x01210080
 115 #define DDRMC_PHY_MASTER_CTRL                           0x0001012a
 116 #define DDRMC_PHY_SLAVE_CTRL                            0x00012020
 117
 118 #define DDRMC_PHY50_DDR3_MODE                           (1 << 12)
 119 #define DDRMC_PHY50_EN_SW_HALF_CYCLE                    (1 << 8)
 120
 121 #define DDRMC_CR00_DRAM_CLASS_DDR3                      (0x6 << 8)
 122 #define DDRMC_CR00_DRAM_CLASS_LPDDR2                    (0x5 << 8)
 123 #define DDRMC_CR00_START                                1
 124 #define DDRMC_CR02_DRAM_TINIT(v)                        ((v) & 0xffffff)
 125 #define DDRMC_CR10_TRST_PWRON(v)                        (v)
 126 #define DDRMC_CR11_CKE_INACTIVE(v)                      (v)
 127 #define DDRMC_CR12_WRLAT(v)                             (((v) & 0x1f) << 8)
 128 #define DDRMC_CR12_CASLAT_LIN(v)                        ((v) & 0x3f)
 129 #define DDRMC_CR13_TRC(v)                               (((v) & 0xff) << 24)
 130 #define DDRMC_CR13_TRRD(v)                              (((v) & 0xff) << 16)
 131 #define DDRMC_CR13_TCCD(v)                              (((v) & 0x1f) << 8)
 132 #define DDRMC_CR13_TBST_INT_INTERVAL(v)                 ((v) & 0x7)
 133 #define DDRMC_CR14_TFAW(v)                              (((v) & 0x3f) << 24)
 134 #define DDRMC_CR14_TRP(v)                               (((v) & 0x1f) << 16)
 135 #define DDRMC_CR14_TWTR(v)                              (((v) & 0xf) << 8)
 136 #define DDRMC_CR14_TRAS_MIN(v)                          ((v) & 0xff)
 137 #define DDRMC_CR16_TMRD(v)                              (((v) & 0x1f) << 24)
 138 #define DDRMC_CR16_TRTP(v)                              (((v) & 0xf) << 16)
 139 #define DDRMC_CR17_TRAS_MAX(v)                          (((v) & 0x1ffff) << 8)
 140 #define DDRMC_CR17_TMOD(v)                              ((v) & 0xff)
 141 #define DDRMC_CR18_TCKESR(v)                            (((v) & 0x1f) << 8)
 142 #define DDRMC_CR18_TCKE(v)                              ((v) & 0x7)
 143 #define DDRMC_CR20_AP_EN                                (1 << 24)
 144 #define DDRMC_CR21_TRCD_INT(v)                          (((v) & 0xff) << 16)
 145 #define DDRMC_CR21_TRAS_LOCKOUT                         (1 << 8)
 146 #define DDRMC_CR21_CCMAP_EN                             1
 147 #define DDRMC_CR22_TDAL(v)                              (((v) & 0x3f) << 16)
 148 #define DDRMC_CR23_BSTLEN(v)                            (((v) & 0x7) << 24)
 149 #define DDRMC_CR23_TDLL(v)                              ((v) & 0xff)
 150 #define DDRMC_CR24_TRP_AB(v)                            ((v) & 0x1f)
 151 #define DDRMC_CR25_TREF_EN                              (1 << 16)
 152 #define DDRMC_CR26_TREF(v)                              (((v) & 0xffff) << 16)
 153 #define DDRMC_CR26_TRFC(v)                              ((v) & 0x3ff)
 154 #define DDRMC_CR28_TREF_INT(v)                          ((v) & 0xffff)
 155 #define DDRMC_CR29_TPDEX(v)                             ((v) & 0xffff)
 156 #define DDRMC_CR30_TXPDLL(v)                            ((v) & 0xffff)
 157 #define DDRMC_CR31_TXSNR(v)                             (((v) & 0xffff) << 16)
 158 #define DDRMC_CR31_TXSR(v)                              ((v) & 0xffff)
 159 #define DDRMC_CR33_EN_QK_SREF                           (1 << 16)
 160 #define DDRMC_CR34_CKSRX(v)                             (((v) & 0xf) << 16)
 161 #define DDRMC_CR34_CKSRE(v)                             (((v) & 0xf) << 8)
 162 #define DDRMC_CR38_FREQ_CHG_EN                          (1 << 8)
 163 #define DDRMC_CR39_PHY_INI_COM(v)                       (((v) & 0xffff) << 16)
 164 #define DDRMC_CR39_PHY_INI_STA(v)                       (((v) & 0xff) << 8)
 165 #define DDRMC_CR39_FRQ_CH_DLLOFF(v)                     ((v) & 0x3)
 166 #define DDRMC_CR41_PHY_INI_STRT_INI_DIS                 1
 167 #define DDRMC_CR48_MR1_DA_0(v)                          (((v) & 0xffff) << 16)
 168 #define DDRMC_CR48_MR0_DA_0(v)                          ((v) & 0xffff)
 169 #define DDRMC_CR66_ZQCL(v)                              (((v) & 0xfff) << 16)
 170 #define DDRMC_CR66_ZQINIT(v)                            ((v) & 0xfff)
 171 #define DDRMC_CR67_ZQCS(v)                              ((v) & 0xfff)
 172 #define DDRMC_CR69_ZQ_ON_SREF_EX(v)                     (((v) & 0xf) << 8)
 173 #define DDRMC_CR70_REF_PER_ZQ(v)                        (v)
 174 #define DDRMC_CR72_ZQCS_ROTATE                          (1 << 24)
 175 #define DDRMC_CR73_APREBIT(v)                           (((v) & 0xf) << 24)
 176 #define DDRMC_CR73_COL_DIFF(v)                          (((v) & 0x7) << 16)
 177 #define DDRMC_CR73_ROW_DIFF(v)                          (((v) & 0x3) << 8)
 178 #define DDRMC_CR74_BANKSPLT_EN                          (1 << 24)
 179 #define DDRMC_CR74_ADDR_CMP_EN                          (1 << 16)
 180 #define DDRMC_CR74_CMD_AGE_CNT(v)                       (((v) & 0xff) << 8)
 181 #define DDRMC_CR74_AGE_CNT(v)                           ((v) & 0xff)
 182 #define DDRMC_CR75_RW_PG_EN                             (1 << 24)
 183 #define DDRMC_CR75_RW_EN                                (1 << 16)
 184 #define DDRMC_CR75_PRI_EN                               (1 << 8)
 185 #define DDRMC_CR75_PLEN                                 1
 186 #define DDRMC_CR76_NQENT_ACTDIS(v)                      (((v) & 0x7) << 24)
 187 #define DDRMC_CR76_D_RW_G_BKCN(v)                       (((v) & 0x3) << 16)
 188 #define DDRMC_CR76_W2R_SPLT_EN                          (1 << 8)
 189 #define DDRMC_CR76_CS_EN                                1
 190 #define DDRMC_CR77_CS_MAP                               (1 << 24)
 191 #define DDRMC_CR77_DI_RD_INTLEAVE                       (1 << 8)
 192 #define DDRMC_CR77_SWAP_EN                              1
 193 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)                    ((v) & 0xf)
 194 #define DDRMC_CR79_CTLUPD_AREF                          (1 << 24)
 195 #define DDRMC_CR82_INT_MASK                             0x1fffffff
 196 #define DDRMC_CR87_ODT_WR_MAPCS0                        (1 << 24)
 197 #define DDRMC_CR87_ODT_RD_MAPCS0                        (1 << 16)
 198 #define DDRMC_CR88_TODTL_CMD(v)                         (((v) & 0x1f) << 16)
 199 #define DDRMC_CR89_AODT_RWSMCS(v)                       ((v) & 0xf)
 200 #define DDRMC_CR91_R2W_SMCSDL(v)                        (((v) & 0x7) << 16)
 201 #define DDRMC_CR96_WLMRD(v)                             (((v) & 0x3f) << 8)
 202 #define DDRMC_CR96_WLDQSEN(v)                           ((v) & 0x3f)
 203 #define DDRMC_CR105_RDLVL_DL_0(v)                       (((v) & 0xff) << 8)
 204 #define DDRMC_CR110_RDLVL_DL_1(v)                       ((v) & 0xff)
 205 #define DDRMC_CR114_RDLVL_GTDL_2(v)                     (((v) & 0xffff) << 8)
 206 #define DDRMC_CR117_AXI0_W_PRI(v)                       (((v) & 0x3) << 8)
 207 #define DDRMC_CR117_AXI0_R_PRI(v)                       ((v) & 0x3)
 208 #define DDRMC_CR118_AXI1_W_PRI(v)                       (((v) & 0x3) << 24)
 209 #define DDRMC_CR118_AXI1_R_PRI(v)                       (((v) & 0x3) << 16)
 210 #define DDRMC_CR120_AXI0_PRI1_RPRI(v)                   (((v) & 0xf) << 24)
 211 #define DDRMC_CR120_AXI0_PRI0_RPRI(v)                   (((v) & 0xf) << 16)
 212 #define DDRMC_CR121_AXI0_PRI3_RPRI(v)                   (((v) & 0xf) << 8)
 213 #define DDRMC_CR121_AXI0_PRI2_RPRI(v)                   ((v) & 0xf)
 214 #define DDRMC_CR122_AXI1_PRI1_RPRI(v)                   (((v) & 0xf) << 24)
 215 #define DDRMC_CR122_AXI1_PRI0_RPRI(v)                   (((v) & 0xf) << 16)
 216 #define DDRMC_CR122_AXI0_PRIRLX(v)                      ((v) & 0x3ff)
 217 #define DDRMC_CR123_AXI1_PRI3_RPRI(v)                   (((v) & 0xf) << 8)
 218 #define DDRMC_CR123_AXI1_PRI2_RPRI(v)                   ((v) & 0xf)
 219 #define DDRMC_CR124_AXI1_PRIRLX(v)                      ((v) & 0x3ff)
 220 #define DDRMC_CR126_PHY_RDLAT(v)                        (((v) & 0x3f) << 8)
 221 #define DDRMC_CR132_WRLAT_ADJ(v)                        (((v) & 0x1f) << 8)
 222 #define DDRMC_CR132_RDLAT_ADJ(v)                        ((v) & 0x3f)
 223 #define DDRMC_CR139_PHY_WRLV_RESPLAT(v)                 (((v) & 0xff) << 24)
 224 #define DDRMC_CR139_PHY_WRLV_LOAD(v)                    (((v) & 0xff) << 16)
 225 #define DDRMC_CR139_PHY_WRLV_DLL(v)                     (((v) & 0xff) << 8)
 226 #define DDRMC_CR139_PHY_WRLV_EN(v)                      ((v) & 0xff)
 227 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)        (((v) & 0x1f) << 27)
 228 #define DDRMC_CR154_PAD_ZQ_MODE(v)                      (((v) & 0x3) << 21)
 229 #define DDRMC_CR155_AXI0_AWCACHE                        (1 << 10)
 230 #define DDRMC_CR155_PAD_ODT_BYTE1(v)                    ((v) & 0x7)
 231 #define DDRMC_CR158_TWR(v)                              ((v) & 0x3f)
 232
 233 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 234 #include <asm/types.h>
 235
 236 /* System Reset Controller (SRC) */
 237 struct src {
 238         u32 scr;
 239         u32 sbmr1;
 240         u32 srsr;
 241         u32 secr;
 242         u32 gpsr;
 243         u32 sicr;
 244         u32 simr;
 245         u32 sbmr2;
 246         u32 gpr0;
 247         u32 gpr1;
 248         u32 gpr2;
 249         u32 gpr3;
 250         u32 gpr4;
 251         u32 hab0;
 252         u32 hab1;
 253         u32 hab2;
 254         u32 hab3;
 255         u32 hab4;
 256         u32 hab5;
 257         u32 misc0;
 258         u32 misc1;
 259         u32 misc2;
 260         u32 misc3;
 261 };
 262
 263 /* Periodic Interrupt Timer (PIT) */
 264 struct pit_reg {
 265         u32 mcr;
 266         u32 recv0[55];
 267         u32 ltmr64h;
 268         u32 ltmr64l;
 269         u32 recv1[6];
 270         u32 ldval0;
 271         u32 cval0;
 272         u32 tctrl0;
 273         u32 tflg0;
 274         u32 ldval1;
 275         u32 cval1;
 276         u32 tctrl1;
 277         u32 tflg1;
 278         u32 ldval2;
 279         u32 cval2;
 280         u32 tctrl2;
 281         u32 tflg2;
 282         u32 ldval3;
 283         u32 cval3;
 284         u32 tctrl3;
 285         u32 tflg3;
 286         u32 ldval4;
 287         u32 cval4;
 288         u32 tctrl4;
 289         u32 tflg4;
 290         u32 ldval5;
 291         u32 cval5;
 292         u32 tctrl5;
 293         u32 tflg5;
 294         u32 ldval6;
 295         u32 cval6;
 296         u32 tctrl6;
 297         u32 tflg6;
 298         u32 ldval7;
 299         u32 cval7;
 300         u32 tctrl7;
 301         u32 tflg7;
 302 };
 303
 304 /* Watchdog Timer (WDOG) */
 305 struct wdog_regs {
 306         u16 wcr;
 307         u16 wsr;
 308         u16 wrsr;
 309         u16 wicr;
 310         u16 wmcr;
 311 };
 312
 313 /* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
 314 struct ddrmr_regs {
 315         u32 cr[162];
 316         u32 rsvd[94];
 317         u32 phy[53];
 318 };
 319
 320 /* On-Chip One Time Programmable Controller (OCOTP) */
 321 struct ocotp_regs {
 322         u32 ctrl;
 323         u32 ctrl_set;
 324         u32 ctrl_clr;
 325         u32 ctrl_tog;
 326         u32 timing;
 327         u32 rsvd0[3];
 328         u32 data;
 329         u32 rsvd1[3];
 330         u32 read_ctrl;
 331         u32 rsvd2[3];
 332         u32 read_fuse_data;
 333         u32 rsvd3[7];
 334         u32 scs;
 335         u32 scs_set;
 336         u32 scs_clr;
 337         u32 scs_tog;
 338         u32 crc_addr;
 339         u32 rsvd4[3];
 340         u32 crc_value;
 341         u32 rsvd5[3];
 342         u32 version;
 343         u32 rsvd6[0xdb];
 344
 345         struct fuse_bank {
 346                 u32 fuse_regs[0x20];
 347         } bank[16];
 348 };
 349
 350 struct fuse_bank0_regs {
 351         u32 lock;
 352         u32 rsvd0[3];
 353         u32 uid_low;
 354         u32 rsvd1[3];
 355         u32 uid_high;
 356         u32 rsvd2[0x17];
 357 };
 358
 359 struct fuse_bank4_regs {
 360         u32 sjc_resp0;
 361         u32 rsvd0[3];
 362         u32 sjc_resp1;
 363         u32 rsvd1[3];
 364         u32 mac_addr0;
 365         u32 rsvd2[3];
 366         u32 mac_addr1;
 367         u32 rsvd3[3];
 368         u32 mac_addr2;
 369         u32 rsvd4[3];
 370         u32 mac_addr3;
 371         u32 rsvd5[3];
 372         u32 gp1;
 373         u32 rsvd6[3];
 374         u32 gp2;
 375         u32 rsvd7[3];
 376 };
 377
 378 /* UART */
 379 struct lpuart_fsl {
 380         u8 ubdh;
 381         u8 ubdl;
 382         u8 uc1;
 383         u8 uc2;
 384         u8 us1;
 385         u8 us2;
 386         u8 uc3;
 387         u8 ud;
 388         u8 uma1;
 389         u8 uma2;
 390         u8 uc4;
 391         u8 uc5;
 392         u8 ued;
 393         u8 umodem;
 394         u8 uir;
 395         u8 reserved;
 396         u8 upfifo;
 397         u8 ucfifo;
 398         u8 usfifo;
 399         u8 utwfifo;
 400         u8 utcfifo;
 401         u8 urwfifo;
 402         u8 urcfifo;
 403         u8 rsvd[28];
 404 };
 405
 406 /* MSCM Interrupt Router */
 407 struct mscm_ir {
 408         u32 ircp0ir;
 409         u32 ircp1ir;
 410         u32 rsvd1[6];
 411         u32 ircpgir;
 412         u32 rsvd2[23];
 413         u16 irsprc[112];
 414         u16 rsvd3[848];
 415 };
 416
 417 #endif  /* __ASSEMBLER__*/
 418
 419 #endif  /* __ASM_ARCH_IMX_REGS_H__ */