arch/arm/include/asm/arch-zynq/hardware.h

   1 /*
   2  * Copyright (c) 2013 Xilinx Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ASM_ARCH_HARDWARE_H
   8 #define _ASM_ARCH_HARDWARE_H
   9
  10 #define ZYNQ_SYS_CTRL_BASEADDR          0xF8000000
  11 #define ZYNQ_DEV_CFG_APB_BASEADDR       0xF8007000
  12 #define ZYNQ_SCU_BASEADDR               0xF8F00000
  13 #define ZYNQ_SCUTIMER_BASEADDR          0xF8F00600
  14 #define ZYNQ_GEM_BASEADDR0              0xE000B000
  15 #define ZYNQ_GEM_BASEADDR1              0xE000C000
  16 #define ZYNQ_SDHCI_BASEADDR0            0xE0100000
  17 #define ZYNQ_SDHCI_BASEADDR1            0xE0101000
  18 #define ZYNQ_I2C_BASEADDR0              0xE0004000
  19 #define ZYNQ_I2C_BASEADDR1              0xE0005000
  20 #define ZYNQ_DDRC_BASEADDR              0xF8006000
  21
  22 /* Reflect slcr offsets */
  23 struct slcr_regs {
  24         u32 scl; /* 0x0 */
  25         u32 slcr_lock; /* 0x4 */
  26         u32 slcr_unlock; /* 0x8 */
  27         u32 reserved0[75];
  28         u32 gem0_rclk_ctrl; /* 0x138 */
  29         u32 gem1_rclk_ctrl; /* 0x13c */
  30         u32 gem0_clk_ctrl; /* 0x140 */
  31         u32 gem1_clk_ctrl; /* 0x144 */
  32         u32 reserved1[46];
  33         u32 pss_rst_ctrl; /* 0x200 */
  34         u32 reserved2[15];
  35         u32 fpga_rst_ctrl; /* 0x240 */
  36         u32 reserved3[5];
  37         u32 reboot_status; /* 0x258 */
  38         u32 boot_mode; /* 0x25c */
  39         u32 reserved4[116];
  40         u32 trust_zone; /* 0x430 */ /* FIXME */
  41         u32 reserved5_1[63];
  42         u32 pss_idcode; /* 0x530 */
  43         u32 reserved5_2[51];
  44         u32 ddr_urgent; /* 0x600 */
  45         u32 reserved6[6];
  46         u32 ddr_urgent_sel; /* 0x61c */
  47         u32 reserved7[56];
  48         u32 mio_pin[54]; /* 0x700 - 0x7D4 */
  49         u32 reserved8[74];
  50         u32 lvl_shftr_en; /* 0x900 */
  51         u32 reserved9[3];
  52         u32 ocm_cfg; /* 0x910 */
  53 };
  54
  55 #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
  56
  57 struct devcfg_regs {
  58         u32 ctrl; /* 0x0 */
  59         u32 lock; /* 0x4 */
  60         u32 cfg; /* 0x8 */
  61         u32 int_sts; /* 0xc */
  62         u32 int_mask; /* 0x10 */
  63         u32 status; /* 0x14 */
  64         u32 dma_src_addr; /* 0x18 */
  65         u32 dma_dst_addr; /* 0x1c */
  66         u32 dma_src_len; /* 0x20 */
  67         u32 dma_dst_len; /* 0x24 */
  68         u32 rom_shadow; /* 0x28 */
  69         u32 reserved1[2];
  70         u32 unlock; /* 0x34 */
  71         u32 reserved2[18];
  72         u32 mctrl; /* 0x80 */
  73         u32 reserved3;
  74         u32 write_count; /* 0x88 */
  75         u32 read_count; /* 0x8c */
  76 };
  77
  78 #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
  79
  80 struct scu_regs {
  81         u32 reserved1[16];
  82         u32 filter_start; /* 0x40 */
  83         u32 filter_end; /* 0x44 */
  84 };
  85
  86 #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
  87
  88 struct ddrc_regs {
  89         u32 ddrc_ctrl; /* 0x0 */
  90         u32 reserved[60];
  91         u32 ecc_scrub; /* 0xF4 */
  92 };
  93 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
  94
  95 #endif /* _ASM_ARCH_HARDWARE_H */