arch/arm/include/asm/arch-zynqmp/hardware.h

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _ASM_ARCH_HARDWARE_H
   9 #define _ASM_ARCH_HARDWARE_H
  10
  11 #define ZYNQ_SERIAL_BASEADDR0   0xFF000000
  12 #define ZYNQ_SERIAL_BASEADDR1   0xFF001000
  13
  14 #define ZYNQ_GEM_BASEADDR0      0xFF0B0000
  15 #define ZYNQ_GEM_BASEADDR1      0xFF0C0000
  16 #define ZYNQ_GEM_BASEADDR2      0xFF0D0000
  17 #define ZYNQ_GEM_BASEADDR3      0xFF0E0000
  18
  19 #define ZYNQ_SPI_BASEADDR0      0xFF040000
  20 #define ZYNQ_SPI_BASEADDR1      0xFF050000
  21
  22 #define ZYNQ_I2C_BASEADDR0      0xFF020000
  23 #define ZYNQ_I2C_BASEADDR1      0xFF030000
  24
  25 #define ZYNQ_SDHCI_BASEADDR0    0xFF160000
  26 #define ZYNQ_SDHCI_BASEADDR1    0xFF170000
  27
  28 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
  29 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT        0x1000000
  30
  31 struct crlapb_regs {
  32         u32 reserved0[36];
  33         u32 cpu_r5_ctrl; /* 0x90 */
  34         u32 reserved1[37];
  35         u32 timestamp_ref_ctrl; /* 0x128 */
  36         u32 reserved2[53];
  37         u32 boot_mode; /* 0x200 */
  38         u32 reserved3[14];
  39         u32 rst_lpd_top; /* 0x23C */
  40         u32 reserved4[26];
  41 };
  42
  43 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
  44
  45 #define ZYNQMP_IOU_SCNTR        0xFF250000
  46 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN    0x1
  47 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG  0x2
  48
  49 struct iou_scntr {
  50         u32 counter_control_register;
  51         u32 reserved0[7];
  52         u32 base_frequency_id_register;
  53 };
  54
  55 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
  56
  57 /* Bootmode setting values */
  58 #define BOOT_MODES_MASK 0x0000000F
  59 #define SD_MODE         0x00000003
  60 #define EMMC_MODE       0x00000006
  61 #define JTAG_MODE       0x00000000
  62
  63 #define ZYNQMP_IOU_SLCR_BASEADDR        0xFF180000
  64
  65 struct iou_slcr_regs {
  66         u32 mio_pin[78];
  67         u32 reserved[442];
  68 };
  69
  70 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
  71
  72 #define ZYNQMP_RPU_BASEADDR     0xFF9A0000
  73
  74 struct rpu_regs {
  75         u32 rpu_glbl_ctrl;
  76         u32 reserved0[63];
  77         u32 rpu0_cfg; /* 0x100 */
  78         u32 reserved1[63];
  79         u32 rpu1_cfg; /* 0x200 */
  80 };
  81
  82 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
  83
  84 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
  85
  86 struct crfapb_regs {
  87         u32 reserved0[65];
  88         u32 rst_fpd_apu; /* 0x104 */
  89         u32 reserved1;
  90 };
  91
  92 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
  93
  94 #define ZYNQMP_APU_BASEADDR     0xFD5C0000
  95
  96 struct apu_regs {
  97         u32 reserved0[16];
  98         u32 rvbar_addr0_l; /* 0x40 */
  99         u32 rvbar_addr0_h; /* 0x44 */
 100         u32 reserved1[20];
 101 };
 102
 103 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
 104
 105 /* Board version value */
 106 #define ZYNQMP_CSU_VERSION_SILICON      0x0
 107 #define ZYNQMP_CSU_VERSION_EP108        0x1
 108 #define ZYNQMP_CSU_VERSION_VELOCE       0x2
 109 #define ZYNQMP_CSU_VERSION_QEMU         0x3
 110
 111 #endif /* _ASM_ARCH_HARDWARE_H */