arch/arm/include/asm/arch-zynqmp/hardware.h

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _ASM_ARCH_HARDWARE_H
   9 #define _ASM_ARCH_HARDWARE_H
  10
  11 #define ZYNQ_GEM_BASEADDR0      0xFF0B0000
  12 #define ZYNQ_GEM_BASEADDR1      0xFF0C0000
  13 #define ZYNQ_GEM_BASEADDR2      0xFF0D0000
  14 #define ZYNQ_GEM_BASEADDR3      0xFF0E0000
  15
  16 #define ZYNQ_SPI_BASEADDR0      0xFF040000
  17 #define ZYNQ_SPI_BASEADDR1      0xFF050000
  18
  19 #define ZYNQ_I2C_BASEADDR0      0xFF020000
  20 #define ZYNQ_I2C_BASEADDR1      0xFF030000
  21
  22 #define ZYNQMP_SATA_BASEADDR    0xFD0C0000
  23
  24 #define ZYNQMP_USB0_XHCI_BASEADDR       0xFE200000
  25 #define ZYNQMP_USB1_XHCI_BASEADDR       0xFE300000
  26
  27 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
  28 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT        0x1000000
  29
  30 struct crlapb_regs {
  31         u32 reserved0[36];
  32         u32 cpu_r5_ctrl; /* 0x90 */
  33         u32 reserved1[37];
  34         u32 timestamp_ref_ctrl; /* 0x128 */
  35         u32 reserved2[53];
  36         u32 boot_mode; /* 0x200 */
  37         u32 reserved3[14];
  38         u32 rst_lpd_top; /* 0x23C */
  39         u32 reserved4[26];
  40 };
  41
  42 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
  43
  44 #if defined(CONFIG_SECURE_IOU)
  45 #define ZYNQMP_IOU_SCNTR        0xFF260000
  46 #else
  47 #define ZYNQMP_IOU_SCNTR        0xFF250000
  48 #endif
  49 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN    0x1
  50 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG  0x2
  51
  52 struct iou_scntr {
  53         u32 counter_control_register;
  54         u32 reserved0[7];
  55         u32 base_frequency_id_register;
  56 };
  57
  58 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
  59
  60 /* Bootmode setting values */
  61 #define BOOT_MODES_MASK 0x0000000F
  62 #define SD_MODE         0x00000003
  63 #define EMMC_MODE       0x00000006
  64 #define JTAG_MODE       0x00000000
  65
  66 #define ZYNQMP_IOU_SLCR_BASEADDR        0xFF180000
  67
  68 struct iou_slcr_regs {
  69         u32 mio_pin[78];
  70         u32 reserved[442];
  71 };
  72
  73 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
  74
  75 #define ZYNQMP_RPU_BASEADDR     0xFF9A0000
  76
  77 struct rpu_regs {
  78         u32 rpu_glbl_ctrl;
  79         u32 reserved0[63];
  80         u32 rpu0_cfg; /* 0x100 */
  81         u32 reserved1[63];
  82         u32 rpu1_cfg; /* 0x200 */
  83 };
  84
  85 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
  86
  87 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
  88
  89 struct crfapb_regs {
  90         u32 reserved0[65];
  91         u32 rst_fpd_apu; /* 0x104 */
  92         u32 reserved1;
  93 };
  94
  95 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
  96
  97 #define ZYNQMP_APU_BASEADDR     0xFD5C0000
  98
  99 struct apu_regs {
 100         u32 reserved0[16];
 101         u32 rvbar_addr0_l; /* 0x40 */
 102         u32 rvbar_addr0_h; /* 0x44 */
 103         u32 reserved1[20];
 104 };
 105
 106 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
 107
 108 /* Board version value */
 109 #define ZYNQMP_CSU_VERSION_SILICON      0x0
 110 #define ZYNQMP_CSU_VERSION_EP108        0x1
 111 #define ZYNQMP_CSU_VERSION_VELOCE       0x2
 112 #define ZYNQMP_CSU_VERSION_QEMU         0x3
 113
 114 #endif /* _ASM_ARCH_HARDWARE_H */