arch/arm/include/asm/armv7.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  * Aneesh V <aneesh@ti.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8 #ifndef ARMV7_H
   9 #define ARMV7_H
  10
  11 /* Cortex-A9 revisions */
  12 #define MIDR_CORTEX_A9_R0P1     0x410FC091
  13 #define MIDR_CORTEX_A9_R1P2     0x411FC092
  14 #define MIDR_CORTEX_A9_R1P3     0x411FC093
  15 #define MIDR_CORTEX_A9_R2P10    0x412FC09A
  16
  17 /* Cortex-A15 revisions */
  18 #define MIDR_CORTEX_A15_R0P0    0x410FC0F0
  19 #define MIDR_CORTEX_A15_R2P2    0x412FC0F2
  20
  21 /* Cortex-A7 revisions */
  22 #define MIDR_CORTEX_A7_R0P0     0x410FC070
  23
  24 #define MIDR_PRIMARY_PART_MASK  0xFF0FFFF0
  25
  26 /* ID_PFR1 feature fields */
  27 #define CPUID_ARM_SEC_SHIFT             4
  28 #define CPUID_ARM_SEC_MASK              (0xF << CPUID_ARM_SEC_SHIFT)
  29 #define CPUID_ARM_VIRT_SHIFT            12
  30 #define CPUID_ARM_VIRT_MASK             (0xF << CPUID_ARM_VIRT_SHIFT)
  31 #define CPUID_ARM_GENTIMER_SHIFT        16
  32 #define CPUID_ARM_GENTIMER_MASK         (0xF << CPUID_ARM_GENTIMER_SHIFT)
  33
  34 /* valid bits in CBAR register / PERIPHBASE value */
  35 #define CBAR_MASK                       0xFFFF8000
  36
  37 /* CCSIDR */
  38 #define CCSIDR_LINE_SIZE_OFFSET         0
  39 #define CCSIDR_LINE_SIZE_MASK           0x7
  40 #define CCSIDR_ASSOCIATIVITY_OFFSET     3
  41 #define CCSIDR_ASSOCIATIVITY_MASK       (0x3FF << 3)
  42 #define CCSIDR_NUM_SETS_OFFSET          13
  43 #define CCSIDR_NUM_SETS_MASK            (0x7FFF << 13)
  44
  45 /*
  46  * Values for InD field in CSSELR
  47  * Selects the type of cache
  48  */
  49 #define ARMV7_CSSELR_IND_DATA_UNIFIED   0
  50 #define ARMV7_CSSELR_IND_INSTRUCTION    1
  51
  52 /* Values for Ctype fields in CLIDR */
  53 #define ARMV7_CLIDR_CTYPE_NO_CACHE              0
  54 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY      1
  55 #define ARMV7_CLIDR_CTYPE_DATA_ONLY             2
  56 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA      3
  57 #define ARMV7_CLIDR_CTYPE_UNIFIED               4
  58
  59 #ifndef __ASSEMBLY__
  60 #include <linux/types.h>
  61 #include <asm/io.h>
  62
  63 /*
  64  * CP15 Barrier instructions
  65  * Please note that we have separate barrier instructions in ARMv7
  66  * However, we use the CP15 based instructtions because we use
  67  * -march=armv5 in U-Boot
  68  */
  69 #define CP15ISB asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
  70 #define CP15DSB asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
  71 #define CP15DMB asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
  72
  73 #ifdef __ARM_ARCH_7A__
  74 #define ISB     asm volatile ("isb" : : : "memory")
  75 #define DSB     asm volatile ("dsb" : : : "memory")
  76 #define DMB     asm volatile ("dmb" : : : "memory")
  77 #else
  78 #define ISB     CP15ISB
  79 #define DSB     CP15DSB
  80 #define DMB     CP15DMB
  81 #endif
  82
  83 /*
  84  * Workaround for ARM errata # 798870
  85  * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
  86  * stalled for 1024 cycles to verify that its hazard condition still exists.
  87  */
  88 static inline void v7_enable_l2_hazard_detect(void)
  89 {
  90         uint32_t val;
  91
  92         /* L2ACTLR[7]: Enable hazard detect timeout */
  93         asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
  94         val |= (1 << 7);
  95         asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
  96 }
  97
  98 /*
  99  * Workaround for ARM errata # 799270
 100  * Ensure that the L2 logic has been used within the previous 256 cycles
 101  * before modifying the ACTLR.SMP bit. This is required during boot before
 102  * MMU has been enabled, or during a specified reset or power down sequence.
 103  */
 104 static inline void v7_enable_smp(uint32_t address)
 105 {
 106         uint32_t temp, val;
 107
 108         /* Read auxiliary control register */
 109         asm volatile ("mrc     p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
 110
 111         /* Enable SMP */
 112         val |= (1 << 6);
 113
 114         /* Dummy read to assure L2 access */
 115         temp = readl(address);
 116         temp &= 0;
 117         val |= temp;
 118
 119         /* Write auxiliary control register */
 120         asm volatile ("mcr     p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
 121
 122         CP15DSB;
 123         CP15ISB;
 124 }
 125
 126 void v7_en_l2_hazard_detect(void);
 127 void v7_outer_cache_enable(void);
 128 void v7_outer_cache_disable(void);
 129 void v7_outer_cache_flush_all(void);
 130 void v7_outer_cache_inval_all(void);
 131 void v7_outer_cache_flush_range(u32 start, u32 end);
 132 void v7_outer_cache_inval_range(u32 start, u32 end);
 133
 134 #ifdef CONFIG_ARMV7_NONSEC
 135
 136 int armv7_init_nonsec(void);
 137 int armv7_apply_memory_carveout(u64 *start, u64 *size);
 138 bool armv7_boot_nonsec(void);
 139
 140 /* defined in assembly file */
 141 unsigned int _nonsec_init(void);
 142 void _do_nonsec_entry(void *target_pc, unsigned long r0,
 143                       unsigned long r1, unsigned long r2);
 144 void _smp_pen(void);
 145
 146 extern char __secure_start[];
 147 extern char __secure_end[];
 148
 149 #endif /* CONFIG_ARMV7_NONSEC */
 150
 151 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 152                                  u32 cpu_rev_comb, u32 cpu_variant,
 153                                  u32 cpu_rev);
 154 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 155                           u32 cpu_variant, u32 cpu_rev);
 156 #endif /* ! __ASSEMBLY__ */
 157
 158 #endif